JP3050896B2 - High definition receiver - Google Patents

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial application field) The present invention relates to a high-vision receiver capable of receiving and processing an analog MUSE signal and a digital MUSE signal, and particularly pays attention to a synchronization circuit thereof. .

(Conventional example) MUSE (multiplesub-Nyquist)
A sampuling encoding method has been developed. This method is disclosed in JP-A-61-264889, Nikkei Electronics
1987.11.2 P189 to P211.

In the MUSE system, the sampling clock is not transmitted from the encoder side, and the decoder reproduces the clock using a synchronization signal. FIG. 8 shows a frame format of a signal in the MUSE system. In the figure
The area described as VITS is an area to which a vertical interval test signal is allocated, the area described as a frame pulse is an area to which a frame pulse signal having a predetermined pattern is allocated, and the area described as a C image is a color. The area where the signal is compressed and assigned, and the area described as Y video is the area where the video signal is allocated. The area described as HD is an area to which a horizontal synchronization signal is assigned.

The HD signal is inserted for each line as shown in FIG. 9, and the decoder reproduces the sampling clock based on this signal. This circuit is called a synchronous reproduction circuit.

 FIG. 7 shows a conventional synchronous reproduction circuit.

An analog MUSE signal is supplied to an input terminal 1 and digitized by an analog / digital (A / D) converter 2. The digitized MUSE signal is output to the phase error detection circuit 3
, Where the phase error of the horizontal synchronization signal is detected. As shown in FIG. 9, the horizontal synchronization signal has a predetermined phase detection point (HD point). Therefore, if the sampling signal obtained at this HD point is not a predetermined value, it means that the phase of the sampling pulse is shifted, and the error output is output via the filter 4 to the digital / analog (D / A) converter 5. Is input to The output of the digital-to-analog converter 5 is a voltage controlled oscillator 6 using quartz.
Is supplied to the control terminal. The oscillation output of the voltage controlled oscillator 6 is used as a sampling clock,
Used as a pulse to create an internal frame pulse. That is, it is supplied to the horizontal counter 8. The horizontal counter 8 obtains the horizontal address of each line, and the line count output is also supplied to the vertical counter 9. The vertical counter 9 obtains a vertical address,
An internal frame pulse corresponding to an external frame pulse generated based on a frame pulse signal having a predetermined pattern is generated.

The internal frame pulse is input to the window width setting circuit 10. The window width setting circuit 10 is a circuit for setting the pulse width of the internal frame pulse slightly wider than the pulse width of the external frame pulse. The internal frame pulse output from the window width setting circuit 10 is input to one input terminal of the out-of-sync detection circuit 11. On the other hand, the output of the analog-to-digital converter 2 is input to the frame pulse detection circuit 7,
Here, a frame pulse signal having a predetermined pattern is detected, and an external frame pulse having a predetermined pulse width is output. This external frame pulse is supplied to the other input terminal of the out-of-sync detection circuit 11.

The out-of-synchronization detection circuit 11 detects whether or not the pulse of the external frame pulse exists within the pulse width of the internal frame pulse. obtain. In the out-of-synchronization state, the filter 4, the horizontal counter 8, and the vertical counter 9 are reset by the detection signal, and set to the initial state. As a result, the synchronization pull-in is started from the beginning.

(Problems to be Solved by the Invention) Recently, with the advance of digital technology, there is a possibility that a receiver having a digital input unit will appear even in a high-vision receiver. In other words, a conventional system in which the digital MUSE signal on the encoder side is directly introduced into the decoder side can be considered. In such a system, signal processing can be performed without passing through the analog-to-digital converter 2.

FIG. 6 is an example of a synchronous reproduction circuit that can be considered when a MUSE receiver provided with a digital input unit is considered.

In addition to the configuration of FIG. 7, a digital input unit 12, a switch
13 and 16, a phase error detection circuit 14, and a filter 15 are added. A digital MUSE signal is supplied to a terminal M of the digital input unit 12, and a clock is supplied to a terminal CK. The clock is supplied to the phase error detection circuit 14. The phase error detection circuit 14 detects the phase error of the clock and supplies it to the filter 15. The output of the filter 15 is supplied to one input terminal D of the switch 16. This switch 16 is an analog MUSE
When the signal is received, the output from the digital-to-analog converter 5 is selected, and when the digital MUSE signal is received, the output of the filter 15 is selected. The output of the switch 16 is supplied to the control terminal of the voltage controlled oscillator 6. The output of the voltage controlled oscillator 6 is used as a sampling clock.

When detecting the phase error of the sampling clock, the HD signal is used when the analog MUSE signal is being processed, and the clock is used when the digital MUSE signal is being processed. This is because, even when processing the digital MUSE signal, the HD pulse may be used, but if the clock is used directly, the pull-in speed can be obtained faster. Therefore, in this case, the phase error detection circuit 14,
A filter 15 and a switch 16 are required.

The switch 13 selects the output of the analog-to-digital converter 2 when the analog MUSE signal is processed, and selects the input terminal M when the digital MUSE signal is processed. Then, the selected output is supplied to the frame pulse detection circuit 7.

According to the above-described synchronous reproduction circuit, since a clock is used as a synchronization reference, there is an advantage that when a digital MUSE signal is processed, synchronization is quickly pulled in and the input signal is resistant to jitter.

However, if the clock is lost momentarily in the synchronized state or if noise jumps into the control voltage of the voltage controlled oscillator,
Clock synchronization will be momentarily lost. However, even if clock synchronization is lost, this system cannot detect an out-of-synchronization state because the pulse width of the internal frame pulse is slightly wider than the external frame pulse. That is, for example, even if the clock synchronization is momentarily lost and the internal frame pulse deviates from the predetermined phase relationship of the external frame pulse (of the digital MUSE signal) by ± 1 clock, the loss of synchronization is not detected. In such a case, even if the synchronization of the clock is pulled in, the internal frame pulse and the external frame pulse remain out of phase with each other, and the loss of synchronization cannot be detected. At the time of processing an analog MUSE signal, in the case of an HD signal, there is no problem because the signal is drawn to the HD point.
Even if the period clock is shifted, the state is synchronized. Moreover, at this time, if a phase shift occurs between the internal frame pulse and the external frame pulse, the video processing is not performed at the correct timing, causing a problem such as a shift between the color signal phase and the luminance signal phase.

Accordingly, an object of the present invention is to provide a high-vision receiver capable of reliably detecting out-of-synchronism even during digital MUSE signal processing.

[Structure of the Invention] (Means for Solving the Problems) (1) The present invention relates to an analog-to-digital conversion means for digitizing an analog MUSE signal, which is a high-definition transmission system, and outputting it as a first MUSE signal; An external frame created based on an external signal in a synchronous reproduction circuit of a receiver having a digital MUSE signal input section in which a signal is supplied as a second MUSE signal and capable of synchronizing with any of the MUSE signals When detecting a loss of synchronization by comparing the pulse with an internally generated internal frame pulse, the pulse width of the internal frame pulse is narrower during the second MUSE signal processing than during the first MUSE signal processing. Means.

(Operation) By the above means, the accuracy of the out-of-synchronization detection function at the time of digital MUSE signal processing is improved, and it can always contribute to obtaining a normal reproduced image.

(2) The present invention further provides an analog-to-digital conversion means for digitizing an analog MUSE signal, which is a transmission method of Hi-Vision, and outputting it as a first MUSE signal;
Digital MUSE where SE signal is supplied as second MUSE signal
In the synchronous reproduction circuit of the receiver having a signal input unit and capable of synchronizing with any of the MUSE signals, in the second MUSE signal processing, the means for resetting the counting means includes an output signal of the out-of-synchronization detecting means or Second MU
The reset pulse is generated by using the horizontal synchronization pulse of the SE signal itself.

(Operation) By the above means, the synchronization pull-in operation at the time of the digital MUSE signal processing pulls in the correct phase, which can always contribute to obtaining a normal reproduced image.

(3) The present invention further provides an analog-to-digital converter for digitizing an analog MUSE signal, which is a transmission method of Hi-Vision, and outputting it as a first MUSE signal;
Digital MUSE where SE signal is supplied as second MUSE signal
In a synchronous reproduction circuit of a receiver having a signal input unit and capable of synchronizing with any of the MUSE signals, at the time of the second MUSE signal processing, the internal clock is compared with the internal clock by comparing the phase of the external clock with the internal clock. Means for controlling the oscillating means, and means for controlling the internal oscillating means by comparing the phases of the horizontal synchronizing pulse and the internal horizontal synchronizing pulse when a stable state is attained.

(Operation) According to the above-mentioned means, at the time of digital MUSE signal processing, high-speed pull-in is possible because of clock phase comparison, and when a stable state is reached, the phase is controlled by a horizontal synchronization pulse, so that it is affected by jitters and the like. And can always contribute to obtaining normal image reproduction.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. The input terminal 31 is supplied with an HD signal and an analog MUSE signal including a frame pulse signal having a predetermined pattern, and is digitized by an analog / digital (A / D) converter 32. The digitized MUSE signal is input to the phase error detection circuit 33,
Here, the phase error of the horizontal synchronization (HD) signal is detected.
As shown in FIG. 9, the horizontal synchronization signal has a predetermined phase detection point (HD point). Therefore, if the sampling signal obtained at this HD point is not a predetermined value, it means that the phase of the sampling pulse is shifted, and the error output is output via the filter 34 to the digital-to-analog (D / A) converter 35. Is input to The output of the digital-to-analog converter 35 is supplied to one terminal of the switch 51. The switch 51 selects the terminal 51A when processing an analog MUSE signal, and selects the other terminal 51D when processing a digital MUSE signal. A switching signal for this selection is supplied from a terminal 43. An error signal from the filter 45 is supplied to the terminal 51D. Filter 45
Is supplied with a clock phase error output from the phase error detection circuit 44. The phase error detection circuit 44 detects a phase error of the clock supplied to the clock input terminal of the digital input unit 42.

The output of switch 51 is a voltage controlled oscillator 36 using crystal.
Is supplied to the control terminal. The oscillation output of the voltage controlled oscillator 36 is used as a sampling clock,
Used as a pulse to create an internal frame pulse. That is, it is supplied to the horizontal counter 38. The horizontal counter 38 obtains the horizontal address of each line, and the line count output is also supplied to the vertical counter 39. The vertical counter 39 obtains a vertical address,
An internal frame pulse corresponding to an external frame pulse generated based on a frame pulse signal having a predetermined pattern is generated.

The internal frame pulse is input to the window width setting circuit 40. This window width setting circuit 40 can set the pulse width of the internal frame pulse to be slightly wider than the pulse width of the external frame pulse, or can set the same pulse width as the external frame pulse. The switching of the pulse width is controlled by a switching signal supplied from a terminal 43,
When processing the analog MUSE signal, set the pulse width of the internal frame pulse to be slightly wider than the pulse width of the external frame pulse, and when processing the digital MUSE signal,
The pulse width of the internal frame pulse is set to the same pulse width as the external frame pulse.

The internal frame pulse output from the window width setting circuit 40 is input to one input terminal of the out-of-sync detection circuit 41.

Further, the output of the analog-to-digital converter 32 is supplied to one input terminal 52A of the switch 52. This switch 5
The digital MUSE signal from the digital input section 42 is supplied to the other input terminal 52D of the second. The switch 52 is controlled by a switching signal from the terminal 43 so as to select the terminal 52A when processing an analog MUSE signal and to select 52D when processing a digital MUSE signal.

The output of the switch 52 is input to the frame pulse detection circuit 37, where a frame pulse having a predetermined pattern is detected, and an external frame pulse having a predetermined pulse width is output. This external frame pulse is supplied to the other input terminal of the out-of-sync detection circuit 41.

The out-of-synchronization detection circuit 41 detects whether or not the pulse of the external frame pulse is within the pulse width of the internal frame pulse. A detection signal is obtained as a state. In the out-of-synchronization state, the filter 34, the horizontal counter 38, and the vertical counter 39 are reset by the detection signal, and set to the initial state. As a result, the synchronization pull-in is started from the beginning.

FIG. 2 shows the window width setting circuit 40 and the out-of-synchronization detecting circuit 41.
Are specifically shown.

The output (vertical synchronization pulse) from the vertical counter 39 is supplied to the input terminal 401. This pulse is supplied to the load terminal of the 4-bit counter 402. Data is supplied from the switch 403 to the data input terminal of the counter 402. The switch 403 is controlled by a switching signal from the terminal 43, selects data AD from the terminal A when the analog MUSE signal is processed, and selects data DD from the terminal D when the digital MUSE signal is processed. It is controlled to select and output. The carry of the counter 402 is supplied to an enable terminal of the counter via an inverter 404, and is input to the out-of-sync detection circuit 41 as an internal frame pulse. Therefore, when a vertical sync pulse is input,
Data is loaded into the counter 402, and a carry is obtained when the count of the clock advances. Where the data
AD is, for example, a value at which a carry is obtained when three clocks are counted, and data DD is set to a value at which a carry is obtained when one clock is counted. In other words, when processing analog MUSE signals,
Since the time until the carry is obtained is long, the pulse width of the internal frame pulse is wide, and when the digital MUSE signal is processed, the time until the carry is obtained is short, so that the pulse width of the internal frame pulse is short.

The internal frame pulse is supplied to one input terminal of the NAND circuit 411 of the out-of-sync detection circuit 41 and the clock input terminal of the counter 412. An external frame pulse from the frame pulse detection circuit 37 is supplied to the other input terminal of the NAND circuit 411. The output of this NAND circuit 411 is
It is supplied to the clear terminal of the counter 412. The output of the counter 412 is supplied to one terminal of a NAND circuit 414, and is inverted by an inverter 413 and supplied to an enable terminal. An external frame pulse is supplied to the other input terminal of the NAND circuit 414.

According to the out-of-sync detection circuit 41, if the phase of the internal frame pulse matches the phase of the external frame pulse, the output of the counter 412 is low level (no carry) because the counter 412 is cleared. Therefore, the output of the NAND circuit 414 maintains the high level. However, if the phases of the external frame pulse and the internal frame pulse do not match, the counter 41
2 is not cleared. For this reason, counting proceeds and carry is obtained. Therefore, at this time, the output of the NAND circuit 414 becomes low level, and a detection signal indicating loss of synchronization is obtained. The output of the NAND circuit 414 is supplied to the reset terminals of the filter 34, the horizontal counter 38, and the vertical counter 39 shown in FIG.

Note that the output of the NAND circuit 414 is inverted as necessary and supplied to another circuit.

The present invention is not limited to the above embodiments,
Needless to say, the present invention can be applied to a receiver of the MUSE-T system (document: D-22-166, Spring Meeting of the Communication Society of Japan, 1988) having the same synchronization waveform as the MUSE signal.

As described above, according to this embodiment, the digital MU
Even during the SE signal processing, the out-of-synchronization can be reliably detected, which can always contribute to obtaining a good image.

 FIG. 3 shows another embodiment of the present invention.

The same parts as those in the embodiment of FIG. 1 are denoted by the same reference numerals. The different points from the previous embodiment will be described below.

In this embodiment, the window width setting circuit 40 sets the pulse width of the internal frame pulse slightly wider than the pulse width of the external frame pulse. The internal frame pulse output from the window width setting circuit 40 is input to one input terminal of the out-of-sync detection circuit 41.

The out-of-synchronization detection circuit 41 detects whether or not the external frame pulse exists within the pulse width of the internal frame pulse.If the external frame pulse exists, the out-of-sync state is detected. Obtain a detection signal. In the out-of-synchronization state, the detection signal goes low and the filter 3
4, horizontal counter 38, vertical counter 39 are reset,
Set to the initial state. As a result, the synchronization pull-in is started from the beginning.

The output of the out-of-synchronization detection circuit 41 is also supplied to one input terminal of the AND circuit 53. The output terminal of the AND circuit 53 is connected to one input terminal 54D of the switch 54. The output terminal of the out-of-sync detection circuit 41 is directly connected to the other input terminal 54A of the switch 54.
The other terminal of the AND circuit 53 is supplied with the output of a differentiating circuit 55 for differentiating the horizontal synchronizing pulse of the digital MUSE signal. The differentiating circuit 55 obtains a low-level pulse in synchronization with the falling portion of one cycle width of the reproduced clock obtained from the voltage controlled oscillator 36 during the horizontal synchronizing pulse period. The switch 54 is connected to the terminal 54D by a switching signal during digital MUSE signal processing.
Therefore, when an out-of-sync detection signal (low level) from the out-of-sync detection circuit 41 is obtained, or when a low-level pulse is obtained from the differentiating circuit 55 based on the horizontal sync pulse during processing of the digital MUSE signal. , And the output of the AND circuit 53 becomes low level, and a reset pulse for the horizontal counter 38 is given.

According to the embodiment described above, at the time of digital MUSE signal processing, the external and internal frame pulses are synchronized with respect to the horizontal synchronizing pulse. And a good image can always be obtained.

 FIG. 4 shows still another embodiment of the present invention.

An input terminal 31 is supplied with an analog MUSE signal including an HD signal and a frame pulse signal having a predetermined pattern, and is digitized by an analog / digital (A / D) converter 32. The digitized MUSE signal is output to the phase error detection circuit 33.
Here, a phase error of a horizontal synchronization (HD) signal is detected. As shown in FIG. 9, the horizontal synchronization signal has a predetermined phase detection point (HD point). Therefore, if the sampling signal obtained at this HD point is not a predetermined value, it means that the phase of the sampling pulse is shifted, and the error output is output via the filter 34 to the digital-to-analog (D / A) converter 35. Is input to The output of the digital-to-analog converter 35 is supplied to one terminal of the switch 51. The switch 51 selects the terminal 51A when processing an analog MUSE signal, and selects the other terminal 51D when processing a digital MUSE signal. A switching signal for this selection is supplied from a terminal 43. Terminal
An error signal from a switch 63 described later is supplied to 51D.

The clock phase error output from the phase error detection circuit 44 is supplied to one input terminal 631 of the switch 63 via the filter 45. The phase error detection circuit 44 detects a phase error of the external clock supplied to the clock input terminal CK of the digital input section 42. In this case, the phase error detection circuit 44 uses the internal clock output from the voltage controlled oscillator 36 as a reference clock for phase comparison. Further, the other input terminal 632 of the switch 63 is supplied with the phase error output from the phase error detection circuit 65 via the filter 66. The phase error detection circuit 65 is connected to the digital input section 42.
The phase error of the external horizontal sync pulse supplied to the horizontal sync pulse input terminal H is detected. In this case, the phase error detection circuit 65 uses an internal horizontal synchronization pulse from a later-described reference pulse generation circuit (horizontal counter 38) as a reference pulse for phase error comparison.

The switching of the switch 63 is controlled by the output of the window comparator 67. Window comparator 67
Creates a switch control output according to the level of the clock phase output (the output of the filter 45).

Fig. 5 shows the output of the filter 45 and the window comparator.
The output of 67 is shown. The window comparator 67 obtains a discrimination output in which the output level of the filter 45 is discriminated into three regions, large, medium, and small. The switch 63 is connected to the level 63 in the region where the output of the window comparator 67 is large or small.
When the value indicates 1, the output of the filter 45 is selected, and when the level 632 of the middle region is indicated, the output of the filter 66 is selected and derived. The switch 63 derives a clock phase error output when the clock phase error is large, and derives a phase error output of the horizontal synchronization pulse when the clock phase error is small. The output of the switch 63 is supplied to the input terminal 51D of the switch 51.

The output of switch 51 is a voltage controlled oscillator 36 using crystal.
Is supplied to the control terminal. The oscillation output of the voltage controlled oscillator 36 is used as a sampling clock,
It is used as a pulse for generating an internal horizontal synchronization pulse and an internal frame pulse. That is, it is supplied to the horizontal counter 38. The horizontal counter obtains the horizontal address of each line, and the line count output (horizontal synchronization pulse) is also supplied to the vertical counter 39 and the phase error detection circuit 65. The vertical counter 39 obtains a vertical address and generates an internal frame pulse corresponding to an external frame pulse generated based on a frame pulse signal having a predetermined pattern.

The internal frame pulse is input to the window width setting circuit 40. The window width setting circuit 40 sets the pulse width of the internal frame pulse slightly wider than the pulse width of the external frame pulse.

The internal frame pulse output from the window width setting circuit 40 is input to one input terminal of the out-of-sync detection circuit 41.

Further, the output of the analog-to-digital converter 32 is supplied to one input terminal 52A of the switch 52. This switch 5
The digital MUSE signal from the digital input section 42 is supplied to the other input terminal 52D of the second. The switch 52 is controlled by a switching signal from the terminal 43 so as to select the terminal 52A when processing an analog MUSE signal and to select 52D when processing a digital MUSE signal.

The output of the switch 52 is input to the frame pulse detection circuit 37, where a frame pulse signal having a predetermined pattern is detected, and an external frame pulse having a predetermined pulse width is output. This external frame pulse is supplied to the other input terminal of the out-of-sync detection circuit 41.

The out-of-synchronization detection circuit 41 detects whether or not the pulse of the external frame pulse is within the pulse width of the internal frame pulse. A detection signal is obtained as a state. In the out-of-synchronization state, the filter 34, the horizontal counter 38, and the vertical counter 39 are reset by the detection signal, and set to the initial state. As a result, the synchronization pull-in is started from the beginning.

Now, assuming that the receiver is switched to the digital MUSE signal processing state, the switch 51 is connected to the input terminal 51D and the switch 52.
Becomes a state in which the input terminal 52D side is selected. Phase error detection circuit 44, filter 45, switches 63 and 51, voltage controlled oscillator
The phase locked loop formed by 36 functions as a loop that synchronizes the internal clock with the external clock. Further, a phase locked loop formed by the phase error detection circuit 65, the filter 66, the switches 63 and 51, the voltage controlled oscillator 36, and the horizontal counter 38 functions as a loop for synchronizing the internal horizontal sync pulse with the external horizontal sync pulse.

When the receiver is in the initial synchronization signal pull-in state,
Since the error output of the phase error detection circuit 44 is large, the control information for the voltage controlled oscillator 36 uses the clock phase error information. Thereby, a high-speed retraction operation is obtained. When the switch 63 is in a stable state, the switch 63 forms a phase control loop relating to the horizontal synchronization pulse, so that synchronous reproduction always synchronized with the horizontal synchronization pulse is performed.

[Effects of the Invention] As described above, according to the present invention, the analog MUSE
In both signal processing and digital MUSE signal processing, the synchronization state can be accurately adjusted, which can always contribute to obtaining a good image.

[Brief description of the drawings]

FIG. 1 is a structural explanatory view showing one embodiment of the present invention, FIG. 2 is a circuit diagram showing a specific example of an out-of-synchronization detecting circuit and a window width setting circuit of FIG. 1, and FIGS. FIG. 5 is an explanatory view showing the configuration of another embodiment of the present invention, FIG. 5 is an explanatory view for explaining the operation of the window comparator and switch of FIG. 4, and FIG. 6 is a view for processing a digital MUSE signal. FIG. 7 is a diagram showing a synchronous reproduction circuit used in a conventional analog MUSE signal processing device, FIG. 8 is an explanatory diagram showing a signal format of the MUSE system, and FIG. FIG. 4 is an explanatory diagram of a synchronization signal included in a signal. 32: Analog-to-digital converter, 33, 44, 65 ... Phase error detection circuit, 34, 45, 66 ... Filter, 35 ... Digital-to-analog converter, 36 ... Voltage controlled oscillator, 37 ... Frame pulse detection Circuit, 38 horizontal counter, 39 vertical counter, 40 window width setting circuit, 41 out-of-sync detection circuit, 42 digital input section, 51, 52, 63 switch
67 ... Window comparator.

Continuation of the front page (72) Inventor Toshiro Omura 2-2-1 Jinnan, Shibuya-ku, Tokyo Inside the Japan Broadcasting Corporation Broadcasting Center (72) Inventor Takahiro Shinkai 1-9-1-2 Hara-cho, Fukaya-shi, Saitama Inside Toshiba Fukaya Plant (72) Inventor Yoichi Igarashi 3-3-9, Shimbashi, Minato-ku, Tokyo Toshiba Audio Video Engineering Co., Ltd. (72) Inventor Satoshi Funayama 1-9-1-2 Harara-cho, Fukaya-shi, Saitama (56) References JP-A-2-132990 (JP, A) JP-A-61-261973 (JP, A) JP-A-1-136473 (JP, A) JP-A-63-1987 199587 (JP, A) JP-A-61-171294 (JP, A) JP-A-3-175833 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 5/12 H04N 7 / 015

Claims (3)

(57) [Claims] An analog-to-digital conversion means for digitizing an analog MUSE signal and outputting it as a first MUSE signal, wherein the digital MUSE signal is a second MUSE signal. A digital input unit which is also supplied as a clock, a first phase error detecting means for detecting a phase error of a horizontal synchronization signal included in a first MUSE signal, and a clock supplied to the digital input unit A second phase error detecting means for detecting the phase error of the first phase error detecting means for analog MUSE signal processing and an output from the second phase error detecting means for digital MUSE signal processing. A first switch for supplying to the control terminal of the voltage controlled oscillator; a first MUSE signal for analog MUSE signal processing; and a second MUSE signal for digital MUSE signal processing. A second switch for selecting and outputting, and a first or second MUSE signal selected by the second switch is supplied, and a frame pulse signal transmitted at a vertical cycle included in the MUSE signal is supplied to the second switch. A frame pulse detecting means for detecting and outputting an external frame pulse having a predetermined pulse width; and obtaining a horizontal period pulse by counting the output of the voltage controlled oscillator, and counting the horizontal period pulse to obtain a vertical period pulse. And a circuit for receiving the pulse of the vertical cycle, setting the pulse width of the pulse, and outputting the pulse as an internal frame pulse. An internal frame pulse having a wide width is created, and an internal frame pulse having substantially the same width as the external frame pulse is generated during the second MUSE signal processing. Window width setting means for generating and outputting a pulse; and out-of-synchronization for detecting whether or not frame synchronization has been lost by comparing the phases of the external frame pulse and the internal frame pulse obtained by the window width setting means. A high-definition television receiver comprising: detecting means; and reset means for resetting the counting means when an out-of-sync detection signal is obtained from the out-of-sync detecting means. 2. A receiver capable of receiving a MUSE system which is a transmission system of a high-definition television, wherein: an analog-to-digital conversion means for digitizing an analog MUSE signal and outputting the digital MUSE signal as a first MUSE signal; A digital input unit that is also supplied as a clock and a horizontal synchronization pulse, a first phase error detection unit that detects a phase error of the horizontal synchronization signal included in the first MUSE signal, A second phase error detecting means for detecting a phase error of the supplied clock; an output from the first phase error detecting means during analog MUSE signal processing; and an output from the second phase error detecting means during digital MUSE signal processing. Select the first switch to supply to the control terminal of the voltage controlled oscillator, and select the first MUSE signal when processing the analog MUSE signal, and process the digital MUSE signal. Is supplied with a second switch for selecting and outputting a second MUSE signal, and a first or second MUSE signal selected by the second switch, and is transmitted at a vertical period included in the MUSE signal. Frame pulse detecting means for detecting an incoming frame pulse signal and outputting an external frame pulse having a predetermined pulse width; and obtaining a horizontal period pulse by counting the output of the voltage controlled oscillator, A counting means for counting and obtaining a pulse of the vertical cycle; a circuit for receiving the pulse of the vertical cycle, setting a pulse width of the pulse, and outputting the pulse as an internal frame pulse; A window width setting means for generating and outputting a wide internal frame pulse; the external frame pulse; and an internal frame pulse obtained by the window width setting means. Out-of-synchronization detecting means for detecting whether frame synchronization is out of synchronization by comparing the phase with a frame pulse, shaping means for shaping a horizontal synchronization pulse of the digital input section to generate a reset signal, and resetting the counting means Reset processing means for resetting the counting means using the detection signal when the out-of-synchronization detection means detects the out-of-synchronization at the time of the first MUSE signal processing, and at the time of the second MUSE signal processing, A high-definition television receiver comprising: reset means for resetting the counting means by using a logical product output of the out-of-sync detection signal and a reset signal from the shaping means. 3. A receiver capable of receiving a MUSE system which is a transmission system of a high-definition television, wherein: an analog-to-digital conversion means for digitizing an analog MUSE signal and outputting it as a first MUSE signal; A digital input unit that is also supplied as a clock and a horizontal synchronization pulse, a first phase error detection unit that detects a phase error of the horizontal synchronization signal included in the first MUSE signal, A second phase error detecting means for detecting a phase error of the supplied clock; a third phase error detecting means for detecting a phase error of a horizontal synchronization pulse supplied to the digital input unit; a second phase error A window comparator for supplying an output of the detection means through a filter and obtaining an output which is obtained by discriminating the output level into three areas of large, medium and small; When the output indicates the level of a large area or a small area, the second
A first switch for selecting and outputting the output of the third phase error detecting means when the output of the phase error detecting means is selected and indicating the level of the middle area, and the first switch for selecting and outputting the output of the third phase error detecting means. And a second switch for selecting an output from the phase error detecting means and supplying an output from the first switch during digital MUSE signal processing to the control terminal of the voltage controlled oscillator. Selects a first MUSE signal, selects and outputs a second MUSE signal during digital MUSE signal processing, and a first or second MUSE signal selected by the third switch. Frame pulse detection means for detecting a frame pulse signal supplied and sent at a vertical period included in the MUSE signal, and outputting an external frame pulse having a predetermined pulse width; and Use Means for providing a reference pulse serving as a phase comparison reference to the first phase error detecting means; and obtaining a horizontal period pulse by counting the output of the voltage controlled oscillator, and counting the horizontal period pulse to obtain a vertical period. Counting means for obtaining a pulse; means for giving a horizontal cycle pulse of the counting means to the third phase error detecting means as a reference pulse serving as a phase comparison reference; and a pulse of a vertical cycle from the counting means being input;
Window width setting means for setting the pulse width of this pulse to generate an internal frame pulse wider than the pulse width of the external frame pulse; an internal frame pulse obtained from the window width setting means and the frame pulse detecting means Out-of-synchronization detecting means for comparing the phase with the external frame pulse obtained from the above, and detecting whether or not the frame is out of synchronization; and when the out-of-synchronization detection signal is obtained from the out-of-synchronization detecting means, at least the counting means A high-definition television receiver, comprising: reset means for resetting.