JPS62180689A - Display control clock generating circuit device - Google Patents

Abstract

PURPOSE:To attain the generation of a master clock and a display clock with one clock generation circuit by providing a 2/5 frequency dividing circuit which inputs a signal from the oscillation circuit of 13.5mHz, and a horizontal synchronizing signal. CONSTITUTION:The signal of 13.5mHz inputted from a clock input 1 is 2/5-frequency divided, and the signal of 5.4mHz can be obtained. In such a case, 13.5mHz is represented as 858fH (fH:horizontal frequency), however, even when it is multiplied by 2.5, an integer is not obtained, and as a result, when it is left as it is, the phase of a display clock at every H is dislocated. Therefore, a set pulse generated from the horizontal synchronizing signal is inputted to the clear terminal of a 10 bit counter, and again a synchronization with a horizontal is taken. By constituting a circuit in such a way, a clock generation circuit where two PLLs are used is eliminated and the generation of the clock can be performed with one PLL.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a display control clock generation circuit device that can be used for teletext broadcasting and the like.

(Prior Art) Technology related to multiplex television broadcasting has developed in recent years, and various television multiplexing systems have been proposed accordingly. One method proposed is television teletext. In television teletext, there are 24
It is standardized to be able to display 8 dots, and because of this, the display control clock is synchronized with the horizontal synchronization signal of the television and is capable of displaying 248 dots. Due to the combination of is often used.

In addition, digital television, which digitizes television signal processing, has been proposed in recent years, and the sampling frequency has been changed to a horizontal frequency of 858 fH = 13.5 MHz to suit the three systems of NTSC, PAL, and SECAM systems. A clock synchronized with a synchronization signal is used.

Conventionally, when attempting to incorporate a teletext decoder into a digital television, a display control clock generation circuit for the teletext decoder was provided separately, even though the digital television had a clock synchronized with the horizontal synchronization signal. The conventional system will be explained based on FIGS. 3 to 5.

FIG. 3 is a block diagram of a digital television with a built-in teletext decoder. In the figure, 21 is a tuner;
22 is a VIF, 23 is an audio A/D converter, 24 is a video and synchronization A/D converter, 25 is a sampling clock (13.5MHz) generation circuit, 26 is an audio demodulation amplifier circuit, and 27 is a brightness amplification color demodulation circuit. , 28 is a synchronization separation and deflection processing circuit, 29 is an audio D/A converter, 30 is a video D/A converter, 31 is a circuit for switching between R6B audio decoded from a character multiplex signal and TV RGB audio,
32 is an audio output circuit, 33 is a video output circuit, 34 is a deflection output circuit, 35 is a character multiplex signal decoder, 36 is a speaker, and 37 is a CRT. Here, the clock generation circuit 25 has a 13.5 MHz oscillator, has a horizontal synchronization signal and a PLL configuration, and uses that signal to sample the video signal.

It serves as a master clock for processing nine brightness colors demodulation and deflection signal processing.

FIG. 4 is a detailed block diagram of the teletext decoder. In the figure, 41 is a character signal separation circuit, 42 is an error correction circuit, 43 is a CPU program ROM, and 44 is a CPU
45 is a character data buffer RAM,
46 is a character ROM containing kanji, etc., 47 is a keyboard used for page selection, etc., 48 is a keyboard signal interface circuit, 49 is a CPU, 50 is a display control clock generation circuit, 51 is a display control bus control circuit, 52 is a video color memory, 53 is a video pattern memory, 54 is a color matrix, 55 is an additional sound interface, and 56 is an additional sound decoder.

FIG. 5 is a detailed block diagram of one display clock generation.

In the same figure, 61 is an 8fsc oscillation circuit, and 62 is a 1/1
820 frequency divider circuit, 63 is a filter, 64 is a phase detection circuit, 8fsc oscillation circuit 61.1/1820 frequency divider circuit 62
It constitutes a PLL together with the filter 63 and is synchronized with the horizontal. 65 is a 175 frequency divider circuit with 8/5 fsc
outputs the display clock.

(Problems to be Solved by the Invention) The above configuration has the disadvantage that the circuit is complicated, the number of parts is large, and the cost is high.

SUMMARY OF THE INVENTION An object of the present invention is to provide a display control clock generation circuit that can eliminate the drawbacks of the conventional technology and generate a master clock for a digital television and a display clock for a teletext decoder using only one clock generation circuit.

(Means for solving the problem) The display control clock generation circuit device of the present invention has a 13.5M
An oscillation circuit that oscillates Hz, a frequency divider circuit that takes the signal of this oscillation circuit as input and divides it up to the horizontal frequency of the television, a phase detection circuit that receives the signal of this frequency divider circuit and the horizontal synchronization signal as input, and this 13. A filter circuit that filters the output of the phase detection circuit and the filtered detection signal.
13; means for controlling the 5 MHz oscillator path;
．． It consists of a signal from a 5 MHz oscillation circuit and a 275 frequency divider circuit that receives a horizontal synchronizing signal as input.

(Function) With the above configuration, the present invention has a 13.5 MHz oscillator as the master clock of a digital television as before, and synchronizes it by configuring the horizontal and PLL. On the other hand, in the teletext decoder, the problem can be solved by using a 275 frequency divider circuit that receives a 13.5 MHz signal as an input and is reset by a horizontal synchronizing signal as a display control block generating circuit.

(Example) An example of the present invention will be described based on FIGS. 1 and 2.

FIG. 1 is a diagram of a display control clock generation circuit according to an embodiment of the present invention. In the figure, 1 is a 10-bit 1 counter, 2 is an inverter, 3, 4, and 5.6 are latch circuits (D flip-flops), and 7°8', 9, and 10 are N A
It is an N'0 circuit.

13,5 M l input from clock input (1)
(The signal of z is divided by 275 to obtain a signal of 5.4 MHz.

Here, 13.5 MHz = 858 fH (fH: horizontal frequency), but even if this is 275, it will not become an integer, and as a result, if left as is, the phase of the display clock will shift for each H. Therefore, a reset pulse generated from the horizontal synchronizing signal is input to the clear terminal of the 10-pill counter to synchronize with the horizontal again. With such a circuit configuration, a clock generation circuit using two PLLs becomes unnecessary, and a clock can be generated using one PLL.

FIG. 2 is a timing chart of the display control clock generation circuit shown in FIG. In the figure, ■ to ■ correspond to ■ to ■ shown in FIG.

(Effects of the Invention) According to the present invention, a master clock of a digital television and a display clock of a teletext decoder can be generated with one clock generation circuit without using a clock generation circuit using two PLLs. , simplify the circuit,
The number of parts is reduced, which has great practical effects such as cost reduction.

[Brief explanation of drawings]

FIG. 1 is a display control clock generation circuit diagram according to an embodiment of the present invention, FIG. 2 is a timing chart of the circuit shown in FIG. 1, and FIG. 3 is a block diagram of a digital television incorporating a conventional teletext decoder. FIG. 4 is a detailed block diagram of the same teletext decoder, and FIG. 5 is a detailed block diagram of the same display clock generation. 1...Bit counter, 2...Inverter, 3
．． 4,5.6...Latch circuit (D flip-flop)
7, 8, 9, 10...NAND circuit. Patent applicant Matsushita Electric Industrial Co., Ltd.○ Oe@0 ■Oo■O○

Claims (1)

[Claims] an oscillation circuit that oscillates at 13.5 MHz; a frequency divider circuit that receives the signal of the oscillation circuit as an input and divides the frequency up to the horizontal frequency of the television; and a phase detection circuit that inputs the signal of the frequency divider circuit and a horizontal synchronization signal; 13 with a filter circuit that filters the output of the phase detection circuit and the filtered detection signal.
．． A display control clock generation circuit comprising means for controlling a 5 MHz oscillation circuit, a 2/5 frequency divider circuit that receives a signal from the 13.5 MHz oscillation circuit, and a horizontal synchronization signal as input. Device.