JPH04207865A - Synchronizing signal production circuit - Google Patents

Abstract

PURPOSE:To produce an output synchronizing signal which is synchronous with a standard external synchronizing signal by detecting a phase error of the output synchronizing signal based on a framing signal and a reference signal synchronous with the standard external synchronizing signal and then correcting the phase of the output synchronizing signal based on the result of the phase error detection. CONSTITUTION:The states of the division signals SCK2 end SCK3 outputted from a PLL circuit are detected in the timing set based on the output signal SHD1 outputted from a synchronizing signal generating circuit 12 and having a phase error equivalent to a jitter absorbing band. If the states of both signals SCK2 and SCK3 are not synchronized with a reference external synchronizing signal SGL at detection of both signal states, the correction is applied by an extent equal to the phase error to an internal composite synchronizing signal SSYNC1, an internal blanking signal SBLK1, an internal vertical synchronizing signal SVD1, and an internal horizontal synchronizing signal SHD1 respectively. Thus it is possible to obtain an output composite synchronizing signal SSYNC2, an output blanking signal SBLK2, an output vertical synchronizing signal SVD2, and an output horizontal synchronizing signal SHD2 which are synchronous with the signal SGL.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a synchronization signal generation circuit, and is suitable for application to, for example, synchronizing a VTR with external equipment.

B Summary of the Invention The present invention provides a synchronization signal generation circuit that outputs a framing signal for each predetermined field obtained based on a reference external synchronization signal in synchronization with an internal synchronization signal that includes a phase error with respect to the reference external synchronization signal. The framing signal thus output and a reference signal synchronized with the external synchronization signal are compared to detect the phase error of the internal synchronization signal with respect to the reference external synchronization signal, and the phase error of the internal synchronization signal is determined based on the detection result. By correcting the phase error, it is possible to obtain an output synchronization signal that is synchronized with the reference external synchronization signal.

C. Prior Art Conventionally, for example, in a VTR synchronization signal generation circuit, a method for generating a synchronization signal synchronized with a reference external synchronization signal inputted from the outside is to generate a reference horizontal synchronization signal and a reference vertical synchronization signal from a reference external synchronization signal. After separating the composite synchronization signal, each component circuit is synchronized by applying a reset based on the composite synchronization signal, thereby obtaining a synchronization signal synchronized with the reference external synchronization signal.

In this method, in order to absorb jitter components included in the reference external synchronization signal when resetting is applied, jitter absorption bands for a predetermined time are sequentially provided, and all of the reference external synchronization signals within the jitter absorption band are It is designed to output at a fixed timing.

D Problems to be Solved by the Invention However, if the jitter absorption band is provided in this way, the jitter absorption band will be synchronized with the reference external synchronization signal every time the VTR device is switched on, for example, after being turned off and then turned on again. There was a problem in that the maximum jitter in the output synchronization signal caused bone displacement in the absorption zone.

Particularly in digital VTRs, a burst signal is generated from a horizontal synchronizing signal, and if the phase of the burst signal shifts, images cannot be reproduced correctly.

The present invention has been made in consideration of the above points, and provides a synchronization signal that can absorb the jitter component of a reference external synchronization signal and stabilize the phase of an output synchronization signal output in synchronization with the reference external synchronization signal. This paper attempts to propose a generation circuit.

8 Means for Solving the Problems In order to solve the problems, in the present invention, the framing signal 5COL for each predetermined field obtained based on the reference external synchronization signal SGL is used as the reference external synchronization signal SQ.
internal synchronization signal 5SYNCI including a phase error with respect to L;
Output in synchronization with 5BLKI, 5VD1, SHD 1,
Output framing signal 5COL and external synchronization signal S
Internal synchronization signals 5SYNCI, 5BLKI, 5VD1 .
5) (Detect the phase error of Di with respect to the reference external synchronization signal SQL, and set the internal synchronization signal 5SYNC based on the detection result.
I, 5BLKI, 5VDI, and 5HD1 phase errors are corrected and output synchronization signal 5 is synchronized with the reference external synchronization signal SQL.
Output as SYNC2,5BLK2.5VD2.5HD2.

The framing signal 5COL for each predetermined field obtained based on the F-action reference external synchronization signal SGL is converted into an internal synchronization signal SHD that includes a phase error with respect to the reference external synchronization signal SGL.
The framing signal 5COL thus outputted is compared with the reference signals 5CK2 and 5CK3 synchronized with the reference external synchronization signal SGL to detect the phase error of the internal synchronization signal SHD with respect to the reference external synchronization signal SQL. Based on the detection result, the internal synchronization signal S
By correcting the HD phase error, the output synchronization signals 5SYNC2, 5BLK are synchronized with the reference external synchronization signal SQL.
2.5VD2 and SHD can be obtained.

G-ho example Embodiments of the present invention will be described in detail below with reference to the drawings.

In FIG. 1, 1 is the reference external synchronization signal SC as a whole,
Output synchronization signal (SSYNC2, 5BLK2
．． 5VD2 and 5HD2), the synchronization signal separation circuit 3 separates the burst signal 5BST and the composite synchronization signal 5SYNC from the reference external synchronization signal SG'L, and the burst signal 5BST is transferred to the comparison circuit 4. At the same time, the composite synchronization signal 5SYNC
is input to the reset generation circuit 11.

The comparison circuit 4, together with a VCO (pressure controlled oscillation circuit) 5 and a counter circuit 6, is connected to PLL (phase I).

The frequency of the output signal (subcarrier) of the comparator circuit 4 is multiplied by 4 in the VCO 5 to obtain the reference clock signal 5CK1, and then the frequency is divided by 1/4 in the counter circuit 6. A first frequency-divided signal 5CK2 having a frequency of 1/4 of the reference clock signal SCK and a second frequency-divided signal 5CK3 having a frequency of 1/2 of the reference clock signal SCK are obtained.
By feeding back CK2 to the comparator circuit 4,
Burst signal 5BST and frequency divided signals 5CK2 and 5CK
3 to phase lock.

Further, the reset generation circuit 11 generates a horizontal reset signal 5HR3T based on the horizontal synchronization signal and a vertical reset signal 5VR3T based on the vertical synchronization signal from the composite synchronization signal 5SYNC inputted from the synchronization signal separation circuit 3, and generates a subsequent synchronization signal. The signal is sent to circuit 12.

The synchronization signal generation circuit 12 generates a horizontal reset signal 5HRST.
, internal composite synchronization signal 5SYNCI, internal blanking signal 5BLK1, based on vertical reset signal 5VR3T and reference clock signal 5CKI input from VC05.
Internal vertical synchronization signal 5VDI and internal horizontal synchronization signal 5HD
I and sends them to the variable shift register 13.

Here, the synchronization signal generation circuit 12 ↓ is provided with a jitter absorption band for a predetermined time to absorb the jitter component of the horizontal reset signal 5HR3T, so that the internal composite signal sent from the synchronization signal generation circuit 12 is Synchronous signal 5SY
NCI, internal blanking signal 5BLKI, internal vertical synchronization signal SVD! The phase of the internal horizontal synchronization signal 5HDI also varies depending on the input timing of the reference external synchronization signal SGL.

Therefore, in the subsequent variable shift register 13, the internal composite synchronizing signal 5SYNCI and the internal blanking signal 5BLKI
, internal vertical synchronization signal 5VDI and internal horizontal synchronization signal SH
Processing such as synchronizing the phase of D1 with the reference clock signal 5CKI is executed.

That is, in the D flip-flop circuit 15, the divided signal 5CK2 outputted from the counter circuit 4 is inputted to the D input terminal, and the frame signal SFRAM indicating each frame obtained in the reset generation circuit 11 is inputted to the trigger input terminal. As a result, a color framing signal 5COL having a period of 4 fields is generated and sent to a latch circuit 16 having a single D flip-flop circuit configuration.

The latch circuit 16 outputs the color framing signal 5COL to D.
By inputting the internal horizontal synchronizing signal SHD 1 output from the synchronizing signal generation circuit 12 to the trigger input terminal as well as inputting the internal horizontal synchronizing signal SHD 1 to the trigger input terminal, the internal horizontal synchronizing signal 5) 101 is generated.
The phase shift is synchronized by the color framing signal 5COL based on the reference external synchronization signal SGL,
It is input to the trigger input terminal of the D flip Flora 1 circuit 17.

The D flip Flora 1 circuit 17 inputs the first frequency divided signal 5CK2 and the second frequency divided signal 5CK3 output from the counter circuit 6 to the first input terminal D1 and the second input terminal D2. 4 fields corresponding to the method (
Frequency divided signal 5CK2 at a rate of once per color framing)
and 5CK3, thereby controlling the variable shift register 13 by output signals SQL and SQ2 output from the first output terminal Q1 and the second output terminal Q2.

That is, as shown in FIG. 2, the D flip Flora 1 circuit 17 has a frequency-divided signal 5CK3 (FIG. 2 (A)) at "L".
The divided signal 5CK2 (Fig. 2 (B)) indicates the level.
In the state Li1T1 that indicates the "L" level, the output signal SQL (second
Figure (C)) and SQ2 (Figure 2 (D)) are r
By setting the level to L, the variable shift register 13
The delay amount is set to 3 clocks (Fig. 2 (E)), and the internal composite synchronization signal 5SYNCI, internal blanking signal 5BLKI, and internal vertical synchronization signal 5VD1 are thereby input.
and an output composite synchronization signal 5SYNC2, an output blanking signal 5BLK2, an output vertical synchronization signal 5VD2, and an output horizontal synchronization signal 5HD2, which are obtained by delaying the internal horizontal synchronization signal 5l (Di by three clocks).

In addition, in state T2 in which the frequency divided signal 5CK3 is at the r l('' level and the frequency divided signal 5CK2 is at the "L" level, the output signal SQL is set to the "H" level and the output signal SQ2 is set to the "L" level. By setting the delay amount of the variable shift register 13 to 2 clocks, the input internal composite synchronization signal 5SYNCI, internal blanking signal 5BLKI, internal vertical synchronization signal 5VDI, and internal horizontal synchronization signal 5HD1 are each 2 clocks. An output composite synchronization signal 5SYNC2, an output blanking signal 5BLK2, an output vertical synchronization signal 5VD2, and an output horizontal synchronization signal 5HD2 are obtained which are delayed by 5 minutes.

Further, the frequency division signal 5CK3 indicates the "L" level, and the frequency division signal 5CK3 indicates the "L" level.
In state T3 in which CK2 indicates the rH level, the output signal SQL is set to the "L" level and the output signal SQ2 is set to the rH level, so that the delay amount of the variable shift register 13 is set to one clock. As a result, output composite synchronization signal 5SYNC2, output blanking signal 5BLK2, output vertical A synchronizing signal 5VD2 and an output horizontal synchronizing signal 5HD2 are obtained.

Furthermore, the frequency-divided signals 5CK3 and 5CK2 are rH.
In the state DT4 that indicates the level, the output signal SQ
By setting L and SQ2 to H' level,
Let the delay amount of the variable shift register 13 be O clocks,
Internal composite synchronization signal 5SYNCI, which is manually input by this,
Internal blanking signal 5BLKI, internal vertical synchronization signal S
VD 1 and internal horizontal synchronization signal 5HDI are output without delay.

In this way, the D flip Flora 1 circuit 17 detects the divided signals 5CK3 and 5CK2 once every 4 fields (color framing), and controls the delay amount of the variable shift register 13 according to this state. ing.

In the above configuration, the synchronization signal generation circuit 1 generates a horizontal reset signal 5H obtained based on the external reference synchronization signal SGL.
In order to absorb jitter components included in R3T and vertical reset signal S■R3T, the horizontal reset signal 5HR is
3T and the vertical reset signal 5VR3T are provided with a jitter component absorption band, so that the internal composite synchronization signal 5SYNC1 and the internal blanking signal 5 output from the synchronization signal generation circuit 12 are
BLKI, internal vertical synchronization signal 5VD1, and internal horizontal synchronization signal 5HDI have a maximum phase difference of the jitter absorption zone relative to reference external synchronization signal SQL.

Therefore, the color framing signal 5COL with a 4-field period obtained based on the reference external synchronization signal SQL and the internal horizontal synchronization signal 5HD1 are synchronized in the latch circuit 16, and the latch pulse signal 5LAT obtained thereby is synchronized with the D flip Flora 1 circuit 17. By inputting the frequency divided signals 5CK2 and 5C output from the counter circuit 6 to
K3 is detected every 4 fields.

At this time, the timing of the latch pulse signal 5LAT (i.e., the phase of the internal horizontal synchronization signal 5HDI output from the synchronization signal generation circuit 12) is a frequency-divided signal from the counter circuit 6 (i.e., the PLL circuit) whose phase is locked to the reference external synchronization signal SGL. If the phase is equal to 5CK2 and 5CK3 (
T4 in FIG. 2), this indicates that the internal horizontal synchronizing signal 5HDI output from the synchronizing signal generation circuit 12 is synchronized with the reference external synchronizing signal SCL, and the corresponding 0797
17077 circuit 17 outputs composite synchronization signal 5S without delaying composite synchronization signal 5SYNCI, blanking signal 5BLKI, vertical synchronization signal 5VD1, and horizontal synchronization signal 5HDI inputted in variable shift register 13.
YNC2, output blanking signal 5BLK2, output vertical synchronization signal 5VD2, and output horizontal synchronization signal 5HD2.

In contrast, the timing of the latch pulse signal 5LAT (
That is, the phase of the horizontal synchronization signal SHD output from the synchronization signal generation circuit 12) is shifted from the phase of the frequency-divided signals 5CK2 and 5CK3 from the counter circuit 6 (that is, the PLL circuit) phase-locked to the reference external synchronization signal SGL. (T1, T2, T3 in FIG. 2), this means that the internal horizontal synchronization signal 5HD output from the synchronization signal generation circuit 12
1 represents a state in which the D flip-flop circuit 1 is deviated from the reference external synchronization signal SGL by a predetermined time.
7 is an internal composite synchronization signal 5SYNCI and an internal blanking signal 5BL inputted to the variable shift register 13.
KI, internal vertical synchronization signal SVD 1 and internal horizontal synchronization signal 5HDI are each delayed by the corresponding phase error to output composite synchronization signal 5SYNC2 and output blanking signal 5.
BLK2, output vertical synchronization signal 5VD2 and output horizontal synchronization signal S)! Output as D2.

Thus, the output composite synchronization signal 5SYNC2 and the output blanking signal 5BLK2 are synchronized with the reference external synchronization signal SQL.
, output vertical synchronization signal 5VD2 and output horizontal synchronization signal 5H
You can get D2.

According to the above configuration, the states of the frequency-divided signals 5CK2 and 5CK3 output from the PLL circuit are detected at the timing based on the output signal (SHDI) from the synchronization signal generation circuit 12 having a phase error corresponding to the jitter induced band. , the detection time S
Here, when the states of the frequency-divided signals 5CK2 and 5CK3 are not synchronized with the reference external synchronization signal SCL, the internal composite synchronization signal 5SYNCI and internal blanking signal 5B output from the synchronization signal generation circuit 12 by this phase error.
LKI, an output composite synchronization signal 5SYNC2 synchronized with the reference external synchronization signal SGL by correcting the internal vertical synchronization signal 5VDi and the internal horizontal synchronization signal 5HD1,
Output blanking signal 5BLK2, output vertical synchronization signal 5
VD2 and output horizontal synchronization signal 5HD2 can be obtained.

Note that in the above embodiment, the variable shift register 13
Internal composite synchronization signal SSY NC1, internal blanking signal 5BLK 1, internal vertical synchronization signal 5 input to
Although the case has been described in which the VD1 and the internal horizontal synchronization signal 5HD1 are delayed according to a predetermined amount of correction, the present invention is not limited to this, and may be delayed according to a predetermined amount of correction.

Furthermore, in the above embodiment, a case has been described in which the color frame signal 5COL is output for every 4 fields in response to an NTSC television signal, but the present invention is not limited to this, and for example, the present invention is applicable to a PAL television signal. In the case where the television signal is handled, it may be possible to change this in various ways depending on the television signal to be handled, such as outputting a color frame signal every 8 fields.

Further, in the above-described embodiments, a case has been described in which the present invention is applied to a synchronizing signal generation circuit of a VTR device, but the present invention is not limited to this, but can be widely applied to a synchronizing signal generating circuit of various other electronic devices. be able to.

H Effects of the Invention As described above, according to the present invention, a framing signal for each predetermined field obtained based on a reference external synchronization signal is output in synchronization with an internal synchronization signal including a phase error, and the framing signal and the reference By detecting the phase error of the output synchronization signal based on the reference signal synchronized with the external synchronization signal and correcting the phase of the output synchronization signal based on the detection result, the output synchronization signal synchronized with the reference external synchronization signal is It is possible to realize a synchronization signal generation circuit that can generate synchronization signals.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a synchronizing signal generating circuit according to the present invention, and FIG. 2 is a signal waveform diagram for explaining control of the variable shift register. 1... Synchronous signal generation circuit, 3... Synchronous signal separation circuit, 4... Comparison circuit, 5...
・Voltage controlled oscillation circuit, 6... Counter circuit,
12... Synchronization signal generation circuit, 13...
Variable shift register, 17...D flip-flop circuit.

Claims (1)

[Claims] Outputting a framing signal for each predetermined field obtained based on a reference external synchronization signal in synchronization with an internal synchronization signal including a phase error with respect to the reference external synchronization signal, detecting a phase error of the internal synchronization signal with respect to the reference external synchronization signal by comparing the signal with a reference signal synchronized with the external synchronization signal, and correcting the phase error of the internal synchronization signal based on the detection result; A synchronization signal generation circuit characterized in that the circuit outputs an output synchronization signal synchronized with the reference external synchronization signal.