JP2000175069A - Distortion correction circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain a high response of a loop without scarifying jitter performance on a screen by adopting a configuration such that a delay the same as a delay given to horizontal synchronizing pulse is also given to a horizontal drive pulse and it is fed to a horizontal output circuit to maintain a phase lock state of a PLL circuit. SOLUTION: The PLL circuit consists of a phase comparator 2, an LPF 3, a VCO 4, a horizontal drive pulse generating circuit 5, a variable delay circuit 6 and a horizontal output circuit 7. The phase comparator 2 detects a phase difference between a flyback pulse and a horizontal synchronous pulse delayed by a variable delay circuit 1 and a signal outputted from the LPF 3 controls an oscillated frequency from the VCO 4. The horizontal drive pulse generating circuit 5 receiving an output of the VCO 4 generates and outputs a horizontal drive pulse where the duty factor and the polarity of the pulse are controlled, the variable delay circuit 8 delays the pulse and the delayed pulse is given to the horizontal output circuit 7. When an image is distorted, a saw tooth wave obtained by a waveform generating circuit 8 is used to control the distortion.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a distortion correction circuit for a CRT display device.

[0002]

2. Description of the Related Art Generally, CRT display devices for computers are compatible with various scanning frequencies. Therefore, in order to reduce the distortion of the image at the display of any frequency, various distortion correction circuits capable of adjusting the correction amount are mounted.

[0003] A typical example of distortion in which an image is shifted in the horizontal direction is a parallelogram distortion, and a circuit for correcting the distortion is provided in many display devices.

[0004] The parallelogram distortion can be corrected by modulating the horizontal phase of the image with a sawtooth wave having a vertical period. For example, JP-A-7-253761 describes one of the solutions. The method will be described below with reference to the drawings.

[0005] The operation of the conventional parallelogram distortion correction circuit will be described with reference to FIGS. 5, 2 and 3. FIG. 5 is a configuration diagram of a conventional distortion correction circuit. In FIG. 5, the horizontal synchronization pulse input to the variable delay circuit 1 is a horizontal synchronization signal itself obtained from a signal source connected to the display device or a pulse having a specific phase relationship with the horizontal synchronization signal. Here, in the case of a pulse having a specific phase relationship, a phase relationship is given to a horizontal synchronizing signal by a preceding circuit (not shown) mainly for adjusting the horizontal position of display.

A phase comparator 2 and a low-pass filter (hereinafter, referred to as a low-pass filter)
LPF 3, voltage-controlled oscillator (hereinafter, referred to as VCO) 4, horizontal drive pulse generating circuit 5, and horizontal output circuit 7 constitute a PLL circuit, and a delayed horizontal synchronizing pulse output from variable delay circuit 1 And the phase of the flyback pulse obtained by the horizontal output circuit 7 is adjusted. The phase comparator 2 detects the phase difference between the delayed horizontal synchronization pulse and the flyback pulse, and outputs the VCO
4 is controlled. The horizontal drive pulse generation circuit 5 generates a horizontal drive pulse whose pulse duty, polarity, and the like are controlled from the output of the VCO 4, and supplies the horizontal drive pulse to the horizontal output circuit 7. A flyback pulse is output from the horizontal output circuit 7 and is subjected to deflection control in a horizontal deflection coil (not shown), and is also output to the phase comparator 2.

Here, when the image is distorted in a parallelogram as shown by the solid line in FIG. 2, the delay amount of the variable delay circuit 1 is plotted by the vertical period sawtooth wave obtained by the waveform generation circuit 8. Control as in 3. Since the phase of the flyback pulse follows the phase of the delayed horizontal synchronization pulse by the operation of the PLL circuit, the parallelogram distortion is corrected as shown by the broken line in FIG.

[0008]

However, the conventional parallelogram distortion correction circuit operates the PLL circuit and the AFC loop circuit using the horizontal synchronization pulse whose phase is dynamically changed as a reference signal. In a portion where the phase change is large, if the loop response is not sufficiently fast, it may affect the screen. For example, the upper part of the screen may bend as shown in FIG. 6 as an influence on the screen. At this time, the phase of the flyback pulse is ideally the same as in FIG. 3, but as shown in FIG. 7, the phase is not completely followed before the video period starts.

In such a case, in order to speed up the response of the loop, it is necessary to make a significant circuit modification of the components such as increasing the control sensitivity of the VCO 4 at the expense of the screen jitter performance.

[0010]

In order to solve this problem, the present invention has a configuration in which the same delay as that applied to the horizontal synchronization pulse is applied to the horizontal drive pulse and supplied to the horizontal output circuit. With this configuration, the phase relationship between the two pulses input to the phase comparator of the PLL circuit is always the same, and the phase synchronization state of the PLL circuit is maintained. A screen distortion due to a sharp change in correction that occurs does not occur, and a stable distortion correction circuit can be obtained with a simple circuit configuration.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention has a first variable delay means for delaying a horizontal synchronizing signal or a signal having a specific phase relationship with the horizontal synchronizing signal, The delay amount of the first variable delay unit is changed in a vertical scanning cycle, and is used as a reference signal of a horizontal PLL circuit or a horizontal AFC circuit. This is a distortion correction circuit characterized in that the same delay is given to a horizontal drive pulse and supplied to a horizontal output circuit, and a parallelogram distortion can be corrected with a simple configuration.

The invention according to claim 2 of the present invention relates to a CRT display device having the distortion correction circuit according to claim 1, and a display device free from parallelogram distortion can be easily realized.

(Embodiment 1) An embodiment of a distortion correction circuit according to claim 1 of the present invention will be described below with reference to FIGS.

In FIG. 1, the phase comparator 2, LPF 3, V
The CO 4, the horizontal drive pulse generation circuit 5, the variable delay circuit 6, and the horizontal output circuit 7 constitute a PLL circuit, and include a delayed horizontal synchronization pulse output from the variable delay circuit 1 and a flyback pulse obtained by the horizontal output circuit 7. Operate to match the phase of The phase comparator 2 detects the phase difference between the horizontal synchronization pulse and the flyback pulse delayed by the variable delay circuit 1, and outputs the VCO 4
Control the oscillation frequency of

The horizontal drive pulse generation circuit 5 receives the output of the VCO 4 and generates and outputs a horizontal drive pulse in which the duty and polarity of the pulse are controlled.
After that, it is given to the horizontal output circuit 7. Here, when the image is distorted into a parallelogram as shown by the solid line in FIG. 2, in order to correct the distortion, the vertical delay saw-tooth wave obtained by the waveform Assume that the delay amount is controlled from td1 to td2 as shown in FIG.

The phase of the flyback pulse is the same as the phase of the horizontal synchronization pulse delayed by the operation of the PLL circuit. As shown in FIG. 4, the flyback pulse and the horizontal drive pulse correspond to the storage time tst of the transistor.
, The horizontal drive pulse is also equal to “t”.
The phase changes by the time indicated by "d2-td1". However, since this phase change is generated by the variable delay circuit 6 that generates the same delay as that of the variable delay circuit 1, the phase of the horizontal drive pulse before the delay output from the horizontal drive pulse generation circuit 5 does not change. . That is, even if the phase of the delayed horizontal synchronizing pulse, which is the reference signal input to the PLL, changes, the phase of the flyback pulse follows the operation of the variable delay circuit 6 in the same manner.
Does not cause a phase difference between the two input signals. That is, PLL
The circuit remains phase locked.

As described above, in the conventional example, since the PLL circuit operates to follow the phase change of the reference signal generated by the variable delay circuit 1, the parallelogram distortion correction is realized. In some cases, the response may be a problem. However, in the present invention, the parallelogram distortion correction is realized by the variable delay circuit 6, and the phase change of the flyback pulse is not detected by the phase comparator 2 so that the horizontal delay is not detected by the phase comparator 2. Since the variable delay circuit 1 is operated to similarly delay the synchronization pulse, the PLL circuit can realize a stable operation while maintaining the locked state. Therefore, the present invention is particularly applicable to the case where the correction amount of the parallelogram distortion is large or the horizontal PLL
An object of the present invention is to provide a distortion correction circuit that realizes highly accurate parallelogram distortion correction even when it is difficult to speed up the circuit response.

[0018]

As described above, according to the present invention, the horizontal PL
It is possible to provide a high-performance distortion correction circuit in which the response of the L circuit and the horizontal AFC circuit does not matter.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing parallelogram distortion;

FIG. 3 is a diagram showing a delay amount of a horizontal synchronization pulse when correcting parallelogram distortion;

FIG. 4 is a diagram showing the timing of each waveform.

FIG. 5 is a block diagram showing a conventional parallelogram distortion correction circuit.

FIG. 6 is a diagram showing a bent image at the top of the screen.

FIG. 7 is a diagram showing the phase of a flyback pulse when a bend occurs at the top of the screen.

[Explanation of symbols]

 1, 6 Variable delay circuit 2 Phase comparator 3 Low pass filter (LPF) 4 Voltage controlled oscillator (VCO) 5 Horizontal drive pulse generation circuit 7 Horizontal output circuit 8 Waveform generation circuit

Claims (2)

[Claims] A first variable delay unit for delaying a horizontal synchronizing signal or a signal having a specific phase relationship with the horizontal synchronizing signal, wherein a delay amount in the first variable delay unit is determined by a vertical scanning period. The reference signal of the horizontal PLL circuit or the horizontal AFC circuit is changed, and the same delay as the first variable delay means is given to the horizontal drive pulse by the second variable delay means and supplied to the horizontal output circuit. Distortion correction circuit characterized by things. 2. A C having the distortion correction circuit according to claim 1.
RT display device.