JP2001036765A - Distortion correction circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stabilize distortion correction by varying the frequency dividing ratio of a PLL circuit constituting a horizontal driver pulse generation circuit to a value different from that at a normal time once or plural times in a vertical blanking period. SOLUTION: A pulse outputted from a pulse generation circuit 15 is supplied to a horizontal output circuit 18 as a horizontal drive pulse to make a horizontal deflection current to flow in deflection coil 19. A fly back pulse obtained by the circuit 18 is inputted to a phase comparator 11. When its phase is delayed compared with a horizontal screen position reference pulse, the oscillation frequency of a VCO 13 is raised to advance the phase of the fly back pulse and when the phase is fast compared with the horizontal screen position reference pulse to the contrary, the oscillation frequency of a VCO 13 is lowered to delay the phase of the fly back pulse. An edge detection circuit 111 allows a selector to select the side of a second frequency dividing ratio setting register 110 only in one horizontal period just after a vertical synchronization signal (VS) is inputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a distortion correction circuit for a CRT display device.

[0002]

2. Description of the Related Art Generally, CRT display devices for computers are compatible with various scanning frequencies. Therefore, in order to reduce the distortion of the image at the display of any frequency, various distortion correction circuits capable of adjusting the correction amount are mounted.

[0003] A typical example of distortion in which an image is shifted in the horizontal direction is a parallelogram distortion, and a circuit for correcting the distortion is provided in many display devices.

In the parallelogram distortion, as shown in FIG. 6, an image is inclined in a parallelogram shape, and at that time, a raster as a set of scanning lines is similarly inclined in a parallelogram shape. This is caused by the mechanical inclination of the deflection coil itself, its mounting error, and the non-uniformity of the magnetic field distribution generated by the deflection coil.

In general, in order to correct the parallelogram distortion, there is a method of changing the DC component of the horizontal deflection current by changing the DC component in a vertical cycle as shown in FIG. As described above, there is a method of changing the phase of the horizontal deflection current in a vertical cycle. The former corrects the distortion of the raster itself, while the latter adjusts the phase of the deflection current with respect to the video signal, and is characterized by the raster being distorted in a parallelogram shape.

Since the former technique of dynamically modulating a large current and a high voltage deflection current tends to increase the cost, many display devices use the latter technique which can be handled by a low voltage section and the circuit design is easy.

Further, a circuit for generating a horizontal drive pulse serving as a trigger for causing a horizontal deflection current to flow through a horizontal deflection coil includes:
It is composed of a PLL circuit and absorbs a change in delay generated in the horizontal output circuit, and always receives a flyback pulse (hereinafter FB).
P) is maintained at a predetermined phase.

Some oscillation circuits in the PLL circuit output the same frequency as the horizontal synchronization frequency. However, the oscillation circuit oscillates at a frequency sufficiently higher than the horizontal synchronization frequency. Some are controlled to match. A PLL for so-called clock multiplication is configured.

An example of the horizontal drive pulse generating circuit will be described below with reference to FIGS. The clock generated by the VCO 13 is a clock signal of the programmable counter 14. The dividing ratio setting register 16 has a CPU
From 17 an appropriate value is written according to the horizontal synchronization frequency, and when the value of the programmable counter 14 reaches that value, the counter is cleared. FIG. 2 shows a circuit example of the pulse generation circuit 15.

A pulse signal whose output becomes H when the count value reaches the register 21 and which becomes L when the count value reaches the register 22 is generated by the pulse generation circuit of FIG. The pulse generation circuit 15 and the programmable counter 14 are frequency divider circuits for the clock of the VCO 13.

The pulse output from the pulse generation circuit 15 is supplied to a horizontal output circuit as a horizontal drive pulse, and a horizontal deflection current flows through the deflection coil 19. The flyback pulse obtained by the horizontal output circuit 18 is
If the phase is delayed from the horizontal screen position reference pulse, the output of the phase comparator 11 raises the oscillation frequency of the VCO 13 via the LPF 12, advances the phase of the flyback pulse, and conversely, If the pulse is ahead of the pulse, the oscillation frequency of the VCO 13 is reduced and the phase of the flyback pulse is delayed.

As a result, even if the delay generated in the horizontal output circuit 18 changes, the flyback pulse always operates so as to have the same phase as the horizontal screen position reference pulse. The horizontal screen position reference pulse is generally a pulse having a specific phase relationship that can be controlled with respect to the horizontal synchronizing signal. Based on the horizontal synchronizing signal, a delay circuit or another PL (not shown) is used here.
It is generated by the L circuit.

When correcting a parallelogram distortion in a display device having the above-described horizontal drive pulse generating circuit, the horizontal drive pulse position is changed at a vertical rate as shown in FIG. The PLL constituting the pulse generation circuit is made to follow it. By changing the phase of the flyback pulse, that is, the phase of the deflection in a vertical cycle with respect to the video signal, FIG.
The following correction can be performed.

[0014]

However, since the PLL circuit constituting the conventional horizontal drive pulse generating circuit is a part where the jitter performance is regarded as important, it is designed with the control sensitivity of the VCO suppressed. In the case where the phase is largely changed in the vicinity of the vertical synchronizing signal as described above, it is not possible to follow within the vertical blanking period, and the upper part of the image may bend as shown in FIG.

As a result, it was necessary to reduce the corresponding amount of correction, or to speed up the loop response of the PLL at the expense of some jitter performance.

[0016]

According to the present invention, there is provided a horizontal drive pulse generating circuit comprising:
The phase of the horizontal drive pulse is forcibly changed irrespective of the PLL response by changing the frequency division ratio of the LL circuit once or plural times during the vertical blanking period to a value different from the steady state.

With this configuration, even when it is necessary to greatly change the phase of deflection in the vertical cycle due to the correction of the parallelogram distortion, the amount by which the PLL circuit must change the frequency of the VCO to follow the phase is suppressed. Therefore, even in the case of a PLL circuit using a VCO having low control sensitivity, the image does not bend at the upper portion of the screen, and stable distortion correction can be realized.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention provides a method in which a frequency division ratio of a PLL circuit constituting a horizontal drive pulse generating circuit is set to a value which is different from that in a steady state once or plural times during a vertical blanking period. In this configuration, the phase of the horizontal drive pulse is forcibly changed irrespective of the response of the PLL. With this configuration, it is necessary to greatly change the deflection phase in the vertical cycle by correcting the parallelogram distortion. Even in the case where there is, it is possible to suppress the amount that the PLL circuit has to change the frequency of the VCO and follow the phase, the screen is not bent due to a large change in the phase generated at the top of the screen, and stable distortion correction is performed. It is possible to do.

According to a second aspect of the present invention, a positive integer N is set as a division ratio in a steady state with respect to a frequency of a certain horizontal synchronizing signal, and a division ratio different from that in a steady state is set to N + α (α is an integer). 2. The CRT display device according to claim 1, wherein α in the case of (1) is determined according to the correction amount of the parallelogram distortion. Even if it is necessary to change
It is possible to suppress the amount that the LL circuit has to change the frequency of the VCO to follow the phase, and the screen does not bend due to a large change in the phase that occurs at the top of the screen, enabling stable distortion correction. is there.

(Embodiment 1) An embodiment of the present invention described in claims 1 and 2 of the present invention will be described below with reference to FIGS. 1, 2, 3 and 4. FIG.

In FIG. 1, the clock generated by the VCO 13 is a clock signal of the programmable counter 14. An appropriate value is written in the first frequency division ratio setting register 16 from the CPU 17 in accordance with the horizontal synchronization frequency, and when the value of the programmable counter 14 reaches that value, the counter is cleared.

FIG. 2 shows a circuit example of the pulse generation circuit 15. The pulse generation circuit of FIG. 2 generates a pulse signal whose output becomes H when the count value reaches the register 21 and becomes L when the count value reaches the register 22. The pulse generation circuit 15 and the programmable counter 14 are frequency divider circuits for the clock of the VCO 13.

The pulse output from the pulse generation circuit 15 is supplied to a horizontal output circuit as a horizontal drive pulse, and a horizontal deflection current flows through the deflection coil 19. The flyback pulse obtained by the horizontal output circuit 18 is
If the phase is delayed from the horizontal screen position reference pulse, the output of the phase comparator 11 raises the oscillation frequency of the VCO 13 via the LPF 12, advances the phase of the flyback pulse, and conversely, If the pulse is ahead of the pulse, the oscillation frequency of the VCO 13 is reduced and the phase of the flyback pulse is delayed.

As a result, even if the delay generated in the horizontal output circuit 18 changes, the flyback pulse always operates so as to have the same phase as the horizontal screen position reference pulse. The edge detection circuit 111 outputs 1 immediately after the input of the vertical synchronization signal (VS).
This is a circuit for allowing the selector 112 to select the second frequency division ratio setting register 110 only for the horizontal period.

Here, in order to perform parallelogram distortion correction, FIG.
Consider the case where the phase of the horizontal screen position phase reference pulse changes in the vertical cycle as shown in FIG. In this case, the phase changes greatly before and after the vertical synchronization signal as shown in FIG. FIG. 4 shows the change in the cycle of the horizontal screen position reference pulse. The horizontal screen position reference pulse when the correction of the parallelogram distortion is not performed always has the same period, whereas the correction of the parallelogram distortion is performed. When performing, the cycle gradually changes, and greatly changes during a retrace period of the vertical deflection.

Here, it is assumed that the phase difference of this greatly changing portion is, for example, 5.5 clock periods in the VCO 13 clock. At this time, N + 5 is written in the second frequency division ratio setting register 110 with respect to the value N set in the first frequency division ratio setting register, and the selector 112 is activated once in the vertical cycle. If the division ratio setting register of 2 is selected, the division ratio is increased by 5 by the period, so that the phase of the horizontal drive pulse is delayed by 5 clocks.

Therefore, the need to change the phase in the operation of the PLL can be reduced to 5.5-5 = 0.5 clocks, and the phase can be followed in a short time even when the loop response of the PLL is slow. Is completed, and no problem such as bending at the top of the screen occurs.

The amount by which the phase must be rapidly changed in the vertical cycle is proportional to the correction amount of the parallelogram distortion. Therefore, the CPU corrects the parallelogram distortion,
By determining the value of the second frequency division ratio setting register 22 in consideration of the value N of the first frequency division ratio setting register 21, the correction amount of various parallelogram distortions and the P
VC that can reduce the phase that must be changed by the operation of LL and has high stability and suppressed control sensitivity
O can be used to sufficiently correct parallelogram distortion.

In this embodiment, the CPU directly determines the value of the frequency division ratio setting register 2 and supplies it to the selector. However, the CPU calculates only the portion of α of N + α, and performs the first frequency division. A configuration in which the ratio setting register value N is added by hardware and supplied to the selector may be used. Further, the configuration may be such that α is automatically calculated by hardware according to the correction amount of the parallelogram distortion. Further, the timing of changing the frequency division ratio is not limited to one time in the vertical cycle.

[0030]

As described above, according to the present invention, even if a PLL circuit using a VCO having a low control sensitivity, which is advantageous in jitter performance, is used for a horizontal drive pulse generation circuit, it is possible to prevent the upper portion of the screen from being bent. A high-performance distortion correction circuit having a large parallelogram distortion correction amount can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a pulse generation circuit in FIGS. 1 and 5;

FIG. 3 is a diagram showing an example of a phase change of a horizontal screen position reference pulse when performing parallelogram distortion correction;

FIG. 4 is a diagram showing an example of a change in the cycle of a horizontal screen position reference pulse when performing parallelogram distortion correction;

FIG. 5 is a diagram showing a conventional horizontal drive pulse generation circuit.

FIG. 6 is a diagram showing a state of an image and a raster in which a parallelogram distortion has occurred;

FIG. 7 is a diagram showing a parallelogram distortion correction method;

FIG. 8 is a diagram showing a state in which the response of the PLL is slow and the upper part of the screen is bent.

[Explanation of symbols]

 REFERENCE SIGNS LIST 11 phase comparator 12 low-pass filter (LPF) 13 voltage-controlled oscillator (VCO) 14 programmable counter 15 pulse generation circuit 16 (first) division ratio setting register 17 CPU 18 horizontal output circuit 19 horizontal deflection coil 110 second minute Circumference ratio setting register 111 edge detection circuit 112 selector 21, 22 register 23, 24 comparator 25 JK flip-flop

Claims (2)

[Claims] 1. A CRT display characterized in that a frequency division ratio of a PLL circuit configured to generate a horizontal drive pulse is changed once or plural times during a vertical blanking period to a value different from a normal state. apparatus. 2. For a frequency of a certain horizontal synchronization signal, a positive integer N is set as a division ratio in a steady state, and when a division ratio different from that in a steady state is N + α (α is an integer), α is The CRT display device according to claim 1, wherein the CRT display device is determined according to a correction amount of the parallelogram distortion.