JP4757690B2 - PLL system and in-vehicle television system - Google Patents

Description

  The present invention relates to a high-multiplication PLL (phase-locked loop) circuit for a vehicle-mounted television, and more particularly to a high-multiplication PLL circuit including a virtual synchronization signal generation circuit.

  In general, an in-vehicle television system includes a PLL circuit that generates a clock by comparing the phase of an input horizontal synchronization signal with an internal horizontal synchronization generated in accordance with the horizontal period of a liquid crystal panel.

  The above clock is used to synchronize the entire system with the drawing clock of the liquid crystal panel, and in particular, to display RGB signals such as navigation with one pixel per clock. The navigation screen usually constitutes a one-frame screen (for example, a map screen or a menu screen) by arranging signals for each pixel like a bitmap. Therefore, if the sampling of the video signal and the signal data to be written to the liquid crystal panel are set to 1: 1, there is no video interpolation (horizontal resizing) in horizontal units, thereby displaying a video without jitter.

  FIG. 6 is a schematic configuration diagram of a PLL circuit using a horizontal synchronization signal as an input signal in a conventional in-vehicle television system. As shown in FIG. 6, the PLL circuit includes a phase comparator 8, a loop filter (low-pass filter) 10, a VCO (Voltage Controlled Oscillator) 12, and a frequency divider 14. The PLL circuit inputs a horizontal synchronization signal 6 and outputs a clock.

  FIG. 7 shows an example of the clock output when the input signal is correctly input to the PLL circuit in the conventional in-vehicle television system (FIG. 7 (1)) and the case where the input signal is not input (no signal). This is an example of the clock output (FIG. 7B). When the input signal is correctly generated, the clock output is correctly generated by the PLL circuit.

  However, when the input signal is no signal as shown in FIG. 7B, a desired frequency may not be obtained in the clock output. That is, the frequency of the output clock is increased or decreased depending on the configuration of the PLL circuit (including a portion not shown).

  In particular, in the case of an in-vehicle television, the amplitude of a video signal often decreases due to a weak electric field of a received wave while traveling. In that case, as described above, the horizontal synchronization signal becomes almost equal to no signal, but the output of the PLL circuit also becomes unstable at that time.

  In particular, in the case of an in-vehicle television system, a pulse such as horizontal synchronization may occur in an unexpected place rarely due to engine noise or the like peculiar to in-vehicle equipment. Also, recent in-vehicle devices communicate with each unit via an in-vehicle LAN, and therefore it may take a little longer than before to receive the video switching signal request and reflect it. In such a case, the input horizontal synchronization signal is often in a no-signal state from reception to reflection of the signal request.

  Patent Document 1 is a digital magnetic recording / reproducing apparatus for A / D converting and recording an analog video signal, and a method for generating an optimum A / D conversion sampling clock according to an input signal and A magnetic recording / reproducing apparatus using the same is disclosed.

Japanese Patent Laid-Open No. 08-331597

  An object of the present invention is to form an in-vehicle television that properly forms a clock by a horizontal synchronizing signal even in a no-signal state and a state substantially equal to no-signal.

The present invention has been made to achieve the above object. The PLL system according to claim 1 according to the present invention includes:
A first counter circuit for actually measuring the number of horizontal synchronization signals in one vertical period for the input horizontal synchronization signal ;
A second counter circuit for actually measuring the number of clocks in one horizontal period for the input horizontal synchronization signal;
A comparator circuit for determining an abnormality signal by comparison with the first of said horizontal synchronizing signal number which is actually measured by the counter circuit and the reference value,
When it is determined that the comparison circuit is an abnormal signal, when the number of clocks in one horizontal period measured by the second counter circuit is smaller than the frequency related to the horizontal reference period, the second counter circuit Addition of correction data to the actually measured number of clocks in one horizontal period is output as a virtual horizontal synchronization signal while continuously approaching the horizontal reference period, and the number of clocks in one horizontal period measured by the second counter circuit Is not smaller than the frequency related to the horizontal reference period, the virtual horizontal synchronization signal is obtained by continuously subtracting the correction data from the number of clocks of one horizontal period actually measured by the second counter circuit and approaching the horizontal reference period. If the comparison circuit does not determine that it is an abnormal signal, a virtual synchronization signal generation circuit that outputs an input horizontal synchronization signal;
A PLL circuit that generates a clock signal based on the output of the virtual synchronization signal generation circuit;
Is a PLL system .

The in- vehicle television system according to claim 2 of the present invention is
An in-vehicle television system equipped with the PLL system according to claim 1 .

  By utilizing the present invention, in a vehicle-mounted television system, a clock based on a horizontal synchronization signal can be properly formed even in a no-signal state and a state substantially equal to no-signal.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments according to the invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a schematic configuration diagram of a PLL circuit using a horizontal synchronization signal as an input signal in the in-vehicle television system according to the first embodiment of the present invention. The PLL circuit shown in FIG. 1 includes a phase comparator 8, a loop filter (low-pass filter) 10, a VCO 12, and a frequency divider 14 in the same manner as the PLL circuit shown in FIG. Further, the PLL circuit shown in FIG. 1 includes a virtual synchronization signal generation circuit 2 at the head of the circuit. The virtual synchronization signal generation circuit 2 forms and outputs a virtual horizontal synchronization signal 4 when the input horizontal synchronization signal 6 is an abnormal signal. The switch 18 shown in FIG. 1 is switched depending on whether there is an abnormality in the input horizontal synchronization signal 6.

  FIG. 2 shows an example of a clock output (FIG. 2 (1)) when the input signal is correctly input to the PLL circuit and the input signal in the in-vehicle television system according to the first embodiment of the present invention. Is an example of the clock output when no signal is input (when there is no signal) (FIG. 2 (2)). When the input signal is correctly generated (FIG. 2 (1)), the horizontal synchronizing signal 6 itself becomes the input signal by the switch 18, and the PLL circuit correctly generates the clock output.

  On the other hand, when the input signal is an abnormal signal (for example, no signal) ((2) in FIG. 2), the virtual horizontal synchronizing signal 4 becomes an input signal by the switch 18. Since the virtual horizontal synchronizing signal 4 is a stable signal as will be described later, the PLL circuit at this time stably outputs the clock output. The determination of the presence or absence of abnormality in the input horizontal synchronization signal 6 and the generation circuit of the virtual horizontal synchronization signal 4 will be described later.

  FIG. 3 is a detailed circuit configuration diagram of the virtual synchronization signal generation circuit 2 installed at the head of the PLL circuit in the in-vehicle television system according to the first embodiment of the present invention. FIG. 4 is a configuration diagram focusing on the operation of the same virtual synchronization signal generation circuit 2. First, the operation of the virtual synchronization signal generation circuit 2 will be described with reference to FIG.

  The virtual synchronization signal generation circuit 2 first receives the input horizontal synchronization signal, measures the number of horizontal lines in one vertical period, and determines whether the signal is a normal signal or an abnormal signal (S01). If it is a normal signal, the input horizontal synchronization signal becomes the output horizontal synchronization signal as it is. If it is an abnormal signal, a virtual horizontal synchronizing signal is generated by the circuit operation from S02 onward, and is set as an output horizontal synchronizing signal.

  In the generation of the virtual horizontal synchronization signal, first, the number of clocks in one horizontal cycle period in the input signal is measured to obtain horizontal clock number data (S02). The acquired number of horizontal clocks is compared with the horizontal reference period to classify whether the number of horizontal clocks is greater or less than the horizontal reference period (S03).

  When it is classified as large, “correction data” is gradually subtracted until the horizontal reference period is reached (S04). “Correction data” is a constant value set in the register, and is a gradually decreasing value (gradually increasing value) when the cycle of the virtual horizontal synchronizing signal is brought close to the horizontal reference cycle. On the other hand, when it is classified as small, “correction data” is gradually added until the horizontal reference period is reached (S05). Thus, the reason why the cycle of the virtual horizontal synchronizing signal is gradually brought closer to the horizontal reference cycle is to stabilize the VCO 12. This will be described later.

  A counter reset signal is formed based on the gradually changing “cycle of virtual horizontal synchronization signal” data in S04 and S05. The counter horizontal signal is counted by a counter circuit using the counter reset signal as a reset signal and the system clock as a count-up signal (S06).

  The count value of the counter circuit is compared with the horizontal reference period to form a virtual horizontal period signal (S07). In FIG. 4, 1/16 of the horizontal reference period is set as the reference period. In the case of an NTSC signal, since one horizontal period is 63.5 μs (one horizontal period is 64.0 μs in PAL & SECAM), data is about 4 μs (horizontal synchronization signal width) at [1/16] of the horizontal reference period.

  Next, the configuration of the virtual synchronization signal generation circuit 2 will be described with reference to the circuit configuration diagram of the virtual synchronization signal generation circuit 2 shown in FIG.

From the vertical reference period 24 and the number 22 of abnormal signal determination lines, a normal signal maximum value and a normal signal minimum value regarding “the number of horizontal lines in one vertical period” are obtained. The input horizontal synchronization signal 6 is given a reset signal by the vertical synchronization signal start flag 26, and the counter circuit 30 counts the number of horizontal lines in one vertical period. The number of horizontal lines in one vertical period (number of vertical lines) Data is acquired. The “number of horizontal lines in one vertical period” (number of vertical lines) is compared with the above normal signal maximum value and normal signal minimum value, and if any one of the following determination formulas 1 is satisfied, an abnormality is determined. It becomes normal judgment. At the time of abnormality determination, the abnormality determination flag is “1”, and at the time of normal determination, the abnormality determination flag is “0”.
[Judgment formula 1]
“Number of horizontal lines in one vertical period” (number of vertical lines)> normal signal maximum value “Number of horizontal lines in one vertical period” (number of vertical lines) <Minimum normal signal value

  First, if abnormality determination = “0”, the switch 18 outputs the input horizontal signal 6 as it is. If abnormality determination = “1”, a virtual horizontal periodic signal formed as follows is output.

  A start flag is derived from the input horizontal synchronization signal 6 (28), and is used as a reset signal to acquire horizontal clock number data by the counter circuit 44 (46). Whether the acquired horizontal clock number data (28) is larger or smaller than the horizontal reference period 50 is classified (52). If there are more, the switch 66 selects the reset signal generated at the lower part β of the virtual horizontal synchronization signal reset signal generation part in the substantially central part of FIG. If less, the switch 66 selects a reset signal generated at the upper portion α of the virtual horizontal synchronization signal reset signal generation portion in the substantially central portion of FIG.

  In the lower part β of the virtual horizontal synchronizing signal reset signal generation portion at the substantially central portion in FIG. 3, the horizontal clock number data is taken in by the switch 58 and the horizontal clock number data is reduced by the correction data. A reset signal is formed based on the reduced horizontal clock number data and is input to the counter circuit 68 to generate a virtual horizontal synchronizing signal (70). On the other hand, the horizontal clock number data reduced by the correction data is compared with the horizontal reference period 50 by the data comparison unit 74, and if there is a difference, it is corrected (subtracted) again by the correction data. The horizontal clock number data continues to be corrected (subtracted) by the correction data as long as there is a difference from the horizontal reference period 50. That is, the horizontal clock number data is gradually reduced and becomes the basis of the reset signal of the virtual horizontal synchronization signal. The switch 60 is a switch that updates data when the abnormality determination flag changes from “normal” to “abnormal”.

  Similarly, in the upper part α of the virtual horizontal synchronization signal reset signal generation part in the substantially central part of FIG. 3, the horizontal clock number data is taken in by the switch 60 and the horizontal clock number data is increased by the correction data. A reset signal is formed based on the increased horizontal clock number data, and is input to the counter circuit 68 to generate a virtual horizontal synchronizing signal (70). On the other hand, the horizontal clock number data increased by the correction data is compared with the horizontal reference period 50 by the data comparison unit 74, and if there is a difference, it is corrected (added) again by the correction data. The horizontal clock number data continues to be corrected (added) by the correction data as long as there is a difference from the horizontal reference period 50. That is, the horizontal clock number data becomes the basis of the reset signal of the virtual horizontal synchronization signal while being gradually increased. The switch 58 is also a switch whose data is updated when the abnormality determination flag changes from “normal” to “abnormal”.

  As described above, when the signal generated by the virtual horizontal synchronization signal generation unit 70 has a target period (frequency), a signal from the horizontal reference period is output as a virtual horizontal synchronization signal.

  The reset pulse generator 38 is a circuit that forcibly generates a reset pulse when the input horizontal synchronization signal lacks a rising ridge.

  FIG. 5 is a circuit configuration diagram (FIG. 5 (1)) of the PLL circuit and the virtual synchronization signal generation circuit 2 installed at the head of the vehicle-mounted television system according to the first embodiment of the present invention, and It is an example (FIG. 5 (2)) of the virtual horizontal synchronizing signal produced | generated by the virtual synchronizing signal generation circuit 2. FIG. As described above, in the generated virtual horizontal synchronizing signal, the frequency is gradually brought closer to the target from the time of the start of the abnormal signal (at the time of switching). In FIG. 5 (2), the state is shown by a dotted line. The PLL circuit compares the virtual horizontal synchronizing signal with the phase reference signal and outputs a clock.

  The frequency of the virtual horizontal synchronizing signal is gradually changed for the following reason. When the virtual horizontal synchronizing signal is suddenly set to the target frequency, that is, when the oscillation frequency is rapidly moved, an oscillation phenomenon occurs in the loop filter 10 and the VCO 12 becomes unstable. Then, the output clock frequency becomes unstable until the oscillation phenomenon converges (see the thick dotted line in FIG. 5 (2)). In order to avoid such a phenomenon, it is preferable to gradually change the frequency.

  By using a PLL circuit including the virtual synchronization signal generation circuit 2 as described above, an in-vehicle television that appropriately forms a clock based on a horizontal synchronization signal can be formed even in a no-signal state and a state substantially equal to no-signal.

[Other Embodiments]
The present invention is not limited to the first embodiment. For example, in the determination of the abnormal signal, the number of horizontal lines in one vertical period is used, but other values (for example, the fluctuation range of the signal) may be used.

1 is a schematic configuration diagram of a PLL circuit using a horizontal synchronization signal as an input signal in the in-vehicle television system according to the first embodiment of the present invention. In the in-vehicle television system according to the first embodiment of the present invention, an example of the clock output when the input signal is correctly input to the PLL circuit (FIG. 2 (1)) and the case where the input signal is not input It is an example (FIG. 2 (2)) of the clock output of (when there is no signal). 1 is a detailed circuit configuration diagram of a virtual synchronization signal generation circuit installed at the head of a PLL circuit in an in-vehicle television system according to a first embodiment of the present invention. It is a block diagram which paid its attention to operation | movement of the virtual synchronizing signal generation circuit installed in the head part of the PLL circuit in the vehicle-mounted television system which concerns on the 1st Embodiment of this invention. FIG. 5A is a circuit configuration diagram of a PLL circuit and a virtual synchronization signal generation circuit installed at the head of the in-vehicle television system according to the first embodiment of the present invention, and the virtual synchronization signal generation circuit. 6 is an example of the virtual horizontal synchronization signal generated by the above (FIG. 5B). It is a schematic block diagram of the PLL circuit which uses a horizontal synchronizing signal as an input signal in the conventional in-vehicle television system. An example of clock output when the input signal is correctly input to the PLL circuit in the conventional in-vehicle television system (FIG. 7 (1)) and a clock when the input signal is not input (when there is no signal) It is an example of an output (FIG. 7 (2)).

Explanation of symbols

2 ... virtual synchronization signal generation circuit, 8 ... phase comparator, 10 ... loop filter, 12 ... VCO (voltage controlled oscillator), 14 ... frequency divider.

Claims (2)

A first counter circuit for actually measuring the number of horizontal synchronization signals in one vertical period for the input horizontal synchronization signal ;
A second counter circuit for actually measuring the number of clocks in one horizontal period for the input horizontal synchronization signal;
A comparator circuit for determining an abnormality signal by comparison with the first of said horizontal synchronizing signal number which is actually measured by the counter circuit and the reference value,
When it is determined that the comparison circuit is an abnormal signal, when the number of clocks in one horizontal period measured by the second counter circuit is smaller than the frequency related to the horizontal reference period, the second counter circuit Addition of correction data to the actually measured number of clocks in one horizontal period is output as a virtual horizontal synchronization signal while continuously approaching the horizontal reference period, and the number of clocks in one horizontal period measured by the second counter circuit Is not smaller than the frequency related to the horizontal reference period, the virtual horizontal synchronization signal is obtained by continuously subtracting the correction data from the number of clocks of one horizontal period actually measured by the second counter circuit and approaching the horizontal reference period. If the comparison circuit does not determine that it is an abnormal signal, a virtual synchronization signal generation circuit that outputs an input horizontal synchronization signal;
A PLL circuit that generates a clock signal based on the output of the virtual synchronization signal generation circuit;
A PLL system. An in-vehicle television system equipped with the PLL system according to claim 1 .

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