JP2002258824A - Conversion circuit for synchronizing frequency - Google Patents

Abstract

PROBLEM TO BE SOLVED: To convert the synchronizing frequency of an input video signal, so that a CRT copes properly to multiple pairs of horizontal and vertical synchronizing frequencies. SOLUTION: Provided is a memory 43, to which an input video signal is written with a write control signal varying in synchronism with the horizontal and vertical synchronizing signals of the input video signal. A decision circuit 52 is provided, which decides the horizontal and vertical synchronizing frequencies of the input video signal. A 2nd generation circuit 43 generates a readout control signal, which has a nearly constant horizontal synchronizing frequency, regardless of the horizontal synchronizing frequency of the input video signal and a vertical synchronizing frequency as an integral multiple of the vertical synchronizing frequency of the input video signal according to the decision result of the decision circuit 52. When the 2nd generating circuit 43 generates the readout control signal, a circuit 54 normalizes the vertical synchronism of the readout control signal with the vertical synchronizing signals of the input video signal. The written video signal is read out of the memory 43 and is set as the output video signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a circuit for converting a synchronous frequency of a video signal.

[0002]

2. Description of the Related Art A display device used in a television receiver, a personal computer, or the like often uses a CRT as a display means or a display element.

[0003]

However, the specifications of video signals sent from a computer or the like to a display device are not uniform, and the synchronization frequency, video display period, video retrace period, and the like are various. ing. For this reason,
Among display devices using a CRT, a CRT display called a multi-scan display (CRT)
The monitor is adapted to support multiple sets of horizontal and vertical synchronization frequencies.

In this case, as a method for a CRT display to cope with a plurality of sets of horizontal and vertical synchronization frequencies, the horizontal and vertical deflection frequencies (synchronization frequencies) of the CRT are made variable. Then, the horizontal and vertical deflection frequencies are changed so as to match the horizontal and vertical synchronization frequencies of the input video signal. The horizontal and vertical deflection frequencies in a CRT are fixed at a single frequency. Then, the horizontal and vertical synchronization frequencies of the input video signal are converted into horizontal and vertical deflection frequencies of the CRT by performing an interpolation process and a thinning process on the input video signal. It has been known.

However, in the case of the method (1), the range of the horizontal deflection frequency is widened. Therefore, in order to stably obtain a high voltage for horizontal deflection and CRT, a separate system in which a horizontal deflection circuit and a high voltage generation circuit are separated from each other. Is the basis.

However, even in such a case, since the horizontal deflection circuit must be synchronized with a wide range of frequencies, it has been difficult to design synchronization performance, for example, jitter performance well.

Further, when the horizontal deflection frequency changes, the horizontal size of the display screen changes. Therefore, it is necessary to control the power supply of the horizontal deflection circuit according to the horizontal deflection frequency. Further, it is necessary to switch the horizontal S-shaped correction capacitor according to the horizontal deflection frequency, and for this switching, it is necessary to use an FET having a high withstand voltage as a switch.

Further, tracking adjustment for frequency characteristics of the horizontal deflection circuit must be performed. Also, if the frequency of the horizontal drive pulse suddenly changes due to the characteristics of the horizontal deflection circuit, it will result in destruction. Therefore, it is necessary to properly execute a protection procedure. Furthermore, since the response when controlling the main deflection and the high voltage changes depending on the horizontal scanning frequency, setting the design parameters is difficult, and in some cases, the parameters need to be switched according to the horizontal scanning frequency.

Furthermore, in recent years, the synchronization frequency of a video signal has become
As the resolution of the display screen becomes finer, it is getting higher. As a result, for example, the horizontal synchronization frequency is lower than NT
It is desired that the signal be able to cope with the SC signal from 15.75 kHz to 130 kHz or more for high-performance workstations. Therefore, the horizontal deflection circuit for multi-scan is
Compared with a horizontal deflection circuit having a single horizontal deflection frequency, the circuit and the system become considerably complicated.

The vertical deflection circuit has the same problem as the horizontal deflection circuit. However, since the frequency of a signal to be handled is much lower than that of the horizontal deflection circuit, the burden is considerably smaller than that of the horizontal deflection circuit. Is easy.

On the other hand, in the case of the method, since there is no need to change the deflection frequency, there is no problem as in the case of the method.

However, in the case of the method (1), interpolation or thinning is performed on an input video signal, so that, for example, a point or a line that should be displayed by one dot is represented by two dots on a display screen. Displayed, or conversely 2
A point or line to be displayed by one dot is displayed by one dot. Moreover, such a phenomenon does not occur uniformly, for example, every three dots.

As a result, when text characters or graphics are displayed, the outline is blurred and the display quality is significantly reduced. In particular, in the case of a display device for a workstation, for example, in which display quality is required to be extremely strict, deterioration in image quality due to interpolation or thinning of display data is not allowed.

Further, a digital filter or the like is used for the interpolation processing, but the digital filter occupies a large proportion in the hardware LSI. Furthermore, since the frequency range of the signal to be handled is wide and high, the operating frequency of the interpolation arithmetic unit also becomes a very high value, and it is difficult to appropriately cope with the operation frequency.

For the above reasons, the following method is generally employed in the multi-scan monitor. However, at that time, the above problems have not been solved.

The present invention has been made in view of the above points,
An object of the present invention is to solve the problems as in the case of the above method without increasing the hardware and to improve the display quality of the moving image.

[0017]

According to the present invention, for example, a first forming circuit for forming a write control signal which changes in synchronization with horizontal and vertical synchronizing signals of an input video signal; A memory into which the input video signal is written, a discriminating circuit for discriminating the horizontal and vertical synchronization frequencies of the input video signal, and a discrimination result of the discrimination circuit, regardless of the horizontal and vertical synchronization frequencies of the input video signal A second forming circuit for forming read control signals having substantially constant horizontal and vertical synchronizing frequencies; and when the second forming circuit forms the read control signal, the read operation is performed for each vertical synchronizing signal of the input video signal. A circuit for regulating the vertical synchronization of the control signal, wherein the image is written from the memory to the memory by the read control signal. It reads the items, it is an conversion circuit of the synchronization frequency set as the output video signal a video signal thus read out. Therefore, a video signal having a substantially constant horizontal synchronization frequency is read from the memory regardless of the horizontal synchronization frequency of the input video signal.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Now, an input video signal is written into a frame memory in synchronization with its horizontal and vertical synchronization frequencies, and the written video signal is written in synchronization with the horizontal and vertical deflection frequencies of a CRT. It shall be read.

In this case, when writing the input video signal to the frame memory, it is assumed that the input video signal is written for each dot displayed by the video signal. The reading of the video signal from the frame memory is also performed in dot units, and it is assumed that the readout is performed for each dot without excess or deficiency.

First, consider the horizontal deflection of the CRT as follows. That is, when reading a video signal from the frame memory, as shown in FIG. 4, each dot displayed on the CRT and each cycle of the read clock CLKR correspond to each other on an arbitrary horizontal line (the horizontal and vertical lines). Since the total number of dots in one second = the number of dots in one line × the number of horizontal lines in one second, the frequency fcrl of the read clock CLKR is fcrl = (nhscn + nhblk) · fhdef (1) ) nhscn: number of dots in horizontal video period (horizontal effective scanning period) nhblk: number of dots in horizontal blanking period fhdef: horizontal deflection frequency (output horizontal synchronization frequency) of CRT

When the read clock CLKR is formed by a PLL, fclkr = N · fref (2) N: frequency division ratio of a frequency divider of the PLL fref: frequency of a reference signal of the PLL.

Therefore, from equations (1) and (2), N = fclkr / fref = (nhscn + nhblk) fhdef / fref (3)

However, actually, since the frequency division ratio N is an integer, the equation (3) further satisfies N = int (fclkr / fref + 0.5) = int ((nhscn + nhblk) fhdef / fref + 0.5) ... (4)

Here, int (x) is a function that rounds the value x down to the decimal point to make it an integer. Therefore, int (x + 0.
5) is a value obtained by rounding off the decimal part of the value x. Therefore, the dividing ratio N obtained by the expression (4) is a value obtained by rounding off the decimal part of the dividing ratio N obtained by the expression (3) and converting it to an integer. If the error does not matter, It may be rounded down to an integer.

When the frequency division ratio N obtained by the equation (4) (or the equation (3)) is used, the actually obtained frequency fclkr0 of the read clock CLKR is fclkr0 = int ((nhscn + nhblk) fhdef / fref + 0 .5) fref (5) Therefore, the actual horizontal deflection frequency f of the CRT
hdef0 is fhdef0 = 1 / (nhscn + nhblk) .fclkr0 = int ((nhscn + nhblk) fhdef / fref + 0.5)) / (nhscn + nhblk) .fref (6)

The horizontal flyback period thblk in the CRT
0 becomes thblk0 = nhblk / fclk0 (7).

That is, when the video signal is read from the frame memory, if the frequency division ratio N is set to the value shown by the equation (4), the frequency fclkr0 of the read clock CLKR becomes the value shown by the equation (5). As shown in FIG. 4, each dot of the video can be associated with each cycle of the read clock CLKR, and each dot can be read and displayed without excess or deficiency. At this time, even if the resolution changes, the horizontal deflection frequency fhdef0 of the CRT becomes a value shown by the equation (6), and becomes substantially constant.

On the other hand, the vertical deflection of a CRT is as follows. That is, horizontal deflection frequency = vertical deflection frequency × number of horizontal lines per vertical period or vertical deflection frequency = horizontal deflection frequency / number of horizontal lines per vertical period (8).

Then, in this case, the horizontal deflection frequency is the value f
Since hdef0 is constant, when a video signal is read from the frame memory, the vertical cycle of the readout changes according to the number of horizontal lines of the video signal to be read (the number of horizontal lines per vertical period).

Therefore, in the video signal supplied to the CRT, the vertical deflection frequency fvdef0 is fvdef0 = fhdef0 / (nhscn + nhblk) (9) nvscn: the vertical video period (vertical effective scanning period) of the input video signal ) The number of horizontal lines nvblk: The number of horizontal lines in the vertical blanking period. Also, the vertical blanking period tvblk0 in the CRT
Is as follows: tvblk0 = nvblk / fhdef0 (10)

Therefore, the vertical deflection frequency of the CRT also changes. However, as mentioned above, the vertical deflection frequency is much lower than the horizontal deflection frequency,
The burden associated with the vertical deflection circuit is fairly small.

When an image is displayed on a CRT by the above-described method, the image signal is simply written and read out to and from the frame memory in dot units of the input image signal. Since no processing such as thinning or thinning is performed, the display quality hardly deteriorates.

Further, since it is not necessary to change the horizontal deflection frequency of the CRT even if the resolution is changed, the configuration of the horizontal deflection circuit is simplified, and appropriate horizontal deflection can be performed even if distortion correction or the like is required. it can.

As is apparent from equation (9), as the number of horizontal lines nvscn increases, the vertical deflection frequency fvdef0 decreases, and flicker on the CRT becomes noticeable. Therefore, when the number of horizontal lines nvscn is the largest input video signal, the horizontal deflection frequency fhdef0 is set so that flicker on the CRT is not noticeable.

According to the present invention, first, a synchronous frequency conversion circuit capable of coping with a plurality of sets of synchronous frequencies is constructed in accordance with the above-described concept. Hereinafter, one embodiment of the present invention will be described.

In FIG. 1, an input video signal S11 is supplied from an input terminal 11 to a synchronous frequency conversion circuit 14 through an input interface circuit 13. Further, a horizontal and vertical synchronization signal Ssync corresponding to the input video signal S11 is supplied from the input terminal 12 to the synchronization frequency conversion circuit 14 through the interface circuit 13.

In this case, it is assumed that the video signal S11 is a three primary color signal composed of red, green and blue signals.
Although the details of the conversion circuit 14 will be described later, the conversion circuit 14 has a frame memory, and converts the synchronization frequency of the supplied video signal S11 and outputs the video signal S14 according to the above idea. is there.

The output video signal S 14 is supplied to the color CRT 17 through the video drive circuit 16 after the video control circuit 15 performs processing such as gamma correction.

The conversion circuit 14 outputs a horizontal synchronization signal H synchronized with the output video signal S14 as shown in FIG.
out is taken out, and the horizontal synchronization signal Hout is supplied to the horizontal deflection circuit 21 to form a horizontal deflection current. Then, the horizontal deflection current is supplied to the horizontal deflection coil 22, and the horizontal deflection of the CRT 17 is performed. Note that the horizontal deflection frequency at this time is a value fhdef0.

Further, a horizontal pulse is taken out from the horizontal deflection circuit 21, and the horizontal pulse is supplied to a high voltage generation circuit 23 to form a high voltage. The high voltage is supplied to the CRT 17 as an anode voltage or the like.

Further, the output video signal S
A vertical synchronizing signal Vout synchronized with 14 is taken out, and this vertical synchronizing signal Vout is supplied to a vertical deflection circuit 24 to form a vertical deflection current. This vertical deflection current is supplied to a vertical deflection coil 25 to cause a vertical deflection of the CRT 17 to be performed. Is performed.
Note that the vertical deflection frequency at this time is a value fvdef0.

In this case, the synchronous frequency conversion circuit 1
4 is configured, for example, as shown in FIG. That is,
The input video signal S11 from the interface circuit 13 is
The signal is supplied to the A / D converter circuit 42 and A / D-converted into a digital video signal S12. This signal S12 is supplied to the frame memory 43.

The horizontal synchronizing signal Hin of the synchronizing signal Ssync is taken out from the interface circuit 13 and supplied to the PLL 51 to form a pulse signal S51 having a frequency corresponding to the dot cycle of the input video signal S11. The pulse signal S51 is supplied to the A / D converter circuit 42.
Is supplied as a clock at the time of the A / D conversion, and the input video signal S11 is A / D converted as described above for each dot when the display is performed by the signal S11.

Further, the horizontal and vertical synchronizing signals Ssync from the interface circuit 13 are supplied to the signal discriminating circuit 52, and the horizontal and vertical synchronizing frequencies of the input video signal S11, the temporal position of the horizontal and vertical video periods, and the like are provided. Is determined, and the determined output is supplied to the timing control circuit 53.

The timing control circuit 53 is constituted by a microcomputer, a DSP or a hard logic. The control circuit 53 calculates the input video signal S11 and the input video signal S11 from the information indicated by the discrimination output of the signal discrimination circuit 52 by calculation or by referring to a look-up table prepared in advance in a nonvolatile memory or the like. The number of dots in one horizontal period of the output video signal S14, the number of horizontal lines in one vertical period, the temporal position of horizontal and vertical video periods (scanning periods), and the like are required to convert the synchronization frequency of the video signal. Data.

The output of the control circuit 53 is supplied to a timing pulse generation circuit 54. PLL5
The pulse signal S51 from the timing pulse generation circuit 5
4 and the horizontal and vertical synchronizing signals Hin and Vin are taken out of the interface circuit 13 and supplied to the timing pulse generating circuit 54.

Thus, the timing pulse generating circuit 54
, A timing signal S4W is formed. This timing signal S4W is stored in the frame memory 43 as the video signal S12.
Is a signal indicating the timing when writing is performed, and includes a signal indicating the temporal position of the horizontal and vertical video periods.

The timing signal S4W is supplied to the memory controller 55, and the pulse signal S51 from the PLL 51 is supplied to the memory controller 55. Thus, in the memory controller 55, a control signal S5W for writing the input video signal S12 to the frame memory 43 is formed, and this signal S5W is supplied to the frame memory 43.

The control signal S5W includes a write clock, a write address signal, and a write enable signal for writing the video signal S12 in the frame memory 43. These signals include the effective dot of the input video signal S12 and the write enable signal. It is changing in synchronization with the line.

Therefore, of the input video signal S12, the signal of the signal section serving as the display screen is sequentially written into the frame memory 43 for each dot without excess or deficiency.

The input video signal S12 written in the frame memory 43 is read out in synchronization with the horizontal and vertical deflection of the CRT 17. That is, VCO 61
, An oscillation signal S61 having a predetermined frequency is extracted, and the oscillation signal S61 is supplied to the variable frequency dividing circuit 62. The variable frequency dividing circuit 62 and the VCO 61 constitute the PLL 60 together with the circuits 63 to 65.

Then, from the timing control circuit 53, (4)
The frequency dividing ratio N obtained according to the equation is taken out, the frequency dividing ratio N is set in the variable frequency dividing circuit 62, and the oscillation signal S61 is frequency-divided into a frequency of 1 / N from the variable frequency dividing circuit 62. The divided signal S62 is extracted, and the divided signal S62 is supplied to the phase comparison circuit 63. Further, in the forming circuit 64, a reference signal S64 having a stable frequency fref as a reference is formed, and this signal S64 is supplied to the comparing circuit 63.

In this way, in the comparison circuit 63, the phase of the frequency-divided signal S62 is compared with the phase of the reference signal S64, and the comparison output is supplied to the loop filter 65 to correspond to the phase difference between the frequency-divided signal S62 and the reference signal S64. A DC voltage having a varying level is extracted. Then, this DC voltage is supplied to the VCO 61 as its control voltage.

Therefore, in the steady state, the signals S62 and S64
Are equal to each other, the expression (2) is established. As a result, the frequency of the oscillation signal S61 of the VCO 61 is set to the frequency fclkr0 shown by the expression (5).

Then, the signal S61 is supplied to the timing pulse generating circuit 54 as the read clock CLKR to form the horizontal synchronizing signal Hout and the vertical synchronizing signal Vout. These synchronization signals Hout and Vout are supplied to the deflection circuits 21 and 24 as described above, and the CRT 17 performs horizontal and vertical deflection at the frequencies fhdef0 and fvdef0.

In the timing pulse generating circuit 54, the signal S61 (read clock CL) supplied thereto is supplied.
KR) in synchronization with the timing signal S4R. The timing signal S4R is a signal indicating the timing when the video signal S13 is read from the frame memory 43.
The signal includes a signal indicating the temporal position of the horizontal and vertical video periods.

The timing signal S4R is supplied to the memory controller 55, and a control signal S5R for reading the output video signal S13 from the frame memory 43 is formed. The signal S5R is supplied to the frame memory 43. The control signal S5R includes, for example, a read clock CLKR for reading the video signal S13 from the frame memory 43, a read address signal, and a read enable signal RDEN as shown in FIG.

Accordingly, as shown in FIG. 4, for example, the horizontal frequency has a value fhd from the frame memory 43 regardless of the horizontal and vertical synchronization frequencies of the input video signal S12.
An output video signal S13 which is constant at ef0 and whose vertical frequency changes in accordance with the number of horizontal lines of the input video signal S11 is extracted.

Then, the extracted video signal S13
Is supplied to the D / A converter circuit 44,
The pulse signal S61 from the VCO 61 is supplied to the D / A converter circuit 44 as a clock for D / A conversion.
Thus, the video signal S13 is output to the D / A converter circuit 44.
In the above, the analog three primary color signals, that is, red, green and blue video signals S14 are D / A converted, and this signal S14 is supplied to the color CRT 17 through the video control circuit 15 and the video drive circuit 16 as described above. .

Thus, according to the display device and the synchronous frequency conversion circuit shown in FIGS. 1 and 2, the horizontal deflection frequency can be set to a constant value fhdef0 for a plurality of sets of synchronous frequencies. Therefore, the horizontal deflection frequency of the CRT 17 becomes constant with respect to a plurality of sets of synchronization frequencies, so that the horizontal deflection circuit 22 only needs to synchronize with the constant frequency fhdef0, and the synchronization performance such as jitter performance is improved.

Moreover, in this case, the video signal S11 is only written and read from the frame memory 43 in dot units of the input video signal S12, and no processing such as interpolation or thinning is performed. Since it is not performed, the display quality hardly deteriorates.

However, with the above configuration only, the writing of the video signal S12 to the frame memory 43 and the reading of the video signal S13 from the frame memory 43 are performed independently, so that the input video signal S12 and the output video signal It is not synchronized with S13. Therefore, the difference between the vertical frequency of the input video signal S12 and the vertical frequency fvdef0 of the output video signal S13 is absorbed in the frame memory 43.
When the output video signal S13 is read from the frame memory 43, the same frame may be repeatedly read once every several frames, or may not be read.

In this case, a moving image moving at a uniform speed in the screen normally becomes a jerky movement.
For example, as shown in FIG. 5B (the vertical direction is the direction of time flow), when the car is moving at a uniform speed in the input video signal S12, one frame is repeatedly read from the frame memory 43. If so, in the output video signal S13, the movement is as shown in FIG. 5A, and it is as if the movement of the car stopped for a moment. Conversely, the input video signal S
In 12, if one frame is not read from the frame memory 43 when the car is moving at a uniform speed, the output video signal S13 has a movement as shown in FIG. It's as if you jumped.

As described above, when the input video signal S12 and the output video signal S13 are asynchronous, especially when the motion of the image is large, the motion looks unnatural.

Therefore, in the present invention, such a problem is solved to improve the display quality. For this reason, in the present invention, the frequency of the output vertical synchronizing signal Vout (vertical deflection frequency fvdef0) is set to M times (M is a positive integer) the frequency of the input vertical synchronizing signal Vin. The speed at which the video signal S13 is read is set.

In this case, the output vertical synchronizing frequency (vertical deflection frequency fvdef0) cannot be simply set to an integral multiple (M times) of the frequency of the input vertical synchronizing signal Vin, but as is clear from the equation (9). Since the output vertical synchronization frequency fvdef0 also changes depending on the number of horizontal lines nvblk in the vertical blanking period, the output vertical synchronization frequency fvdef0 is changed or adjusted by changing or adjusting the number of horizontal lines nvblk in the vertical blanking period.
vdef0 can be an integral multiple of the frequency of the input vertical synchronization signal Vin.

Further, in the present invention, the main part of the timing pulse generating circuit 54 is configured, for example, as shown in FIG. That is, the horizontal counter 541 is constituted by a presettable up counter, and the read clock CLKR from the PLL 60 is supplied as a count input (clock input). Further, the reset terminal R of the counter 541 is set to “L” level, and the enable terminal EN is set to “H” level.

Further, a value obtained by subtracting “1” from the number of dots per one horizontal period (nhscn) is obtained from the timing control circuit 53.
+ Nhblk-1) is output, and this data is output to the counter 54 through the preset terminal DATA of the counter 541.
Preset to 1. Note that this preset is executed when the synchronization frequency of the input video signal S11 supplied to the terminal 11 changes. The counter 541 is
When the decoder has a built-in decoder and the count value becomes a preset value, the output terminal Q is set to “H” level.

Therefore, the counter 541 operates at the clock CL
Counts KR and counts clock CL
Since it restarts every (nhscn + nhblk) pieces of KR,
The output terminal Q of the counter 541 outputs a pulse Ph having a pulse width of one clock period (one clock period of the clock CLKR) every time (nhscn + nhblk) clocks CLKR are counted. That is, the frequency of the pulse Ph is the horizontal synchronization frequency fhdef0 of the output video signal S13.

Then, the pulse Ph is supplied to the horizontal synchronizing signal forming circuit 542 to form the horizontal synchronizing signal Hout, and the horizontal synchronizing signal Hout is supplied to the horizontal deflection circuit 21 as described above, and the CRT 17 has the frequency fhdef0. Horizontal deflection is performed.

The vertical counter 543 is constituted by a presettable up counter, and the read clock CLKR from the PLL 60 is supplied as a count input (clock input). Further, the pulse Ph from the counter 541 is supplied to the counter 5 through an AND circuit 548 described later.
It is supplied to the enable terminal EN of 43.

The value (nvscn +) obtained by subtracting “1” from the number of lines per vertical period from the timing control circuit 53 is obtained.
nvblk-1) is output, and this data is output to the counter 543 through the preset terminal DATA of the counter 543.
Preset to. Note that this preset is
1 is executed when the synchronizing frequency of the input video signal S11 supplied to 1 changes. The counter 543 has a built-in decoder, and it is assumed that the output terminal Q becomes “H” level when the count value becomes a preset value.

Therefore, if the reset terminal R of the counter 543 is at "L" level,
Counts the clock CLKR for each pulse Ph, and the count is (nvscn + nvbl) of the pulse Ph.
k), the pulse Pv having a pulse width of one clock period (one clock period of the clock CLKR) is output from the output terminal Q of the counter 543 every (nhscn + nhblk) of the pulses Ph. . That is, the frequency of the pulse Pv is the vertical synchronization frequency fvdef0 of the output video signal S13.

Then, the pulse Pv is supplied to the vertical synchronizing signal forming circuit 544 to form a vertical synchronizing signal Vout. The vertical synchronizing signal Vout is supplied to the horizontal deflection circuit 21 as described above, and the CRT 17 has the frequency fvdef0. Performs vertical deflection. Although not shown, the timing signals S4W and S5W supplied from the timing pulse generation circuit 54 to the memory controller 55 include pulses Ph and Pv as signals indicating the timings of the output synchronization signals Hout and Vout. .

Further, the presettable up counter 5
46 are provided. The counter 546 is for adjusting the phase of the output vertical synchronization signal Vout and synchronizing with the input vertical synchronization signal Vin. The output pulse Pv is supplied to the vertical counter 543 as a count input (clock input). The input vertical synchronizing signal Vin is supplied to the reset terminal R, and the enable terminal EN is set to the “H” level.

Further, the output video signal S with respect to the vertical synchronizing frequency of the input video signal S12 is output from the timing control circuit 53.
Data of a value m (= M−1) obtained by subtracting “1” from the multiple M of the 13 vertical synchronization frequencies fvdef0 is output, and this data is preset in the counter 546 through the preset terminal DATA of the counter 546. For example, as shown in FIGS. 6A and 6B, the vertical synchronization frequency fvdef0 of the output video signal S13 is
If the vertical synchronizing frequency of the input video signal S12 is four times (M = 4), the data of the value 3 (= m) is counted by the counter 546.
Preset to. The output terminal Q of the counter 546 is supplied to the AND circuit 548 through the inverter circuit 547.
Connected to.

The preset value m for the counter 546 is determined by the input video signal S 11 supplied to the terminal 11.
Is executed when the synchronizing frequency changes. It is also assumed that the counter 546 has a built-in decoder, and the output terminal Q goes to “H” level when the count value reaches the preset value m.

Therefore, in the case of FIG. 6 (when m = 3)
Is taken as an example, as shown in FIGS.
6 at the time point t0, the input vertical synchronization signal V
reset to “0” by “in”.
As shown in D, the output Q546 of the counter 546 is "L".
At the same time, as shown in FIG. 6E, the output Q547 of the inverter circuit 547 becomes "H" level.

Then, as shown in FIGS. 6B and 6C,
The count value C546 increases by “1” for each output vertical synchronization signal Vout, and Q546 = “L”, Q547
= “H” continues.

However, when the count value C546 reaches the preset value 3 (= m) at the time point t1, Q546 = “H” and Q547 = “L”.
The pulse P supplied to the counter 543 through 48
h is blocked by its AND circuit 548 and no longer supplied to the counter 543. Therefore, after time t1, the count of the counter 543 stops, and the pulse Pv is no longer output. This also stops the counter 546 from counting.

However, at time t2 when one vertical period (one vertical period of the input video signal S12) has elapsed from time t0, the input synchronization signal Vin is obtained again, and this synchronization signal Vin is obtained.
The count value C546 is reset to "0" by
= "L" and Q547 = "H".

Therefore, the operation after time t0 is repeated after time t2, so that the pulse Pv and the output vertical synchronizing signal Vout are synchronized with the input vertical synchronizing signal Vin as shown in FIGS. 6A and 6B. Thus, the output video signal S13 is obtained in synchronization with the vertical frequency M times that of the input video signal S12.

However, as described above, the input video signal S12
7 is not synchronized with the output video signal S13.
As shown in A and B, the phase relationship between the input vertical synchronizing signal Vin and the output horizontal synchronizing signal Hout may be shifted.

Therefore, an RS flip-flop circuit 545 is provided in the timing pulse generation circuit 54 of FIG. The input vertical synchronizing signal Vin is supplied to the set terminal S of the flip-flop circuit 545, the pulse Ph from the counter 541 is supplied to the reset terminal R, and the negative output signal P545 is supplied to the reset terminal R of the vertical counter 543. Is done.

Therefore, flip-flop circuit 545
7A and 7C, the negative output signal P545 falls by the input vertical synchronizing signal Vin and rises by the output horizontal synchronizing signal Hout, and the rising of the negative output signal P545 resets the vertical counter 543. That would be. As a result, the vertical counter 54
3 is reset by the first output horizontal synchronizing signal Hout after the input vertical synchronizing signal Vin is obtained, so that the output vertical synchronizing signal Vin is obtained as shown in FIG. 7D. After the first output horizontal synchronization signal H
It will be synchronized with out.

At this time, as is clear from FIG. 7, the phase of the output vertical synchronizing signal Vout changes by a maximum of one horizontal period, but the vertical deflection circuit 24 is generally configured as shown in FIG. Therefore, there is no problem even if the phase of the output vertical synchronization signal Vout slightly changes.

That is, in the vertical deflection circuit 24 shown in FIG. 8, the output vertical synchronizing signal Vout is supplied to the sawtooth wave signal forming circuit 241 to form a sawtooth wave voltage synchronized with the signal Vout. The voltage is amplified by the vertical output amplifier 242 and then supplied to the vertical deflection coil 25. At this time, a negative feedback is applied to the amplifier 242, and a pump-up circuit 243 is connected to correct the linearity of the vertical deflection current supplied to the vertical deflection coil 25.

At this time, if a margin is provided for the time constant of the negative feedback loop, there is no problem even if the phase of the output vertical synchronization signal Vout changes by about one horizontal period. In particular, when the saw-tooth wave signal forming circuit 241 is a direct-current type (DC clamp type), the starting point of vertical scanning, that is, the scanning starting point at the top of the screen is fixed, so that the vertical direction of the display screen is fixed. There is no jitter.

Thus, according to the above-described display device and synchronous frequency conversion circuit, for a plurality of sets of synchronous frequencies,
The horizontal deflection frequency can be set to a constant value fhdef0. Therefore, for a plurality of sets of synchronization frequencies, CRT
Since the horizontal deflection frequency at 17 is constant, the horizontal deflection circuit 22 only needs to synchronize with the constant frequency fhdef0, and the synchronization performance such as the jitter performance is improved.

Further, even if the horizontal synchronizing frequency of the input video signal S11 changes during use, the frequency of the horizontal drive pulse does not suddenly change, so that there is no need to take measures against destruction of the change in the frequency.

Further, even if the horizontal synchronization frequency of the input video signal S11 changes, the horizontal deflection frequency fhdef0 does not change, so that there is no need to control the power supply of the horizontal deflection circuit 22. Further, there is no need to switch the horizontal S-shaped correction capacitor according to the horizontal deflection frequency fhdef0, and it is not necessary to use an FET having a high withstand voltage for the switching.

Further, since the tracking adjustment for the frequency characteristic of the horizontal deflection circuit 22 is not required, the circuit and system can be simplified. Furthermore, the response when controlling the main deflection and the high voltage changes depending on the horizontal deflection frequency. However, since the horizontal deflection frequency fhdef0 is constant, the design parameters can be easily set and there is no need to switch the parameters.

Further, since no interpolation or thinning is performed on the input video signal S11, the display quality does not deteriorate when displaying text characters, graphics, and the like. Further, since a product-sum calculator required for the interpolation processing is not required, the degree of integration of the LSI can be reduced. Further, since it is not necessary to operate the product-sum operation unit at a very high operating frequency, it is not necessary to cope with such a frequency.

The output vertical synchronizing frequency (vertical deflection frequency fvdef0) is set to an integral multiple (M times) of the frequency of the input vertical synchronizing signal Vin, and their vertical synchronizing is synchronized. Even if the moving image moves at a uniform speed, the moving image moves at a uniform speed on the screen of the output video signal and does not move unnaturally.

Furthermore, if the output vertical synchronizing signal Vout is merely synchronized with the input vertical synchronizing signal Vin, it can be realized by a PLL. In that case, however, it is practical in terms of the time constant of the transient response and jitter. is not. That point,
In the timing pulse generating circuit 54 of FIG. 3, since the phase of the output vertical synchronizing signal Vout is regulated based on the input vertical synchronizing signal Vin for each input vertical synchronizing signal Vin, an appropriate output vertical synchronizing signal Vout can be obtained. .

Further, since the phase relationship between the horizontal synchronization and the vertical synchronization in the output video signal can be regulated, the jitter in the vertical direction can be eliminated, and the quality of the display screen can be improved from this point as well. .

In the above description, the input video signal S11
Is a general analog signal, for example, TDM
In the case of the S format or the LVDS format, the signal may be decoded into a general digital video signal in the interface circuit 13 or the like and then supplied to the frame memory 43.

Further, as described above, since the frequency division ratio N obtained by the equation (4) is a value obtained by converting the frequency division ratio N obtained by the equation (3) into an integer, the horizontal deflection frequency fhdef0 becomes an integer. However, in this case, the reference signal S
By changing the frequency fref of 64, the change of the horizontal deflection frequency fhdef0 can be minimized.

Further, the timing control circuit 53 is
In this case, the CRT 17 can also be used as a DSP for forming a distortion correction signal.

When the horizontal deflection frequency fhdef0 is set so that the flicker on the CRT is not noticeable when the number of lines nvscn is the largest in the input video signal, the horizontal deflection frequency fhdef0 may be too high. The horizontal deflection frequency fhdef0 can be switched to several values, and the number n of lines of the input video signal
The value of the horizontal deflection frequency fhdef0 may be switched according to vscn.

Further, in the above description, the counter 541
Is a presettable up counter, and when the count value reaches a preset value, the output terminal Q becomes “H”.
Level, but actually, the counter 541 is
It can be constituted by a presettable down counter and a decoder for detecting when the count value becomes "0". And this is the counter 54
The same applies to 3, 546.

In other words, the horizontal and vertical deflection frequencies of the CRT are fixed to a single frequency and the input video signal is subjected to interpolation processing and thinning-out processing. The present invention can be applied to a case where an output video signal is obtained.

[List of abbreviations used in this specification] A / D: Analog to Digital CRT: Cathode Ray Tube D / A: Digital to Analog DC: Direct Current DSP: Digital Signal Processor FET: Field Effect Transistor LSI : Large Scale integration LVDS: Low Voltage Differential Signal NTSC: National Television System Committee PLL: Phase Locked Loop TDMS: Transition Minimized Differrential Signa
l VCO: Voltage Controlled Oscillator

[0104]

According to the present invention, the horizontal deflection frequency can be set to a constant value for a plurality of sets of synchronization frequencies. Therefore, the horizontal deflection circuit need only be synchronized with the fixed frequency, and the synchronization performance such as the jitter performance is improved. Furthermore, even if the horizontal synchronization frequency of the input video signal changes during use, the frequency of the horizontal drive pulse does not suddenly change, so that no destructive measures against the change in the frequency are required.

Also, even if the horizontal synchronizing frequency of the input video signal changes, the horizontal deflection frequency does not change, so that it is not necessary to control the power supply of the horizontal deflection circuit. Further, there is no need to switch the horizontal S-shaped correction capacitor according to the horizontal deflection frequency, and the FE with a high withstand voltage for the switching is not required.
T is also unnecessary.

Further, since it is not necessary to perform tracking adjustment for the frequency characteristics of the horizontal deflection circuit, the circuit and system can be simplified. Furthermore, the response when controlling the main deflection and high pressure changes depending on the horizontal deflection frequency,
Since the horizontal deflection frequency is constant, the design parameters can be easily set, and there is no need to switch the parameters.

Further, since no interpolation or thinning is performed on the input video signal, when text characters, graphics, and the like are displayed, the display quality does not deteriorate. Further, since a product-sum calculator required for the interpolation processing is not required, the degree of integration of the LSI can be reduced. Further, since it is not necessary to operate the product-sum operation unit at a very high operating frequency, it is not necessary to cope with such a frequency.

Further, even if the moving image moves at a uniform speed in the screen of the input video signal, it may move at a uniform speed in the screen of the output video signal and move unnaturally. Absent.

[Brief description of the drawings]

FIG. 1 is a system diagram illustrating one embodiment of the present invention.

FIG. 2 is a system diagram illustrating one embodiment of the present invention.

FIG. 3 is a system diagram showing an embodiment of a main part of the present invention.

FIG. 4 is a timing chart for explaining the present invention.

FIG. 5 is a diagram for explaining the present invention.

FIG. 6 is a waveform chart for explaining the present invention.

FIG. 7 is a waveform chart for explaining the present invention.

FIG. 8 is a connection diagram for explaining the present invention.

[Explanation of symbols]

11 and 12: input terminal, 13: interface circuit, 14: synchronous frequency conversion circuit, 15: video control circuit, 16: video drive circuit, 17: color CRT, 21
... horizontal deflection circuit, 22 ... horizontal deflection coil, 23 ... high voltage generation circuit, 24 ... vertical deflection circuit, 25 ... vertical deflection coil,
42 ... A / D converter circuit, 43 ... Frame memory,
44: D / A converter circuit, 51: PLL, 52: signal discrimination circuit, 53: timing control circuit, 54: timing pulse generation circuit, 55: memory controller, 56
... PLL, 61 ... VCO, 62 ... variable frequency dividing circuit, 63 ...
Phase comparator circuit, 64 forming circuit, 65 loop filter, 541 horizontal counter, 542 horizontal synchronizing signal forming circuit, 543 vertical counter, 544 vertical synchronizing signal forming circuit, 545 RS flip-flop circuit, 546
counter

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5C025 BA05 BA25 BA27 BA30 DA10 5C068 AA01 AA17 LA02 LA03 LA05 MA05 5C082 AA01 AA02 BB15 BC19 BD01 CA81 CB01 DA54 DA55 DA76 MM07 MM10

Claims (6)

[Claims] A first forming circuit for forming a write control signal which changes in synchronization with horizontal and vertical synchronization signals of an input video signal; a memory in which the input video signal is written by the write control signal; A discriminating circuit for discriminating the horizontal and vertical synchronizing frequencies of the input video signal; and reading control of substantially constant horizontal and vertical synchronizing frequencies regardless of the horizontal and vertical synchronizing frequencies of the input video signal according to the discrimination result of the discriminating circuit. A second forming circuit for forming a signal; and a circuit for regulating vertical synchronization of the read control signal for each vertical synchronizing signal of the input video signal when the second forming circuit forms the read control signal. The video signal written in the memory is read from the memory by the read control signal, and the read video signal is read. Conversion circuit synchronizing frequency so as to force the video signal. 2. A first forming circuit for forming a write control signal which changes in synchronization with horizontal and vertical synchronization signals of an input video signal; a memory in which the input video signal is written by the write control signal; A discriminating circuit for discriminating the horizontal and vertical synchronizing frequencies of the input video signal; and, according to the discrimination result of the discriminating circuit, a substantially constant horizontal synchronizing frequency regardless of the horizontal synchronizing frequency of the input video signal; A second forming circuit for forming a read control signal having a vertical synchronizing frequency that is an integral multiple of the vertical synchronizing frequency of the signal; and a vertical synchronizing signal for the input video signal when the second forming circuit forms the read control signal. A circuit for regulating the vertical synchronization of the read control signal for each of the read control signals. It reads the video signal, conversion circuit of the synchronization frequency set as the output video signal a video signal thus read out. 3. The synchronization frequency conversion circuit according to claim 2, wherein the vertical synchronization frequency of the output video signal is set by setting a length of a vertical blanking period of the output video signal to a predetermined value. A synchronization frequency conversion circuit which is an integral multiple of the vertical synchronization frequency of the input video signal. 4. The synchronizing frequency conversion circuit according to claim 1, wherein said output video signal is obtained at a time point when a first horizontal synchronizing signal of said output video signal is obtained after a vertical synchronizing signal of said video signal is obtained. A synchronization frequency conversion circuit for controlling the phase of the vertical synchronization signal so that the vertical synchronization signal is positioned. 5. The synchronous frequency conversion circuit according to claim 1, wherein the number of dots per line of the video signal read from the memory is equal to the number of dots per line of the input video signal. A synchronous frequency conversion circuit adapted to change the frequency of the read signal. 6. The synchronizing frequency conversion circuit according to claim 1, wherein the output video signal is supplied to a CRT, and the sawtooth signal forming circuit in the vertical deflection circuit of the CRT is a DC direct connection type. Synchronization frequency conversion circuit.