KR20060047515A - Sequence adaptive synchronization signal generator - Google Patents

Abstract

According to a predetermined output timing standard, a method and apparatus are provided for generating a synchronization signal based on a received synchronization signal. A timing deviation of the received synchronization signal is detected from a predefined input timing standard, and based on the detected deviation, the timing of the generated synchronization signal is adjusted.

Description

Synchronization signal generator, video conversion circuit, synchronization signal generation method and video conversion method {SEQUENCE ADAPTIVE SYNCHRONIZATION SIGNAL GENERATOR}

1A is a diagram illustrating a video conversion scheme of a 50 Hz accompanying video signal into a 100 Hz engaged video signal;

FIG. 1B is a diagram illustrating a video conversion scheme of a 50 Hz parallel video signal into a 75 Hz progressive video signal; FIG.

1C is a diagram illustrating a video conversion method of a 50 Hz parallel video signal into a 60 Hz progressive video signal;

2 is a schematic diagram of a conventional video conversion circuit,

3 is a diagram illustrating a conventional synchronization signal generation scheme, wherein a synchronization signal for a 75 Hz forward video signal is generated from a synchronization signal of a received 50 Hz perforated video signal;

4A illustrates an error in timing of a video signal due to source switching;

4B is a diagram illustrating timing deviation of a video signal typically generated by a consumer grade VCR in playback seeking mode;

5 illustrates the operation of a conventional video conversion technique provided with a video signal of non-standard timing;

6 is a schematic diagram of a synchronization signal generator according to the present invention;

7 illustrates an exemplary configuration of a synchronization signal generator whose deviation is detected by a pixel counter, in accordance with the present invention;

8 is a schematic diagram of a video conversion circuit using the synchronization signal generation scheme of the present invention;

9 is a diagram illustrating a synchronization signal generation scheme according to the present invention, illustrating a case in which a received video sequence is shorter than a standard video sequence;

FIG. 10 is a diagram illustrating a synchronization signal generation scheme of the present invention, in which a received video sequence is longer than a standard video sequence. FIG.

FIG. 11 is a diagram illustrating another synchronization signal generation scheme of the present invention, in which a deviation in a sequence of received video images is introduced into a sequence of simultaneously generated synchronization signals;

12 is a diagram illustrating a synchronization signal generating method according to the present invention;

13 illustrates an exemplary implementation of deviation detection in an input synchronization signal, in accordance with the present invention;

14 illustrates an exemplary implementation of timing adjustment of a generated synchronization signal in accordance with the present invention.

Explanation of symbols for the main parts of the drawings

610: deviation detector 620: timing adjustment circuit

630: timing reference means 640: signal generator

The present invention relates to the adaptive generation of synchronization signals.

In particular, the present invention relates to the generation of synchronization signals used in temporal frame rate converters and picture improvement circuits in television and multimedia display applications.

Temporal frame rate conversion has become an important problem in modern television sets. In particular, cathode ray tube (CRT) television sets sometimes convert a video signal from a 50 Hz original field rate of a PAL or SECAM video signal or a 60 Hz field rate of an NTSC video signal to a higher frame rate, thereby producing an area flicker effect. circuitry to reduce flicker effects. The received video signal at 50 Hz is converted to temporal frame rates such as 60 Hz, 75 Hz and 100 Hz. The 60 Hz input video signal can be up-converted to frequencies such as 72 Hz, 80 Hz and 120 Hz.

Typically, temporal frame rate conversion is performed by a digital signal processing chipset that can further perform image size scaling and de-interlacing of received interlaced video images. For example, a standard PAL video signal may be converted to a frame of 1500 * 810 pixels at a frame rate of 75 Hz.

Temporal frame rate conversion requires the generation of an intermediate image that reflects the video content at a different temporal position than the input video sequence. The temporal relationship between the received video image and the image of the upconverted video signal is shown in FIGS. 1A, 1B and 1C for a received video signal having a field rate of 50 Hz, such as a video signal according to the PAL standard.

As shown in FIG. 1A, the conversion of the 50 Hz signal to the 100 Hz perturbation video signal may be performed by repeating each received field. As is well known, more sophisticated techniques are also known in the art. 1B shows the conversion to a 75 Hz progressive video signal. In this case, the subsequent input field pairs are converted into a converted video signal of three frames. Finally, FIG. 1C shows the conversion between a perturbation 50 Hz video signal and a progressive 60 Hz video signal. As can be seen from the figure, the time period of 10 fields of the input video signal corresponds to the time period of 12 fields of the converted video signal.

In addition to generating the image content of the converted video signal, in order to control the provision of the converted video signal on the display, a new video time base of the vertical and horizontal synchronization signals must be generated.

A conventional technique for generating a synchronization signal for the converted video signal is shown in FIG. Typically, the conversion frequency ratio between the original video signal and the converted video signal corresponds to an integer ratio. Thus, some synchronization signals of the original video signal and the converted video signal can be matched in time. Conventional video conversion circuitry exploits this relationship by triggering the generation of a particular synchronization signal of the converted video signal 311, 331 with each synchronization signal 310, 330 to the original video signal.

In the example shown in FIG. 3 regarding the conversion of a perturbing 50 Hz signal to a progressive 75 Hz signal, the second every second vertical synchronization signal 310, 330 of the original video signal is a third every third synchronization signal of the converted video signal. (311, 331). These vertical synchronization signals 311 and 331 are generated when the corresponding vertical synchronization signals 310 and 330 of the original video signal are received. Based on the time raster set by the triggered synchronization signals 311, 331, the intermediate synchronization signals 312, 313, 332 are generated by the operation of the timer.

So far, only the generation of the vertical synchronization signal has been described. In the same way, the horizontal synchronization signal can be generated by triggering the generation of the horizontal synchronization signal based on the respective horizontal synchronization of the original video signal. The timer supplements the horizontal synchronization signal that does not match the synchronization of the original video signal and the timing of the signal. Alternatively, the horizontal synchronization signal may be generated based only on the timer operation in the time raster of the triggered vertical synchronization signals 311 and 331.

FIG. 2 illustrates a circuit structure of a conventional upconversion circuit capable of performing generation of a synchronization signal as described above with reference to FIG. 3. In the circuit shown, upconversion from 50 Hz to 100 Hz is performed. For a similar video conversion circuit, it is described in application note AN10233 entitled "Scan conversion using the SAA4998 (FALCONIC EM)" available from Philips Semiconductors.

As shown in FIG. 2, the received video signal 201 is subjected to digital acquisition by the video input circuit 210 and stored in the memory 220. Its horizontal synchronization signal 202 is provided to the PLL stage 240 to generate an output pixel clock 205. The output pixel clock 205 is divided into two in the frequency dividing circuit 250 to obtain an acquisition pixel clock 206. The converted video output 230 generates a video image of the up-converted video signal 231 by accessing the memory 220 and further generates a synchronization signal for the converted video signal. These synchronization signals can be generated in the manner described above by triggering certain of the synchronization signals generated based on the input synchronization signal 202. In addition, an intermediate synchronization signal is generated based on the output pixel clock signal 205.

A disadvantage of the conventional approach of generating the synchronization signal is that an error in the timing of the synchronization signal of the original video signal is not controlled in the timing of the generated synchronization signal relative to the output timing standard and sometimes results in significant errors. 4A and 4B show two possible causes of the deviation of the received synchronization signal from each input timing standard. 5 shows the response of a conventional synchronization signal generator to timing errors of a received synchronization signal.

4A illustrates the switching of a video source that may occur, for example, in a digital receiver. At a time point T0, the video signal is switched from the first source 1A, 1B, 2A, to the second source 1B ', 2A', 2B ',. In the resulting video image sequence, field 1B is generated that is shorter than the standard field by time Δt1. In other cases, fields longer than the standard fields may appear. 4B shows a timing error known from the video signal of a standard consumer grade video tape recorder (VCR) in search playback mode. At irregular intervals, a certain number of lines fall out of the field as compared to the standard field. In the case shown, field 1B is shorter than the standard field by the interval Δt2. Moreover, non-standard video signals can be generated from entertainment devices such as video game consoles.

When such a non-standard video sequence is supplied to the video conversion circuit, a continuous synchronization signal substantially deviating from the preset output timing standard can be generated, as shown in FIG. Here, field 1B of the input video signal is shorter than the standard field by a deviation Δt3. The operation of a conventional conversion circuit is shown for conversion from a 50 Hz perforation to a 100 Hz perforated video signal. Applying the conventional synchronization signal generation technique to this example, the second vertical synchronization signal is generated by using the vertical synchronization signal of the input video signal as a trigger.

Thus, upon transition from input field 1B to the next input field 2A, the vertical synchronization signal indicating the start of input field 2A triggers the vertical synchronization signal indicating the transition from the generated field 'd' to 'e'. As can be seen from FIG. 5, the synchronization signal generated for field 'd' is substantially deviated by the amount of DELTA t4 from the preset output timing standard.

As shown in Fig. 2, on the basis of the pixel clock signal generated from the input synchronization signal by the PLL circuit, the next generated field 'e' will be provided with a synchronization signal of a higher frequency than the standard timing. Thus, field 'e' will be shortened by the time [Delta] t5 than the standard field. For the generation of the synchronization signal for the next field 'f', the circuit will wait until each trigger reception from the input synchronization signal, so that the field 'f' is longer by the period [Delta] t6 than the standard field.

Cathode ray tube displays typically follow such deviations and display at least distorted images, but modern digital displays, such as LCDs and plasma flat panel displays, do not accept video signals that deviate substantially from predetermined timing standards according to device specifications. . On such a digital display, the screen turns blank until the generated video signal resumes standard timing. Thus, the conventional technique of generating a synchronization signal for the converted video signal performs unsatisfactorily for the digital display because it creates a blank screen during source switching or video scene searching in a consumer grade VCR. Because.

The error described is particularly annoying when the conversion from the 50 Hz video signal to the 60 Hz forward video signal is performed. This type of conversion becomes more important because a digital frame frequency of 60 Hz is set as the display standard for digital displays such as plasma flat panels and LCD displays. As shown in FIG. 1C, at this conversion ratio, the time period between the coincidence of the vertical synchronization signals of the input video signal and the output video signal corresponds to the length of 10 input fields and 12 output fields. When the timing deviation of the input synchronization signal occurs at the beginning of such a sequence, a rather long time passes until the next output synchronization signal is triggered. Thus, the timing error will be apparent for a long time in the converted video signal.

There is a way to generate the output pixel clock and the input pixel clock by separate PLL circuits, where the PLL circuit for the output pixel clock can achieve a slow response rate, as described, for example, in the Philips application note above. Have Thus, a more stable output pixel clock is generated. A similar approach is to generate the output pixel clock by a stable internal crystal oscillator. However, neither of these approaches can prevent the generation of a synchronization signal that, in response to a timing error of the original video signal, uncontrolled substantially deviates from the output timing standard of the converted video signal.

Another alternative of the video conversion method is described in EP-0 775 421 B, where the video conversion circuit is operated according to a stable reference synchronization signal. The reference synchronization signal corresponds to the temporal frame rate of the converted video signal. The video conversion circuit evaluates the phase difference between the reference synchronization signal and the synchronization signal of the received video signal to determine the interpolation ratio of the original image to be applied to the generation of the interpolated image.

The disadvantage of this approach is that somewhat complex processing is required to determine the current phase in real time. Moreover, this approach leads to high computational and hardware behavior.

In view of the above deficiencies of the conventional conversion scheme, it is an object of the present invention to provide an improved way of generating a synchronization signal based on the received synchronization signal.

This object is achieved by the features of claim 1 for a synchronization signal generator and claim 24 for a method of generating a synchronization signal.

According to a first aspect of the invention, a synchronization signal generator is provided for generating a synchronization signal, based on a received synchronization signal, in accordance with a predefined output timing standard. The synchronization signal generator includes detection means for detecting a deviation of the timing of the received synchronization signal from a predefined input timing standard and a timing adjustment circuit for adjusting the timing of the generated synchronization signal based on the deviation detected by the detection means. do. In particular, the synchronization signal generator of the present invention is provided for the generation of horizontal and vertical video synchronization signals.

According to another aspect of the present invention, a method of generating a synchronization signal generates a synchronization signal based on a received synchronization signal according to a predefined output timing standard. According to this method, the deviation of the timing of the received synchronization signal from the predefined output timing standard is detected, and based on the deviation detected in the detection step, the timing of the generated synchronization signal is adjusted. In particular, the synchronization signal generation method of the present invention is provided for generation of horizontal and vertical video synchronization signals.

A special solution of the invention is to detect the deviation of the received synchronization signal. Based on the detection result, the timing of the generated synchronization signal is adjusted to reflect only a slight change from the output timing standard, thereby reflecting the detected timing error. In this way, the generated synchronization signal can always be inherently controlled in reliance upon the output timing standard and the deviation of the generated synchronization signal from the output timing standard. Thus, the generated synchronization signal reliably drives the digital display device while allowing only a slight deviation of the input video signal from the specified standard. Such display applications include LCDs and plasma flat panel displays. The synchronization signal generation scheme of the present invention is preferably used in a video conversion circuit for performing temporal frame rate conversion between a 50 Hz perforation and a 60 Hz forward video signal.

According to a preferred embodiment, by counting the first pixel clock signal such that the time period between the received synchronization signals is measured in units of pixel clock counts, detection of the deviation of the received synchronization signal from a predefined input timing is performed. By using the count value of the pixel clock, efficient quantitative detection of the deviation between the received synchronization signal and the input timing standard is achieved.

Preferably, the number of pixels is counted for a period of a predefined number of subsequent input images. In particular, pixels may be counted for 1, 2 or 10 subsequent input fields.

According to another embodiment, the number of subsequent input images to be counted is preset such that the period of the number of subsequent input images according to the input timing standard corresponds to the period of integers of the subsequent output image according to the output timing standard. Thus, the image sequence of the input image and the corresponding output image are predefined, where a matching vertical synchronization signal determines the start of each sequence. This makes it possible to particularly efficiently determine the timing adjustment of the generated synchronization signal.

According to another embodiment, the timing of the generated synchronization signal of the current output image is adjusted. According to this, the deviation in the received synchronization signal is immediately introduced into the generated synchronization signal.

According to a preferred embodiment, the timing of the generated synchronization signal is adjusted for a sequence of output images, where the number of images in the sequence corresponds to a period of the sequence according to the output timing standard corresponding to a predetermined number of periods of subsequent input images. Is preset. Accordingly, the synchronization signal generation scheme of the present invention is performed based on the image sequence, which includes the time interval between two matching vertical synchronization signals of the received and generated synchronization signals. In this way, the operation of detecting the deviation and making each adjustment is simplified.

According to another preferred embodiment, the number of generated horizontal synchronization signals of the last image of the sequence of output images is adjusted in response to the number of counted pixels different from the input timing standard. Thus, the current sequence of output synchronization signals maintains a standard timing raster until the last frame of the output sequence.

According to another preferred embodiment, by adjusting the number of generated horizontal synchronization signals in all the images of the sequence of output images, the detected deviation is distributed in the sequence of output images. Thus, the deviation is distributed such that only a small change between the generated synchronization signal and the origin timing standard occurs. In particular, the generated synchronization signal is easily maintained within the timing specification of the digital display device, allowing for an improved viewing experience when displaying the converted video signal.

Preferably, in addition to distributing the deviation by adjusting the number of generated horizontal synchronization signals of all the images of the sequence, the remaining time by adjusting the time interval between successively generated horizontal synchronization signals for all lines of the sequence of output images. The deviation is distributed. Thus, to avoid rejection of the generated signal by the digital display device, the detected deviation can be distributed in a more sophisticated manner.

Preferably, the detected deviation for a predetermined number of input images is fully introduced into the current or subsequent sequence of output images. Thus, a slight deviation of the output synchronization signal from a predetermined output timing standard occurs only within a limited time interval corresponding at most to one sequence. Moreover, as the next sequence begins, all deviations are taken into account, allowing the generation of the standard synchronization signal to resume.

According to another preferred embodiment, in addition to timing adjustment of the output synchronization signal, a sequence position signal is generated that indicates the current image position relative to the sequence of output images. Such sequence position signals efficiently control the conversion process. In particular, the conversion process using a predetermined interpolation ratio between the currently generated image and the one or the plurality of received images can be efficiently controlled.

Preferably, the temporal position of the generated synchronization signal is determined by a process of performing timing adjustment in accordance with the second pixel clock signal. Thus, the timing of the generated synchronization signal is reliably determined based on the independent pixel clock.

According to another preferred embodiment, to control the generation of the synchronization signal, the number of lines per field or frame is determined.

Preferably, in order to control synchronization signal generation, the number of pixels per line is determined.

According to another preferred embodiment, the synchronization signal generation scheme of the present invention selects an adjustment operation from the following three predefined operations, wherein the three operations are as follows. (1) By adjusting the number of lines, the detected deviation is introduced into the last image of the sequence of output images. The remaining pixels are added to the last line. (2) By adjusting the number of lines of all the images of the sequence, the detected deviation is distributed between all the images of the sequence with respect to the output image, and the remaining pixels are added to the last line of the last image. (3) By adjusting the number of lines of all images, the detected deviation is distributed among all images of the sequence of output images, and the remaining pixels are distributed among all lines of all images. The remaining pixels are added to the last line of the last image. Therefore, it is possible to select the adjustment operation that appears most appropriately to the detected deviation.

Preferably, the adjustment operation is selected based on the magnitude and direction of the deviation. These two values provide an easily and efficiently accessible criterion for performing the selection of the adjustment action.

According to another preferred embodiment of the present invention, the adjustment operation is selected such that the deviation between the timing of the generated synchronization signal and the output timing standard does not exceed the predefined deviation range. Thus, the individual deviation of the generated synchronization signal due to the adjustment operation can be maintained within a predefined interval, so that the generated signal is guaranteed, for example, in accordance with the preset device specifications of the LCD display.

According to another preferred embodiment, in order to select an adjustment operation, the type and temporal position of the received synchronization signal are evaluated. Thus, the type of signal error can be detected, allowing for a distinction between VCR and source switching in, for example, a seek mode. Accordingly, the adjustment operation can be selected.

Preferably, the video conversion circuit for causing the video signal to be temporally frame rate converted comprises a synchronization signal generator according to the invention.

Another embodiment is the subject of the dependent claims.

These and other objects and features of the present invention will become apparent from the following description provided in conjunction with the accompanying drawings.

The present invention relates to the generation of a synchronization signal based on a received synchronization signal, wherein a deviation in the timing of the received synchronization signal relative to the input timing standard is detected. The detected deviation is introduced into the timing of the generated synchronization signal by adjusting the timing of the generated synchronization signal so that it changes only slightly from the output timing standard.

6 shows a synchronization signal generator for implementing the described synchronization signal generation scheme. The deviation detector 610 receives the synchronization signal 601 and compares the timing of the received synchronization signal with an input timing standard. The input timing standard is provided by the timing reference means 630. The timing reference means may comprise, for example, a table representing standard time period characteristics for the input timing standard. When a deviation occurs between the input synchronization signal 601 and the input timing standard, the deviation detector 610 detects the deviation and signals the deviation to the timing adjustment circuit 620. According to the output timing standard, the timing adjustment circuit 620 adjusts the timing of the generated synchronization signal 602. According to the adjusted timing, the signal generator stage 640 generates the synchronization signal 602. Similar to the input timing standard, the timing reference means 630 provides an output timing standard.

By providing the deviation detector 610, the present invention recognizes whether the received synchronization signal follows the input timing standard. In contrast, the conventional approach does not compare the input synchronization signal with the standard timing, which causes the generation of the synchronization signal to deviate significantly from the output timing standard.

According to the present invention, the timing of the generated synchronization signal is adjusted to deviate from the output timing standard in a deterministic manner so that the deviation is reliably controlled. Thus, the generated synchronization signal always follows the output timing standard inherently and maintains a continuous frame raster. Thus, the generated synchronization signal reliably drives the digital display device while allowing only a slight deviation of the input video signal from the specified standard.

The synchronization signal generator of the present invention is effectively used for generating synchronization signals of video signals that have undergone temporal frame rate changes. In particular, in applications requiring up-conversion from a 50 Hz perforated video signal to a 60 Hz forward video signal, the present invention generates a synchronization signal of improved timing quality.

In addition, the present invention is preferably used in applications where the synchronization signal of the video signal is restored, by receiving a distorted synchronization signal possibly from a video source and generating a new synchronization signal at the same temporal frame rate.

The synchronization signal generator of the present invention may receive a synchronization signal according to the PAL, SECAM or NTSC video standard, among others.

The generated synchronization signal may be associated with a high definition television standard such as HDTV. Image rates corresponding to the generated synchronization signal include a 60 Hz traveling video signal, a 75 Hz traveling, a 100 Hz traveling and a 120 Hz traveling video signal.

In the following, both fields and frames of the video signal will be represented as video images.

Referring now to FIG. 7, an exemplary configuration of a synchronization signal generator of the present invention is described in more detail. The received synchronization signal is provided to a deviation detector 710, which counts the clock signal of the first pixel clock 750 to detect a deviation between the timing of the received synchronization signal and the input timing standard. .

The pixel clock generator 750 may be implemented as a crystal oscillator stage. The counter 715 of the deviation detector 710 is reset and restarted after receiving a particular synchronization signal. When the counter 715 is reset, the count value is evaluated. Thus, the time period between specific synchronization signals is measured in units of pixel clock counts. The pixel clock count value corresponding to the measured time period is compared with the expected value corresponding to the time period determined by the input timing standard.

In a particular implementation, the counter 715 counts the pixel clock signal for a period corresponding to a predefined number of subsequent input images with which the received synchronization signal is associated. In this case, the reset condition of the counter includes a synchronization signal representing the new video image, causing the counter to count the pixel clock signal for the integer of the subsequent input image.

The deviation detector 710 provides the deviation signal 711 to the timing adjustment circuit 720. The deviation signal includes the direction of the deviation, which indicates whether a small or exceeding pixel has been counted compared to the expected count value according to the input timing standard. The deviation signal further includes a difference between the expected pixel count value and the measured pixel count value.

According to this deviation signal, the timing adjustment circuit 720 adjusts the timing of the generated synchronization signal. For this purpose, the timing adjustment circuit signals the temporal position of the synchronization signal to the synchronization signal generator 740, which generates the actual signal waveform of each synchronization signal.

The timing adjustment circuit 720 is operated based on the clock reference from the second pixel clock 760 which is preferably related to the pixel clock of the output image of the video conversion circuit. The second pixel clock is generated by the crystal oscillator. The second pixel clock signal may be obtained, for example, from the display driving stage of the temporal frame rate converter.

9, 10 and 11 show an example of the timing adjustment process of the present invention performed by the synchronization signal generator shown in any of Figs. 6 or 7. In these specific examples, a temporal frame rate conversion from a 50 Hz perforated video signal to a 75 Hz progressive video signal was chosen. However, the illustrated mode of operation can apply to any other temporal frame rate conversion ratio.

In general, in the following, received and generated synchronization signals are described in terms of images, fields, frames, lines and pixels, but it should be understood that the timing adjustment of the present invention relates only to the adjustment of the number and the temporal position of the synchronization signals. Terms such as image, field, frame, line, pixel, etc. are used to aid in understanding the adjustment operation and should always be understood as a reference to the corresponding synchronization signal. The timing adjustment does not need to take into account the video image content generated in the conversion process in which the synchronization signal generation method of the present invention can be used. In particular, generation of video image content including errors due to non-standard input video images may be allowed.

All illustrated examples essentially detect timing deviations of the received synchronization signal based on the sequence of input images, and perform timing adjustments of the generated synchronization signal based on the sequence of output images. Each sequence of a plurality of consecutive input or output images is defined in such a way that the number of consecutive input images and the number of consecutive output images correspond to the same time period. The number of images is an integer. The input image corresponds to the image of the original video signal and the output image corresponds to the image of the converted video signal. Similar to the definition of an image sequence, the sequence of received synchronization signals and the sequence of generated synchronization signals correspond to the same time period. In particular, the vertical synchronization signal indicating the start of the sequence may coincide with the sequence of received synchronization signals and the sequence of generated synchronization signals.

As is apparent from the above description, the length of the sequence is predetermined by the conversion ratio. When a synchronization signal is generated for conversion from a 50 Hz traveling signal to a 60 Hz traveling signal, the input sequence corresponds to 10 subsequent fields and the output sequence includes 12 frames. In the case of a conversion from 50 Hz perforation to 75 Hz perforation, the sequence of received synchronization signals corresponds to two fields, and at the same time a synchronization signal for three output frames is generated. Those skilled in the art will readily determine the number of sequences for the different conversion ratios.

According to the timing adjustment process shown in Fig. 9, the time period t0 corresponding to the sequence of the input image is measured and evaluated. In the example shown, this time period corresponds to two input fields and three output frames. For each successive sequence, the input pixel clock is counted and a deviation from the expected count value is detected.

As shown in FIG. 9, the input sequence received in the time interval T1-T2 deviates by the deviation time Δt10 from the expected time period t0 according to the input timing standard. In this case, the first fields T1-T2 of the input image sequence are shorter than those defined by the input timing standard.

The timing adjustment of the generated synchronization signal is performed such that the generated synchronization signal of the currently generated sequence started at the same time T1 as the input sequence where the deviation is detected is exactly terminated according to the output timing standard. The next sequence of generated synchronization signals between time intervals T3 and T4 is adjusted in its timing such that the detected time deviation Δt10 is introduced into this sequence of generated synchronization signals. Therefore, the sequence of synchronization signals generated in the time interval T3-T4 has the same length t0-Δt10 as the input image sequence in which the deviation was detected. Thus, at time point T4, the beginning of the sequence of input image and output image coincide again.

For adjustment of the generated synchronization signal in the time period T3-T4, different adjustment operation options can be implemented. According to the first adjustment option, the detected deviation [Delta] t10 is applied only to the last image of the output image sequence to be adjusted. Adjustment is performed by reducing the number of lines in the last image of the output image sequence. This means that the number of horizontal synchronization signals of the last image is reduced. The remaining pixels not added to the entire line form the last line of the last image of the output sequence.

According to a second option for performing the adjustment, the detected deviation Δt10 is evenly distributed to the generated synchronization signal of the output sequence. The adjustment includes reducing the number of lines in all the images of the sequence. Also, the number of pixels per line can be reduced so that the time interval between two consecutive horizontal synchronization signals is shortened. According to the aforementioned adjustment operation option, the individual deviation of the generated synchronization signal from the output timing standard is considerably lower as in accordance with the first option described above. Thus, the second option is desirable for applications that require the output synchronization signal to deviate as little as possible from the predetermined timing standard specification. Such applications include signal generation for digital displays such as LCD screens and plasma flat panel displays.

The example of the timing adjustment operation shown in FIG. 10 differs from the adjustment process described with reference to FIG. 9 in that the received synchronization signal sequence requires a longer period of time than defined by the input timing standard. .

As shown in FIG. 10, the sequence of input images requires time t0 + Δt20 instead of the expected time t0 in time intervals T1-T3. The detected deviation [Delta] t20 is introduced into the sequence T2-T4 of the generated synchronization signal continuing after the sequence T1-T2 of the generated synchronization signal starting at the same time T1 as the sequence of the received signal deviating from the input timing standard.

In a manner similar to the operation described in FIG. 9, the detected deviation Δt20 is added to the last frame of the output image sequence according to the first adjustment option, or uniformly between frames of the output image sequence according to the second adjustment option. Is distributed. As a result, at time T4, the vertical synchronization signals starting another sequence of received and generated synchronization signals are matched again.

According to the first adjustment option, an additional horizontal synchronization signal corresponding to the line of the output image sequence is added to the last frame. Any remaining pixels can be added to form the last line. According to the second adjustment option, the deviation is distributed by adding the same number of lines to each frame of the output image sequence. In addition, the number of pixels per line can be increased so that the time interval between two consecutive horizontal synchronization signals becomes longer.

When only a small amount of deviation is detected, this deviation can be introduced into the generated synchronization signal associated with the last image of the source image sequence. However, when a larger deviation is detected, this deviation is preferably distributed over a plurality of images, so that the individual deviation of the generated synchronization signal from the output timing standard is small.

As shown in FIG. 11, for example, by detecting a deviation after each received vertical synchronization signal, a timing deviation that already exists in an input image sequence that has not yet been fully received may be detected. According to this, it is possible to adjust the timing of the sequence of generated synchronization signals starting at the same time point T1 as the sequence of received signals without waiting for the completion of the received sequence.

According to the example shown, a deviation Δt30 is generated in the first image of the received sequence T1-T2 and detected by evaluating the period of each field of the input sequence. Referring to example options 1 and 2 in FIG. 11, the detected deviation is applied to one of the images of the output image sequence following the input image where the deviation was detected. According to the third option in FIG. 11, the detected deviation is distributed among the remaining output images. As already described in the above implementation, timing adjustment is performed by adding or subtracting a line (ie, a horizontal synchronization signal), or by adjusting the number of pixels per line.

8 shows the configuration of a temporal frame rate converter for performing the generation of a synchronization signal according to the invention. Such a temporal frame rate converter may perform any of the timing adjustment operations described above.

Temporal frame rate converter 800 is provided with a buffer 870 that stores input image data and reads out image data to be supplied as a converted video signal. The acquisition of the received image data is controlled by the memory controller 880 which receives the horizontal and vertical synchronization signals 801 of the received video signal and the input pixel clock. A synchronization signal and an input pixel clock are also supplied to a clock counter 815 that counts pixel clock signals corresponding to a certain number of input images. Clock counter 815 counts the pixels for each sequence of the input image. The received synchronization signal, indicating the start of the next sequence, causes the count value to be evaluated and the counter to be reset.

The count value is provided to an arithmetic logic unit (ALU) 810 and compared with the expected count value according to the input timing standard. Depending on the detected deviation, the ALU 810 determines the adjustment of the generated synchronization signal to the sequence of output images. For this purpose, the ALU 810 calculates the temporal position at which the horizontal and vertical synchronization signals 802 will be generated and provides each signal to the synchronization signal generation circuit 840. This circuit generates the actual waveform of the synchronization signal 802 and outputs the generated synchronization signal along with the output pixel clock. The generated synchronization signal 802 and output pixel clock are also provided to the read memory controller 890 to control the generation of the converted video signal.

The ALU further provides a 'sequence start' signal and a current sequence position to control the conversion process. The sequence position represents the current image in the output image sequence. An efficient way of generating a sequence position signal is to increment the sequence position counter whenever the generated synchronization signal represents a new image, which is typically the simultaneous generation of vertical and horizontal synchronization signals. Resetting the sequence position to zero indicates the start of a new sequence of output images. The conversion process uses the sequence position to determine the image interpolation ratio between the output video image and one or a plurality of input video images. In this way, efficient control of the conversion process is achieved.

The ALU 810 internally determines the number of lines per image and the number of pixels per line of the output sequence to control the generation of horizontal and vertical synchronization signals 802.

In addition to the pixel clock count value, the ALU 810 may be provided with the received horizontal and vertical synchronization signals. Based on these signals, the ALU determines the type of deviation. By determining whether the horizontal synchronization signal and / or the vertical synchronization signal have a period according to the input timing standard, the timing error generated by the VCR in the seek mode and the error generated by the source switching can be distinguished. Thus, appropriate adjustment processing of the generated synchronization signal is selected.

12 describes a method for generating a synchronization signal based on a received synchronization signal in accordance with a predefined output timing standard. In a first step s100, a deviation between the received synchronization signal and the input timing standard is detected. In a second step s200, the timing of the generated synchronization signal is adjusted according to the detected deviation.

Thus, the described synchronization signal generation method of the present invention provides the generated synchronization signal reflecting the deviation of the received synchronization signal. However, the deviation in the received synchronization signal does not cause substantial error in the generation of the output synchronization signal. In contrast, the described method essentially generates a synchronization signal in accordance with the output timing standard, where the timing of the generated synchronization signal can be reliably controlled. In this way, the generated synchronization signal provides improved display control for applications requiring stable signal input, such as digital displays including LCD screens and plasma flat screens.

Referring now to FIG. 13, an exemplary implementation of the detection step s100 is described in more detail. According to this implementation, in the sub-step s110, the clock signal of the input pixel clock is counted. In another substep s120, when a specific synchronization signal is received, the count value is reset.

In this way, the pixel clock signal is counted for the time period between two specific synchronization signals. For example, by counting the pixel clock signal between two consecutive vertical synchronization signals, a pixel clock count is obtained for a time interval corresponding to the received field or frame. According to the operation mode described above, the time interval for the sequence of received vertical synchronization signals is counted. The number of images is predetermined according to the conversion ratio between the received synchronization signal and the generated synchronization signal.

In another substep s130, the count value for the time interval between specific synchronization signals is compared with the expected count value according to the input timing standard. In this way, the deviation between the received synchronization signal and the input timing standard is determined in units of pixel clock count values. Thus, with efficient operation, the deviation can be determined quantitatively.

In the above-described operating mode (see FIGS. 9, 10, 11), the number of pixels counted for the sequence of received synchronization signals is compared with the expected pixel clock count according to the input timing standard. The difference between the expected count value and the actual count value specifies the deviation value used to control the timing adjustment of the generated synchronization signal.

The implementation of the described deviation detection step s100 may be efficiently implemented in any kind of programmable logic circuit, such as a programmable digital signal processor or a field programmable gate array (FPGA).

Referring to FIG. 14, an example implementation of adjusting the timing of the generated synchronization signal (s200) is described. In a first substep s210, a value specifying the detected deviation is received. According to the received deviation value, in the substep s220, an adjustment method for adjusting the timing is selected.

The selection of the adjustment method is performed efficiently by considering at least the magnitude of the deviation. In addition, the direction of the detected deviation can be used as the selection criterion. The appropriate timing adjustment method is selected in such a way that the deviation between the timing of the generated synchronization signal and the output timing standard does not exceed the predefined deviation range. Thus, an improved timing quality synchronization signal is generated, which is preferably used to drive display applications that require highly stable input signals such as LCD and plasma flat panel displays.

Alternatively, the selection of the adjustment method may be performed by detecting the type of deviation. According to this alternative, the temporal position of each received horizontal and vertical synchronization signal is evaluated. Based on this evaluation, one can, for example, distinguish whether an error in the input video signal results from a consumer grade VCR in search mode or from source switching. In particular, it is possible to determine whether the input image deviates from the input timing standard in that a line of integers is missing or added in each field. It is also possible to determine whether a particular line has a larger or smaller number of pixels. In accordance with this distinction, an appropriate adjustment method is selected.

Considerations in which the adjustment method is selected will be described in describing the individual adjustment method so that the timing deviation in the generated synchronization signal is not as opposing as possible. At least one of the adjustment methods described below should be available for selection. Preferably, one can choose between any of the described adjustment methods.

According to the first adjustment method shown by step s230a, the detected deviation is introduced into the last image of the sequence of generated synchronization signals. Corresponding to the deviation value, the number of horizontal synchronization signals representing the line of the last image is increased or decreased. An excessive number of pixels are added as the last (shorter) line.

If the deviation does not exceed a certain value, this adjustment method is selected so that the detected deviation for the sequence of received images does not deviate more than the predefined deviation range from the output timing standard. May be introduced in the last image. If the deviation of the received synchronization signal results in a deviation that is greater than the predefined deviation range for the generated synchronization signal, another adjustment method is selected.

According to the second adjustment method shown in step s230b, the detected deviation is distributed among all the images of the sequence of output synchronization signals. The number of lines of all images in the output sequence is adjusted to distribute the deviation so that all fields / frames have the same number of lines. The remaining pixels form the last line of the last field. This line may be shorter than the standard line.

According to this method, a larger deviation can be distributed between a plurality of images of the sequence of generated synchronization signals. Moreover, the deviation of the generated synchronization signal from the output timing standard can be kept within a predetermined deviation range. This method of adjustment is particularly desirable for handling errors in the received synchronization signal where a line of integers falls out of the input field, such as caused by the VCR in search mode. Depending on the number of lines that fall out of the received sequence of synchronization signals, the number of lines in the generated synchronization signal is adjusted, resulting in the least inverse deviation of the generated synchronization signal from the output timing standard.

If the detected deviation is such a magnitude that the deviation of the individual generated synchronization signal is greater than the timing adjustment according to the second adjustment method is greater than the preset deviation range, the third adjustment method is selected.

According to this method shown in step s230c, the detected deviation is distributed among all the images of the sequence of synchronization signals generated. By adjusting the number of generated horizontal synchronization signals corresponding to the lines in all the images of the output sequence, the detected deviation is distributed, and the number of pixels per line is adjusted to distribute the remaining pixels. The remaining pixels, which may not be evenly distributed between all the lines of the output sequence, form the last line of the last field.

According to this method, larger deviations can be distributed between the output fields / frames without the generated synchronization signal being more than a predetermined deviation range from the output timing standard. This deviation range may include an interval specifying the number of lines per field / frame and an interval specifying the number of pixels per line. Thus, a large amount of deviation can be distributed between the generated synchronization signals, while complying with the predetermined deviation limit.

The implementation of the timing adjustment step s200 described may be efficiently implemented in any kind of programmable logic circuit, such as a programmable digital signal processor or an FPGA.

In summary, the present invention provides a synchronization signal generation scheme for generating a synchronization signal based on a received synchronization signal according to a predefined output timing standard. A deviation of the timing of the received synchronization signal from a predefined input timing standard is detected, and based on the detected deviation, the timing of the generated synchronization signal is adjusted.

Thus, a deviation in the timing of the received synchronization signal is introduced into the generated synchronization signal in such a way that the generated synchronization signal always follows the output timing standard, and the deviation of the generated synchronization signal from the output timing standard is assured. Can be controlled. Thus, the generated synchronization signal reliably drives the digital display device while allowing only a slight deviation of the input video signal from the specified standard. Such display applications include LCDs and plasma flat panel displays. The generation of substantial errors in the timing of the generated synchronization signal, which is a disadvantage of the conventional synchronization signal generation scheme, is avoided.

According to the present invention, an improved scheme for generating a synchronization signal based on a received synchronization signal can be provided.

Claims (44)

According to a predefined output timing standard, based on the received synchronization signal 601, a synchronization signal generator that generates a synchronization signal 602—the received synchronization signal 601 and the generated synchronization signal 602 are Comprising horizontal and vertical video synchronization signals, Detection means (610, 710) for detecting a deviation in timing of the received synchronization signal (601) from a predefined input timing standard; A timing adjustment circuit 620, 720 for adjusting the timing of the generated synchronization signal 602 based on the deviation detected by the detection means 610, 710; Synchronization signal generator. The method of claim 1, The detection means 710 and 810 count counters 715 and 815 for counting the first pixel clock signal to measure the time period between the received synchronization signals 601 and 801 in units of pixel clock count values. A synchronization signal generator that includes. The method of claim 2, The counter (715, 815) counts the number of pixels for a predefined number of subsequent input image periods. The method of claim 3, wherein Wherein the period corresponds to one or two subsequent input fields. The method of claim 3, wherein Wherein the period corresponds to 10 subsequent input fields. The method of claim 3, wherein The number of subsequent input images is a synchronization signal that is preset such that a period t0 of the number of subsequent input images according to the input timing standard corresponds to a period t0 of an integer subsequent output image according to the output timing standard. generator. The method according to any one of claims 1 to 6, The timing adjustment circuit (620, 720, 810) for adjusting the timing of the generated synchronization signal (602, 802) of the current output image. The method of claim 6, The timing adjustment circuits 620, 720, 810 adjust the timing of the generated synchronization signals 602, 802 of the sequence of output images, wherein the number of images in the sequence is determined by the period of the sequence according to the output timing standard. and t0) is preset to correspond to the period t0 of the preset number of subsequent input images. The method of claim 8, The timing adjustment circuits 620, 720, and 810 synchronize to increase the number of generated horizontal synchronization signals of the last image of the sequence of output images in response to the number of counted pixels higher than that specified by the input timing standard. Signal generator. The method of claim 8, The timing adjustment circuits 620, 720, 810 are configured to reduce the number of generated horizontal synchronization signals of the last image of the sequence of output images in response to the number of counted pixels lower than that specified by the input timing standard. Signal generator. The method of claim 8, And the timing adjustment circuit (620, 720, 810) distributes the deviation in the number of pixels counted by adjusting the number of generated horizontal synchronization signals in all images of the sequence of output images. The method of claim 11, The timing adjustment circuit (620, 720, 810) further adjusts the time interval between successive horizontal synchronization signals for all lines of the sequence of output images. The method according to any one of claims 8 to 12, The timing adjustment circuits 620, 720, and 810 provide a synchronization signal that completely introduces the detected deviations? T10,? T20,? T30 for the preset number of input images into a sequence of current or subsequent output images. generator. The method according to any one of claims 8 to 13, The timing adjustment circuit (620, 720, 810) further generates a sequence position signal indicative of the current image position relative to the sequence of output images. The method according to any one of claims 1 to 14, The timing adjustment circuit (720, 810) determines a temporal position of the generated synchronization signal (602, 802) according to a second pixel clock signal. The method according to any one of claims 1 to 15, And the timing adjustment circuit (620, 720, 810) determines the number of lines per field or frame to control the synchronization signal generation. The method according to any one of claims 1 to 16, And the timing adjustment circuit (620, 720, 810) determines the number of pixels per line to control the synchronization signal generation. The method according to any one of claims 8 to 17, The timing adjustment circuits 620, 720, and 810 may use the following predefined operations, i.e. (i) introduce a detected deviation in the last image of the sequence of output images by adjusting the number of lines, add the remaining pixels to the last line, (ii) distribute the detected deviation between all images of the sequence of output images by adjusting the number of lines of all said images, add the remaining pixels to the last lines of the last image, (iii) distributing the detected deviation between all images of the sequence of output images by adjusting the number of lines of all the images, distributing the remaining pixels among all the lines of all the images, and remaining pixels of the last image Add to last line A synchronization signal generator that selects an adjustment action from the actions performed. The method of claim 18, And the adjustment operation is selected based on the magnitude and / or direction of the deviation. The method of claim 19, The adjustment operation is selected such that a deviation between the timing of the generated synchronization signal and the output timing standard does not exceed a predefined deviation range. The method of claim 18, And the timing adjustment circuit (620, 720, 810) evaluates the type and time of the received synchronization signal to select the adjustment operation. A video conversion circuit for causing a video signal to be temporally frame rate converted, A synchronization signal generator as claimed in claim 1. Video conversion circuit. A method of generating a synchronization signal based on a received synchronization signal, in accordance with a predefined output timing standard, wherein the received synchronization signal and the generated synchronization signal comprise horizontal and vertical video synchronization signals; Detecting a deviation of timing of the received synchronization signal from a predefined input timing standard (s100); Adjusting the timing of the generated synchronization signal based on the deviation detected by the detecting step (s100) (s200). How to generate a synchronization signal. The method of claim 23, The detecting step (s100) includes counting the first pixel clock signal (s110) to measure a time period between received synchronization signals in units of a pixel clock count value (s110). The method of claim 24, The detecting step (s100) further includes the step (s120) of resetting a count value of the first pixel clock signal upon receiving a specific synchronization signal. The method of claim 25, And the number of pixels is counted for a period of a predefined number of subsequent input images. The method of claim 26, Wherein said period corresponds to one or two subsequent input fields. The method of claim 26, Wherein said period corresponds to 10 subsequent input fields. The method of claim 26, The number of subsequent input images is preset such that the period t0 of the predefined number of subsequent input images according to the input timing standard corresponds to the period t0 of an integer subsequent output image according to the output timing standard. Synchronization signal generation method. The method according to any one of claims 23 to 29, The timing adjusting step (s200) adjusts the timing of the generated synchronization signal (602, 802) of the current output image. The method of claim 29, The timing adjusting step s200 adjusts the timing of the generated synchronization signal of the sequence of output images, wherein the number of images of the sequence is such that the period t0 of the sequence according to the output timing standard is subsequent to the preset number. And a synchronization signal generation method which is preset to correspond to the period t0 of the input image. The method of claim 31, wherein The timing adjustment step (s200) adjusts the number of generated horizontal synchronization signals of the last image of the sequence of output images in response to the number of counted pixels different from the input timing standard (s230a). The method of claim 31, wherein And the timing adjusting step (s200) distributes (s230b) the deviation in the number of counted pixels by adjusting the number of generated horizontal synchronization signals in all images of the sequence of output images. The method of claim 33, wherein The timing adjustment step (s200) further adjusts the time interval between successive horizontal synchronization signals for all the lines of the sequence of the output image. The method according to any one of claims 31 to 34, wherein And the timing adjustment step (s200) completely introduces detected deviations (Δt10, Δt20, Δt30) for the preset number of input images into a sequence of current or subsequent output images. The method according to any one of claims 31 to 35, Generating a sequence position signal indicative of the current image position relative to the sequence of output images. The method according to any one of claims 23 to 36, The timing adjustment step (s200) is a synchronization signal generation method for determining the temporal position of the output synchronization signal in accordance with a second pixel clock signal. The method according to any one of claims 23 to 37, The timing adjusting step (s200) determines the number of lines per field or frame to control the generation of the synchronization signal. The method according to any one of claims 23 to 38, The timing adjusting step (s200) determines the number of pixels per line to control the generation of the synchronization signal. The method according to any one of claims 31 to 39, The timing adjusting step s200 may include the following predefined operations, namely (i) introducing the detected deviation in the last image of the sequence of output images by adjusting the number of lines (s230a), adding the remaining pixels to the last line, (ii) distributing the detected deviation between all images of the sequence of output images by adjusting the number of lines of all the images (s230b), and adding the remaining pixels to the last line of the last image, (iii) distributing the detected deviation between all images of the sequence of output images by adjusting the number of lines of all the images (s230c), distributing the remaining pixels among all the lines of all the images, and disposing the remaining pixels. Append to last line of last image And (s220) selecting an adjustment operation from the operations to perform the synchronization signal generation. The method of claim 40, And the adjustment operation is selected based on the magnitude and / or direction of the deviation. 42. The method of claim 41 wherein And the adjustment operation is selected such that the deviation between the timing of the generated synchronization signal and the output timing standard does not exceed a predefined deviation range. The method of claim 40, The timing adjustment step (s200) further comprises the step of evaluating the type and time of the received synchronization signal to select the adjustment operation. A method for causing a video signal to be temporally frame rate converted, 44. A method for generating a synchronization signal according to any one of claims 23 to 43 How to convert video.

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