JP2844675B2 - Television receiver - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a television receiver suitable for application to, for example, a high-vision receiver having an aspect ratio of a screen different from an ordinary one.

[Summary of the Invention]

The present invention relates to a television receiver capable of selectively receiving video signals of two different aspect ratios, such as a video signal for a high-definition video signal and a video signal of the NTSC system, by changing the phase of a vertical synchronizing signal of the video signal. This makes it possible to easily adjust the display position of the image.

[Conventional technology]

2. Description of the Related Art In recent years, a video signal transmission system for displaying a high-resolution image called high-definition has been developed. In this Hi-Vision system, not only the resolution of the image is simply increased, but also the width of the screen in the horizontal direction is widened so that the screen is longer than the screen using a normal video signal. The ratio between the width and height of such a screen is called an aspect ratio.The conventional screen aspect ratio of a normal video signal is 4: 3, whereas in a high-definition system, it is 16: 9. It has been proposed to.

For this reason, when considering a television receiver capable of receiving both a high-definition video signal and a normal video signal such as the NTSC system, assuming that the screen size is for high-definition television, the aspect ratio is high when receiving a normal video signal. Part of the image is cut by the difference in the ratio.

An example in which an NTSC video signal is received on a high-vision aspect ratio screen is shown in FIG. 5A. For example, as shown in FIG. Let it be displayed on the screen. In this case, since the screen size for HDTV is wider than the NTSC system as shown in FIGS. 5B and 5C, when displaying the image on the entire screen for HDTV, the upper or lower part of the original image is cut. Is done. That is, as shown in FIG. 5B, the lower part of the image is cut and displayed, or as shown in FIG. 5C, the upper part and the lower part of the image are equally cut and the center part is displayed. May be.

Although various display states are conceivable as described above, it is desirable that a part to be cut can be appropriately selected according to a position where a viewer wants to see is displayed.

[Problems to be solved by the invention]

However, there is a disadvantage that the circuit configuration for changing the display state is complicated. That is, for example, if a DC bias current is superimposed on a vertical deflection current supplied to a cathode ray tube, a display image can be moved up and down by changing the amount of the bias current. When a bias current is superimposed, adjustment values such as pin distortion and convergence change, causing inconvenience such as image distortion, and a complicated circuit is required for correction. Also, if each horizontal scanning line is shifted using a frame memory, the display state can be changed without adjusting the deflection system, but the frame memory and its peripheral circuits have a very large circuit configuration. The structure is complicated and the frame memory is expensive.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and it is an object of the present invention to enable a display position to be adjusted with a simple configuration when displaying images having different aspect ratios.

[Means for solving the problem]

The television receiver of the present invention, for example, as shown in FIGS. 1 and 2, converts a video signal having a first aspect ratio and a video signal having a second aspect ratio different from the first aspect ratio into two. In a television receiver capable of selectively displaying an image on a video display section (8) of a screen having a first aspect ratio, a predetermined number of horizontal synchronization signals are reset by a vertical synchronization signal of a video signal having a second aspect ratio. The first to count
Counting means (13), a second counting means (14) which is reset when the first counting means (13) counts a predetermined number, and counts a horizontal synchronizing signal, and a second counting means (14) And a means (15) and (18) for generating a pseudo vertical synchronization signal in accordance with the output of the comparator (16). By changing the value, a pseudo vertical synchronizing signal in which the phase of the vertical synchronizing signal is changed within a predetermined range is generated, and the second aspect ratio is displayed on the video display section (8) in synchronization with the pseudo vertical synchronizing signal. Is displayed.

[Action]

According to such a configuration, the display image is shifted in the vertical direction by changing the phase of the vertical synchronization signal, and the display position is adjusted.

〔Example〕

Hereinafter, an embodiment of a television receiver of the present invention will be described with reference to the accompanying drawings.

In this example, the aspect ratio CR for HDTV
A television receiver equipped with T is capable of receiving an NTSC video signal and a high-vision video signal. That is, in FIG. 1, (1) indicates a reception signal input terminal to which a signal received from an antenna or the like is supplied, and a reception signal obtained at this input terminal (1) is supplied to a tuner (2).
The tuner (2) extracts a video signal of a desired channel. Also, in the figure, (3) and (4) show a video tape reproducing device and a video disk reproducing device, and the reproduced video signals are output from the respective reproducing devices (3) and (4).

The video signal output from the tuner (2) is supplied to the first fixed contact (5a) of the changeover switch (5), and the video signal output from the video tape reproducing device (3) is supplied to the first fixed contact (5) of the changeover switch (5). The second fixed contact (5b) is supplied to the third fixed contact (5c) of the change-over switch (5). Then, the video signal obtained at the movable contact (5m) of the changeover switch (5) is supplied to the synchronization separation circuit (6). The synchronization separation circuit (6) separates the horizontal synchronization signal H and the vertical synchronization signal V from the video signal, and processes the video signal output from the synchronization separation circuit (6) and the horizontal and vertical synchronization signals H and V into a video signal. Supply to circuit (7). The sync separation circuit (6) and the video signal processing circuit (7) are NTSC video signal processing circuits having 262.5 horizontal scanning lines in one field period, and the high definition video signal is a MUSE signal decoder. Is supplied to another circuit system (not shown) provided with the above-mentioned components, and is received by a cathode ray tube (8) described later.

Then, the video signal processing circuit (7) performs a so-called double-speed scanning of twice the number of horizontal scanning lines in one frame of the supplied video signal (the number of horizontal scanning lines in one field period is 525).
And converts the converted video signal into a signal for image reception, and then supplies it to a cathode ray tube (8). In this case, the display on the cathode ray tube (8) is the same as that shown in FIG.
In displaying the video signal of the system, tens of horizontal scanning lines (for example, 66 horizontal scanning lines in one field) are cut, and the remaining video is displayed in an enlarged vertical direction. The video signal processing circuit (7) converts the horizontal synchronizing signal H into a horizontal synchronizing signal 2H for double-speed scanning.
(A frequency signal twice as high as the horizontal synchronizing signal H), and supplies this horizontal synchronizing signal 2H to the deflection circuit (9).

In this example, the vertical synchronizing signal V output from the synchronizing signal separating circuit (6) and the horizontal synchronizing signal 2H for double-speed scanning output from the video signal processing circuit (7) are converted into a vertical synchronizing processing circuit (10). To supply. This vertical synchronization processing circuit (10)
Is a circuit for outputting a pseudo vertical synchronizing signal V 'in which the phase of the vertical synchronizing signal V is changed within a predetermined range. The circuit changes the phase by an amount based on adjustment data obtained from the outside. 10) The pseudo vertical synchronization signal V 'output by
Is supplied to the deflection circuit (9).

The horizontal and vertical deflection of the electron beam of the cathode ray tube (8) is controlled based on the horizontal synchronization signal 2H and the pseudo vertical synchronization signal V 'obtained by the deflection circuit (9), and the video signal processing circuit (7) Is displayed on the cathode ray tube (8).

Here, if the circuit configuration of the vertical synchronization processing circuit (10) is shown in FIG. 2, the horizontal synchronization signal 2H for double-speed scanning supplied from the video signal processing circuit (7) is input via the input terminal (10a). The signal is supplied to a frequency multiplying circuit (11), and the frequency multiplying circuit (11) converts the signal into an eight-fold frequency signal 16H. Then, the frequency signal 16H is supplied to the first counter (12) as a clock signal. Then, the vertical synchronization signal V supplied from the synchronization separation circuit (6) is supplied to the reset signal input terminal of the first counter (12) via the input terminal (10b). The first counter (12) outputs a count signal every eight cycles of the clock signal. With this configuration, as the count signal of the first counter (12), a sub-horizontal synchronization signal 2H ′ having the same synchronization as the horizontal synchronization signal 2H obtained by dividing the frequency signal 16H by 8 is obtained.

Then, the sub-horizontal synchronization signal 2H 'is supplied to the clock signal input terminals of the second, third and fourth counters (13), (14) and (15). In this case, the second counter (13)
Is supplied with the vertical synchronizing signal V obtained at the input terminal (10b). The second counter (13) outputs a count signal when the clock signal has counted 459 cycles. This count signal is sent to the third
As a start signal S. When the start signal S is supplied, the third counter (14) starts counting the sub-horizontal synchronization signal 2H ', and compares the count signal, which changes every cycle of the sub-horizontal synchronization signal 2H', with the comparator. (16) is supplied to one comparison signal input terminal.

In the figure, reference numeral (10c) denotes an adjustment data input terminal, to which adjustment data for controlling a display state is supplied from a central control unit (not shown) of each circuit of the television receiver. Is done. In this case, as the adjustment data, a signal according to a count signal of a preset count value in the range of the count value 0 to 132 is supplied, and this adjustment data is supplied to the comparator (16) via the register (17). It is supplied to the other comparison signal input terminal. And this comparator (1
In step 6), when a match between the count value indicated by the count signal supplied to one input terminal and the count value supplied as the adjustment data is detected, a coincidence pulse P is output.

Then, the coincidence pulse P is supplied to the fourth counter (15) as a start signal. The fourth counter (15)
When the coincidence pulse P is supplied, the sub-horizontal synchronization signal
The counting of 2H 'is started, and 1 of this sub-horizontal synchronization signal 2H' is
A count signal that changes every cycle is supplied to the decoder (18). The decoder (18) is a pseudo-vertical synchronous circuit which becomes a low level signal "0" when the count value of the supplied count signal is in the range of 0 to 5, and becomes a high level signal "1" when the count value exceeds 5. The signal V 'is supplied to an output terminal (10d). Then, the pseudo vertical synchronizing signal V 'obtained at the output terminal (10d) is supplied to the deflection circuit (9).

The operation at the time of receiving an image with the television receiver having such a configuration will be described. First, the overall operation will be described with reference to the time chart of FIG. The television receiver of this example can receive an image from a desired image signal source by switching an input image signal by switching a changeover switch (5). Here, when a video signal source from which an NTSC video signal is obtained is selected, the video signal is supplied to the sync separation circuit (6). Assuming that this video signal is a signal having a cycle as shown in FIG. 3A, a vertical synchronization signal V (FIG. 3B) is extracted from this video signal in one field cycle, and this vertical synchronization signal V is processed by video signal processing. To the circuit (7) and the vertical synchronization processing circuit (10). Here, when a predetermined horizontal scanning period elapses after the vertical synchronization signal V is supplied to the vertical synchronization processing circuit (10), the start signal S (the first counter) is supplied to the third counter (14) in the vertical synchronization processing circuit (10). 3C) is supplied, and when a predetermined period indicated by the adjustment data elapses after the start signal is supplied,
A pseudo vertical synchronization signal V 'is output. This pseudo vertical synchronizing signal V 'is, for example, as shown in FIGS.
The output is delayed from the start signal by a period (t ₁ , t ₂ and t ₃ ) indicated by the adjustment data. In this case, when the adjustment data is data of the midpoint which will be described later, the pseudo vertical synchronizing signal V 'which is output with a delay period t ₂ is set at this time, a vertical synchronizing signal V shown in FIG. 3 B The phases become equal with a shift of one field period. Therefore, by changing the adjustment data before the middle point, a pseudo vertical synchronization signal V 'having a phase advanced from the vertical synchronization signal V can be obtained as shown in FIG. 3D, for example. By changing the adjustment data later, a pseudo vertical synchronizing signal V 'having a phase delayed from that of the vertical synchronizing signal V can be obtained, for example, as shown in FIG. 3F.

Here, the operation in which the pseudo vertical synchronization signal V 'is formed in the vertical synchronization processing circuit (10) will be described with reference to the time chart of FIG. 4. First, the vertical synchronization signal V' as shown in FIG. Is supplied to an input terminal (10b), and a horizontal synchronizing signal 2H for double-speed scanning as shown in FIG. 4B is input to the input terminal (10a).
Is supplied to At this time, this horizontal sync signal
A frequency signal 16H (FIG. 4C), which is eight times as large as 2H, is generated by the frequency multiplier circuit (11). And a first counter (12)
In this case, the vertical synchronizing signal V is supplied as a reset signal.
And a sub-horizontal synchronization signal 2H 'having the same phase as the sub-horizontal synchronization signal 2H' is generated. When the second counter (13) detects that 459 cycles of the sub-horizontal synchronization signal 2H 'has elapsed from the timing when the vertical synchronization signal V rises, the second counter (13) starts to temporarily become the low level signal "0". The signal S (FIG. 4E) is output.
When the start signal S is supplied to the third counter (14), the third counter (14) turns on the sub-horizontal synchronization signal 2H '.
Is started to output a count signal as shown in FIG. 4F. When this count value matches the count value indicated by the adjustment data obtained at the terminal (10c), the low level signal " A coincidence pulse P (FIG. 4G) which becomes "0" is output. For example, FIG. 4 shows a case where the count value 50 is set by the adjustment data. When the coincidence pulse P is supplied to the fourth counter (15), the fourth counter (15) starts counting the sub-horizontal synchronizing signal 2H 'and counts the count signal as shown in FIG. Is output, but when this count value is between 0 and 5,
The decoder (18) outputs a pseudo vertical synchronizing signal V '(FIG. 4I) which becomes a low level signal "0".

Here, the count value indicated by the adjustment data is 0 to
It changes within the range of 132, and the count value 66 at the middle point is set as the standard value. When the adjustment data is set to the standard value in this way, NT
When receiving SC video signals, double speed scanning is performed.
Although the number of horizontal scanning lines in the field becomes 525, 459 horizontal scanning periods (while the second counter (13) counts 459) elapse from the output of the vertical synchronization signal V to the output of the start signal S. After the start signal S is output, 66 horizontal scanning periods (the third counter (14)
The pseudo vertical synchronizing signal V '
Will be output. Therefore, the pseudo vertical synchronizing signal V 'is output after the elapse of (459 + 66) = 525 horizontal scanning periods after the output of the vertical synchronizing signal V, and the pseudo vertical synchronizing signal V' is output one field period later. Become
As shown in FIGS. 3B and 3E, there is no phase difference between the vertical synchronizing signal V and the pseudo vertical synchronizing signal V '.

Then, the adjustment data is set to a value before or after the standard value 66 (0 to 0).
132), the maximum vertical synchronization signal V and ± 66
A pseudo vertical synchronizing signal V 'having a phase difference during the horizontal scanning period is output. The phase difference in this case is set for each horizontal scanning cycle.

The pseudo vertical synchronizing signal V 'generated in this way is supplied to the deflection circuit (9), whereby the display position of the image displayed on the cathode ray tube (8) can be adjusted up and down. That is, the cathode ray tube (8) of the television receiver of the present embodiment.
5B and C when receiving the NTSC video signal
As shown in FIG. 5, dozens of horizontal scanning lines of the original video (FIG. 5A) are cut off, but the pseudo vertical synchronizing signal V 'changes every one horizontal scanning period due to the adjustment data, and is therefore indicated by the adjustment data. By changing the count value, the displayed image can be moved up and down by one horizontal scanning line. At this time, when the count value indicated by the adjustment data is the minimum value of 0, as shown in FIG. 5B, the horizontal scanning line on the lower side of the screen is cut, and when the count value is the maximum value of 132,
As shown in FIG. 5C, the horizontal scanning line on the upper side of the screen is cut. When the standard value is set to 66, the top and bottom of the screen are equally cut, and the center is displayed.

Thus, according to the television receiver of this example, the NTSC
When displaying video signals of the HDTV system on a high-definition cathode ray tube (8), the display position can be moved up and down only by setting the adjustment data, and the display position can be easily adjusted without adjusting the deflection circuit and the like. it can.

Further, in this example, in the vertical synchronization processing circuit (10), the sub-horizontal synchronization signal 2H 'synchronized with the vertical
Since the pseudo vertical synchronizing signal V 'is generated based on the sub-horizontal synchronizing frequency 2H' based on the frequency signal 16H which is eight times the horizontal synchronizing signal 2H, the vertical synchronizing circuit (1
Even when the horizontal synchronization signal 2H supplied to (0) includes a jitter component, the fluctuation of the output pseudo vertical synchronization signal V ′ can be minimized. That is, the horizontal synchronizing signal may include jitter when the reception state in the tuner (2) is poor or when reproduced from the VTR (3), but the horizontal synchronizing signal 2H is directly counted and the pseudo vertical synchronizing signal V ', The pseudo vertical synchronizing signal V' may fluctuate for one horizontal scanning period and the display line may fluctuate temporarily even if this horizontal synchronizing signal 2H contains a slight jitter component. In the case of the present example, since it is created from the sub-horizontal synchronization signal 2H 'which is in phase with the vertical synchronization signal V, it is suppressed by a slight fluctuation, and no temporary fluctuation of the display line occurs.

In the above-described embodiment, a case has been described in which an NTSC video signal is received by a high-vision receiver. However, the present invention is not limited to this method, and various types of video signals having different aspect ratios are received. Of course, it can be applied in the case of.

〔The invention's effect〕

ADVANTAGE OF THE INVENTION According to the television receiver of this invention, when the aspect ratio set by a video signal differs from the aspect ratio of a display screen, there exists an advantage which can adjust a display position easily.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a television receiver of the present invention, FIG. 2 is a block diagram of a main part of the example of FIG. 1, and FIGS. 3 and 4 are explanations of the example of FIG. FIG. 5 is a schematic diagram for explaining a display state. (8) is a cathode ray tube, and (10) is a vertical synchronization processing circuit.

Claims (1)

(57) [Claims] A video signal having a first aspect ratio;
A video signal having a second aspect ratio different from the aspect ratio of the first aspect ratio on a video display portion of a screen having the first aspect ratio; A first signal which is reset by a vertical synchronizing signal and counts a predetermined number of horizontal synchronizing signals.
Counting means, a second counting means which is reset when the first counting means has counted the predetermined number, counts the horizontal synchronizing signal, and a count value of the second counting means and the adjustment data. A comparator for performing comparison, and means for generating a pseudo vertical synchronization signal according to the output of the comparator are provided, and by changing the value of the adjustment data, the phase of the vertical synchronization signal falls within a predetermined range. A television receiver, wherein a changed pseudo vertical synchronizing signal is generated, and the video signal of the second aspect ratio is displayed on the video display section in synchronization with the pseudo vertical synchronizing signal. .