JP2644045B2 - Time compression device for HDTV receiver - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time compression device for a high-definition television receiver, and more particularly to a method for displaying a NTSC television signal converted into progressive scan on a high-vision display. Also, the present invention relates to a circuit for performing time compression so that the linearity of a reproduced image is not changed by digital processing.

[Conventional technology]

A reproduced image of an NTSC television signal converted into a progressive scan (hereinafter referred to as an NTSC signal) has a frame frequency of
59.94Hz, horizontal frequency is 31.47KHz. On the other hand, the HDTV signal has a field frequency of 60 Hz and a horizontal frequency of 33.75.
KHz. Therefore, since the vertical frequency and the horizontal frequency of the NTSC signal and the HDTV signal are very close values, the NTSC signal can be displayed on the HDTV display.
At this time, the ratio of the vertical blanking period to one frame period in the NTSC display and the high-vision display is defined by exactly the same value, so that there is no problem in the vertical display. However, the aspect ratio of NTSC signals
In contrast to 4: 3, the aspect ratio of a Hi-Vision signal is 16: 9. The ratio of the horizontal blanking period to one horizontal scanning period in the NTSC display and the high-vision display is about 5: 4. Accordingly, when the ratio in the vertical direction is kept constant and the ratio of the number of unit pixels in one horizontal scanning period between the NTSC signal and the Hi-Vision signal is calculated from these numerical values, the ratio is approximately 4: 5. That is, in order to display the NTSC signal on a high-vision display while maintaining the linearity, it must be compressed about 4/5 times in the horizontal direction. A method of changing the horizontal deflection current of the high-definition display to 4/5 times the compression in the horizontal direction can be considered. FIG. 4 shows an example of this general configuration.

In the figure, 1 is an NTSC signal input terminal, 2 is an A / D converter which receives a signal arriving at the NTSC signal input terminal 1 and 3 is A
Synchronization / timing pulse generation circuit having the output of the / D converter 2 as an input, 4 an IDTV decoder having the output of the A / D converter 2 and the synchronization / timing pulse generation circuit 3 as an input, 6 to 8
A D / A converter which receives the output of the IDTV decoder 4 as an input.
A video circuit having the outputs of the converters 6 to 8 as inputs, a synchronization circuit 10 having an output of the synchronization / timing pulse generation circuit 3 as an input, and a inputs 11 having outputs of the synchronization / timing pulse generation circuit 3 and the synchronization circuit 10 as inputs. A high-definition display 12 receives the outputs of the video circuit 9 and the deflection circuit 11 as input.

 Next, the operation will be described.

The analog signal arriving at NTSC signal input terminal 1 is A /
The signal is input to the D converter 2 and converted into a digital signal. The output of the A / D converter 2 is input to the synchronization / timing pulse generation circuit 3 and the IDTV decoder 4. The synchronization / timing pulse generation circuit 3 generates a clock synchronized with the output signal of the A / D converter 2 and outputs a clock and various timing pulses to the IDTV decoder 4. Further, it outputs a synchronization signal to the synchronization circuit 10 and a signal that the NTSC signal is received to the deflection circuit 11 (hereinafter, referred to as an NTSC determination signal). The IDTV decoder 4 digitally processes the output of the A / D converter 2 to perform luminance signal chrominance signal separation and sequential scan conversion to obtain a frame frequency of 5
It outputs RGB signals of 9.94 Hz, 525 scanning lines, and progressive scanning to the D / A converters 6 to 8. Digital processing of the IDTV decoder 4 is controlled by the output of the synchronization / timing pulse generation circuit 3. The D / A converters 6 to 8 convert a digital input into an analog signal. The video circuit 9 has D / A converters 6 to 8
Is amplified and output to the HDTV display 12. The synchronizing circuit 10 separates a horizontal synchronizing signal and a vertical synchronizing signal from the synchronizing signal output from the synchronizing / timing pulse generating circuit 3 and outputs the same to the deflection circuit 11. The deflection circuit 11 is a synchronous circuit 10
The horizontal deflection current and the vertical deflection current are determined from the output of, and are output to the HDTV display 12. As described above, when the input of the video circuit 9 is the output of the D / A converters 6 to 8, the output of the deflecting circuit 11 is adjusted in the vertical direction when the input of the video circuit 9 is adjusted to the HDTV signal. On the other hand, since there is only 4/5 information in the horizontal direction, an image stretched 5/4 times in the horizontal direction is displayed on the high definition display 12. Therefore, in this case, in order to display the output of the video circuit 9 on the HDTV display 12 while maintaining the linearity, it is necessary to change the horizontal deflection current of the output of the deflecting circuit 11 to compress the HDTV display horizontally 4/5 times. There is. FIG. 5A shows a case where the input of the video circuit 9 is a high definition signal, and FIG. 5B shows a case where the input of the video circuit 9 is the output of the D / A converters 6 to 8. In FIG. 5B, the value of the horizontal deflection current is made smaller than in the case of FIG. 5A, and the display on the high-definition display is compressed to 4/5 times in the horizontal direction. In the case of FIG. 5 (a) and FIG. 5 (b), the display on the high definition display 12 is as shown in FIG. 6 (a) and FIG. 6 (b), respectively. The shaded portion in FIG. 6B is the blanking level. Switching of the horizontal deflection current output from the deflection circuit 11 is performed by an NTSC determination signal output from the synchronization / timing pulse generation circuit 3. Thus, the HDTV display 12 can display HDTV signals and NTSC signals with correct linearity.

[Problems to be solved by the invention]

The conventional time compression device of the HDTV receiver performs time compression in the horizontal direction with the above configuration.
There is a problem in that the horizontal deflection current of the deflection circuit must be switched by the determination signal, and the deflection circuit becomes complicated, and adjustment of the color shift and the like of the high-vision display must be performed in accordance with two deflection widths. Was.

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-described problems, and has as its object to provide a time compression device of a high-definition receiver capable of performing time compression in a horizontal direction without switching a horizontal deflection current.

[Means for solving the problem]

A time compression device for a high-definition receiver according to the present invention includes an A / D converter for converting an NTSC composite television signal into a digital signal, and a clock and a timing pulse from an output signal of the A / D converter. Synchronization / timing pulse generating means, and an ID for outputting a signal of a digital amount of sequential scanning from the output signal of the A / D conversion means and the output signal of the synchronization / timing pulse generating means
The IDTV decoder, comprising: a TV decoder; a line memory receiving the output signal of the IDTV decoder as input; and a horizontal synchronizing means for outputting a control signal for horizontally compressing the signal input to the line memory in the horizontal direction. Time compression means for time-compressing the output signal in the horizontal direction. The horizontal synchronization means in the time compression means, counting the output signal of the synchronization / timing pulse generation means, and the NTSC composite television signal. A first horizontal count reset for each one frame period, phase comparison means having an output signal of the first horizontal counter as one of its inputs, and a loop filter for integrating the output signal of the phase comparison means. A voltage-controlled oscillating means that receives the output signal of the loop filter as an input, Rutotomoni, its output is obtained shall become and a second horizontal counter to the other input of the phase comparing means.

[Action]

In the present invention, since the configuration is as described above, time compression can be performed in the horizontal direction without switching the horizontal deflection current, and adjustment of color shift and the like of a high definition display can be performed with a constant deflection width.

Further, in the present invention, since the configuration is as described above, the time compressing means can be configured only with a digital circuit.

Further, in the present invention, since the configuration is as described above, it is possible to stably synchronize the horizontal synchronizing means.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a configuration of a time compression circuit according to an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes an NTSC signal input terminal; D / D converter 3 is a synchronization / timing pulse generation circuit having an output of the A / D converter 2 as an input. 4 is an IDTV decoder having an output of the A / D converter 2 and the synchronization timing pulse generation circuit 3 as an input. Is a time compression circuit that receives the output of the synchronization / timing pulse generation circuit 3 and the IDTV decoder 4 as inputs, 6 to 8 are D / A converters that receive the output of the time compression circuit 5, and 9 is a D / A converter 6 A video circuit with the outputs of ~ 8 as inputs, 10
A synchronizing circuit receives the output of the timing pulse generating circuit 3 as an input, a deflecting circuit 11 receives an output of the synchronizing circuit 10 as an input, and a reference numeral 12 denotes a high-vision display that receives outputs of the video circuit 9 and the deflecting circuit 11 as inputs.

 Next, the operation will be described.

The analog signal arriving at NTSC signal input terminal 1 is A /
The signal is input to the D converter 2 and converted into a digital signal. The output of the A / D converter 2 is input to the synchronization / timing pulse generation circuit 3 and the IDTV decoder 4. The synchronizing / timing pulse generating circuit 3 generates a clock synchronized with the output signal of the A / D converter 2 to generate an IDTV decoder 4 and a time compressing circuit 5.
Clock and various timing pulses. Further, a synchronization signal is output to the synchronization circuit 10. IDTV decoder 4 is A /
The output of the D converter is digitally processed to perform luminance signal chrominance signal separation and sequential scan conversion, and to output to the time compression circuit 5 a frame signal of 59.94 Hz, 525 scanning lines, and progressive scan RGB signals. The digital processing of the IDTV decoder is controlled by the output of the synchronization / timing pulse generation circuit 3. The time compression circuit 5 time-compresses the RGB signal output from the IDTV decoder 4 by 4/5 in the horizontal direction by digital processing.

FIG. 2 shows the configuration of the time compression circuit 5. The RGB signal outputs of the IDTV decoder 4 are time-compressed by the line memories 13, 14, and 15, respectively. At this time, the control of the line memories 13 to 15 is performed by the output of the horizontal synchronization circuit 16.

FIG. 3 shows the configuration of the horizontal synchronization circuit 16. The clock WCK output from the synchronization / timing pulse generation circuit 3 is IDT
Horizontal synchronization is performed at the same frequency as the transmission rate of the output data of the V decoder 4, and the horizontal counter 17 counts the clock WCK.

The horizontal counter 21 counts the output clock RCK of the voltage controlled oscillator VCO20. The number of samples for one horizontal scanning period is set in advance in these horizontal counters 17 and 21, and the set value of the horizontal counter 17 is set in the horizontal counter.
It is 4/5 times the setting value of 21.

The output of the horizontal counter 17 and the output of the horizontal counter 21 are input to the phase comparator 18 and the phases are compared every horizontal scanning period. At this time, a signal is output to the outputs of the horizontal counter 17 and the horizontal counter 21 every time a preset set value is counted, and the relationship between the output signal of the horizontal counter 17 and the output signal of the horizontal counter 21 will be described. When,
The clock RCK has a frequency that is 5/4 times the frequency of the clock WCK, and the set value of the horizontal counter 21 that counts the clock RCK is 5/4 of the set value of the horizontal counter 17 that counts the clock WCK.
Therefore, the output signal of the horizontal counter 17 and the output signal of the horizontal counter 21 have the same cycle.

The output of the phase comparator 18 is
, And becomes the control voltage of the voltage controlled oscillator 20.

As described above, the output signals of the horizontal counter 17 and the horizontal counter 21 are input to the phase comparator 18, the phases are compared every one horizontal scanning period, the output is integrated by the loop filter 19, and the integrated output is By setting the control voltage to 20, a feedback loop of the output signal of the horizontal counter 21 is formed.

When this loop is stabilized, a frequency clock RCK 5/5 times the clock WCK synchronized with the clock WCK of the horizontal counter 17 is obtained from the output of the voltage controlled oscillator 20. That is, the clock RCK is a stable clock synchronized with the clock WCK at a frequency that is 5/4 times the clock WCK.

Therefore, the line memory 1 is used by using these clocks WCK and RCK.
By writing and reading 3,14,15,
The process of time-compressing the output of the DTV decoder 4 in the horizontal direction is realized. Therefore, the line memories 13, 14, 15
WCK is used as a write clock, and a reset pulse WRT obtained from the horizontal counter 17 is used for reset. Similarly, RCK is used as the read clock for line memories 13, 14, 15.
The reset pulse RRT obtained from the horizontal counter 21 is used for resetting. Further, the horizontal counter 17 is reset by the frame pulse FP output from the synchronization / timing pulse generation circuit 3 so that the synchronization is stably performed. Therefore, the RCKs of the line memories 13, 14, 15 are horizontally synchronized with the WCK, and since the RCK is 5/4 times the frequency of the WCK, the output of the IDTV decoder 4 is time-compressed to 4/5 times in the horizontal direction. . The output of the time compression circuit 5 is input to the D / A converters 6 to 8 and converted into analog signals. The outputs of the D / A converters 6 to 8 are input to the video circuit 9, amplified by the video circuit 9, and sent to the high-vision display 12. The synchronization signal of the output of the synchronization / timing pulse generation circuit 3 is synchronized with the synchronization circuit 10
The signal is then separated by a synchronization circuit 10 into a horizontal synchronization signal and a vertical synchronization signal, and sent to a deflection circuit 11. The deflection circuit 11 determines a horizontal deflection current and a vertical deflection current from the output of the synchronization circuit 10 and outputs them to the HDTV display 12. Deflection circuit 11
The horizontal deflection current of the output is adjusted to the horizontal deflection width of the HDTV signal. The HDTV display 12 displays the output signal of the video circuit 9 in accordance with the output current of the deflection circuit 11.

According to the above-described embodiment, the time compression circuit including the line memory and the horizontal synchronization circuit is provided in the conventional device, so that the time can be compressed in the horizontal direction without switching the horizontal deflection current. The adjustment of the color shift and the like of the display can be performed with a constant deflection width.

〔The invention's effect〕

As described above, according to the time compression device for a high-definition receiver according to the present invention, A / D conversion means for converting an NTSC composite television signal into a digital signal, and output of the A / D conversion means Synchronization / timing pulse generation means for generating a clock and timing pulse from a signal, and an IDTV for outputting a signal of a digital amount of sequential scanning from an output signal of the A / D conversion means and an output signal of the synchronization / timing pulse generation means A line memory that receives an output signal of the IDTV decoder as input, and a horizontal synchronizing unit that outputs a control signal for temporally compressing a signal input to the line memory in a horizontal direction;
Time compression means for time-compressing the output signal of the TV decoder in the horizontal direction, wherein the horizontal synchronization means in the time compression means counts the output signal of the synchronization / timing pulse generation means, and the NTSC composite television 1st reset every frame period of the
A horizontal counter, a phase comparison means using the output signal of the first horizontal counter as one input, a loop filter integrating the output signal of the phase comparison means, and an output signal of the loop filter as an input. A voltage-controlled oscillating means, and a second horizontal counter which counts the output signal of the voltage-controlled oscillating means and uses the output as the other input of the phase comparing means.
Time compression can be performed in the horizontal direction without switching the horizontal deflection current, and there is an effect that adjustment of a color shift or the like of a high definition display can be performed with a constant deflection width. Further, the time compression means can be constituted only by a digital circuit, so that there is an effect that time compression can be performed stably and with high accuracy against aging. Further, there is an effect that it is possible to stably synchronize the horizontal synchronizing means.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of a high-definition television receiver having a time compression circuit according to one embodiment of the present invention, FIG. 2 is a block diagram of the configuration of a time compression circuit according to one embodiment of the present invention, and FIG. FIG. 4 is a block diagram showing the configuration of a time synchronization circuit of a conventional HDTV receiver, and FIG. 5 is a block diagram showing the configuration of a time compression circuit of a conventional HDTV receiver according to an embodiment of the present invention. FIG. 6 is a diagram showing a relationship between a video signal and a horizontal deflection current, and FIG. 6 is a diagram showing a display on a high definition display. In the figure, 1 is an NTSC signal input terminal, 2 is an A / D converter,
3 is a synchronization / timing pulse generation circuit, 4 is an IDTV decoder, 5 is a time compression circuit, 6, 7, and 8 are D / A converters, 9 is a video circuit, 10 is a synchronization circuit, 11 is a deflection circuit, and 12 is Hi-Vision. A display, 13, 14, 15 are line memories, 16 is a horizontal synchronization circuit, 17 and 21 are first and second horizontal counters, 18 is a phase comparator, 19 is a loop filter, and 20 is a voltage controlled oscillator. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] An A / D converter for converting an NTSC composite television signal into a digital signal, and a synchronization / timing pulse generator for generating a clock and a timing pulse from an output signal of the A / D converter. An IDTV decoder that outputs a signal of a digital amount of sequential scanning from an output signal of the A / D converter and an output signal of the synchronization / timing pulse generator, and a line memory that receives an output signal of the IDTV decoder as an input And a horizontal synchronizing means for outputting a control signal for horizontally compressing the signal inputted to the line memory in the horizontal direction, and a time compressing means for horizontally compressing the output signal of the IDTV decoder in the horizontal direction. The horizontal synchronizing means in the time compressing means,
A first horizontal counter which counts the output signal of the timing pulse generating means and is reset every frame period of the NTSC composite television signal;
Phase comparison means for receiving the output signal of the first horizontal counter as one input, a loop filter for integrating the output signal of the phase comparison means, and voltage control oscillation means for receiving the output signal of the loop filter as input. A high-definition television receiver comprising: a second horizontal counter which counts an output signal of the voltage controlled oscillation means and uses the output as the other input of the phase comparison means. Time compression device.