JP3036066B2 - Display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in the following order.

A Industrial field B Outline of the invention C Conventional technology D Problem to be solved by the invention E Means to solve the problem (FIGS. 1, 9 and 10)
Fig. F action (Fig. 1, Fig. 9 and Fig. 10) G embodiment (Fig. 1 to Fig. 20) (G1) Configuration of embodiment (Fig. 1 to Fig. 20) (G1-1) Picture-in picture circuit (Figs. 6 to 20)
(G2) Operation of the embodiment (G3) Effects of the embodiment (G4) Other embodiments Effects of the H invention A Industrial application field The present invention relates to a display device, for example, a high-definition television broadcast and an NTSC system. The present invention can be applied to a television broadcasting receiver.

B. Summary of the Invention The present invention is the same as the case where a small screen is formed for a video signal having an aspect ratio of 16: 9 in the horizontal direction when a small screen is formed for a video signal having an aspect ratio of 4: 3 in a display device. After sampling at the sampling number, by thinning out the video signal with the aspect ratio 16: 9 at the thinning rate of 3/4 times when forming the child screen,
A child screen with a roundness of 1 can be displayed with a simple configuration.

C Conventional Technology Conventionally, this type of display device has an aspect ratio of 5:
Japanese Patent Application Laid-Open No. SHO 61-61 proposes that a display image having an aspect ratio of 4: 3 is formed by using a CRT of No. 3.
-214872, JP-A-61-214873).

In this type of display device, a separately reduced display image (hereinafter referred to as a small screen) is displayed in a blank portion on the left and right sides of a screen generated when a display image having an aspect ratio of 4: 3 is formed, so that the blank portion is displayed. It is possible to monitor a plurality of programs at the same time by effectively using the program.

D Problems to be Solved by the Invention Incidentally, in this type of display device, the aspect ratio
Some are designed to form a 16: 9 display image.

In a display image with such an aspect ratio of 16: 9, for example,
It would be useful to be able to display the sub-screen of NTSC television broadcasting.

If necessary, display images with an aspect ratio of 16: 9 and NT
It would be convenient if the sub-screens of the SC television broadcast could be displayed interchangeably.

Further, even when the images are exchanged in this way, if a child screen with correct roundness can be displayed, usability can be improved.

The present invention has been made in consideration of the above points, and has as its object to propose a display device that can display various small screens as necessary with a simple configuration.

E Means for Solving the Problem In order to solve the problem, the present invention provides a video signal R, G, B having an aspect ratio of 16: 9 or an aspect ratio of 4: 3.
Alternatively, display the main screen of the SV and switch the video signal R, G, B or SV having the aspect ratio of 16: 9 or 4: 3 to form a sub screen, and display the sub screen in the main screen. In the device 1, a video signal R having an aspect ratio of 16: 9,
For G and B, in the horizontal scanning direction, video signals R, G and B having an aspect ratio of 16: 9 are sampled at a predetermined sampling number (910), and then the compression rate of the small picture (1/3)
In the vertical scanning direction, the video signals R, G, and 16 have the aspect ratio of 16: 9 in the vertical scanning direction.
The line B is thinned out according to the compression ratio (1/3) to form a sub-screen, and the video signal SV having an aspect ratio of 4: 3 is a video signal SV having an aspect ratio of 4: 3 in the horizontal scanning direction. After sampling at the sampling number (910),
Thinning is performed at a thinning rate (1/4) that is 3/4 times the thinning rate (1/3). In the vertical scanning direction, the line of the video signal SV with an aspect ratio of 4: 3 is reduced to a compression rate (1/3). Sub-screens are formed by thinning out accordingly.

F function When forming a small screen with respect to the video signal SV having the aspect ratio of 4: 3, the number of samplings when forming the small screen with respect to the video signals R, G, and B having the aspect ratio of 16: 9 in the horizontal scanning direction (910) After sampling at, the thinning rate (1
/ 3) 3/4 times of the thinning rate (1/4), and in the vertical scanning direction, the line is thinned according to the compression rate (1/3) to form a child screen. Ratio 16: 9
A sub-screen with a roundness of 1 can be displayed in the parent screen of.

G Example Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

(G1) Configuration of Embodiment In FIG. 1, reference numeral 1 denotes a display device as a whole, and a satellite broadcast is received by an antenna 2.

That is, the satellite broadcast receiving circuit 4 receives a channel desired by the user and outputs a video signal of the channel.

The demodulation circuit 6 selects and inputs a video signal of the MUSE (multiple subnyqust sampling encoding) system output from the satellite broadcast receiving circuit 4, and outputs the horizontal and vertical synchronization signals HD and
VD is separated, and the color signals R, G, B are demodulated and output.

The signal level correction circuit 8 converts the color signals R, G, B into Are converted into a luminance signal YH and color difference signals Pb and Pr in accordance with the format of the high-definition television broadcast represented by the formula (1) and output.

The matrix circuit 10 receives the luminance signal YH and the color difference signals Pb and Pr via the selection circuits 12 and 14, and
The cathode ray tube 16 is driven based on H and the color difference signals Pb and Pr.

Here, the cathode ray tube 16 is for high-definition television broadcasting,
Displays a display screen with an aspect ratio of 16: 9.

The deflection circuit 18 receives the horizontal and vertical synchronization signals SH and SV via the selection circuit 20, and drives the deflection yoke 22 of the cathode ray tube 16 based on the synchronization signals SH and SV.

Thus, the display device 1 can display the video signal of the high-definition television broadcast selected by the satellite broadcast receiving circuit 4 via the cathode ray tube 16.

On the other hand, when the satellite broadcast receiving circuit 4 selects an NTSC television broadcast, the satellite broadcast receiving circuit 4 outputs the video signal SV of the channel via the selecting circuit 24.

The demodulation circuit 26 demodulates the video signal SV and outputs a luminance signal and a color difference signal.

The signal level correction circuit 28 calculates the following equation for the red, blue, and green color signals R, G, and B: Y = 0.59G + 0.11B + 0.3R (4) R−Y = −0.59G + 0.89B−0.3 R (5) BY = −0.59G−0.11B + 0.7R (6) NTSC luminance signal Y and chrominance signal R set in the relationship (6)
For -Y and BY, the signal level is corrected, and (1) to
It is converted into a luminance signal and a color difference signal according to the format of the high-definition television broadcast expressed by the equation (3).

The clear vision processing circuit 30 separates the horizontal and vertical synchronization signals HD and VD from the luminance signal Y of the video signal SV, and outputs the signals to the deflection circuit 18 via the selection circuit 20.

Thus, when the NTSC broadcast is selected via the satellite broadcast receiving circuit 4, the deflection circuit 18 drives the deflection yoke 22 according to the NTSC video signal SV.

At this time, the operation of the deflection circuit 18 is switched based on a control signal SC1 output from a system control circuit (not shown) so that the horizontal scanning frequency is changed from the high-definition television broadcasting frequency of 33.75 [kHz] to the NTSC system. Of 1
Even when the frequency is changed to 5.75 [kHz], the drive voltage supplied to the cathode ray tube 16 is maintained at a constant value, whereby the cathode ray tube 16 can be reliably driven even for NTSC video signals. I have.

Further, the clear vision processing circuit 30
Selection circuit for luminance signal Y and color difference signals RY and BY of SV
Output to the aspect ratio conversion circuit 32 via 31.

Here, the aspect ratio conversion circuit 32 compresses the luminance signal Y and the chrominance signals RY and BY in the horizontal scanning direction on the time axis, thereby obtaining the luminance signal Y and the chrominance signals RY and B-Y.
Black display portions are formed at both left and right ends of the display screen formed by Y, and the display image including the black display portions is corrected so as to have an overall aspect ratio of 16: 9.

Further, the aspect ratio conversion circuit 32 outputs the luminance signal Y and the color difference signals RY and BY whose aspect ratios have been corrected to the matrix circuit 10 via the selection circuits 34, 12, and 14 in order.

Thus, when the broadcast of the NTSC system is selected via the satellite broadcast receiving circuit 4, the video signals of the NTSC system can be displayed on the cathode ray tube 16 by switching the contacts of the selection circuits 12, 20, and 24. It has been done.

At this time, the luminance signal Y is output from the aspect ratio conversion circuit 32.
By converting the aspect ratios of the color difference signals RY and BY, as shown in FIG. 2, the cathode ray tube 16 has black display portions on both sides of a display screen having an aspect ratio of 4: 3. In addition, a display image having an aspect ratio of 16: 9 can be displayed as a whole.

Further, the signal level correction circuit 28 corrects the signal levels of the luminance signal and the color difference signal to the format of the high-definition television broadcast represented by the formulas (1) to (3), so that the high-definition television can be realized with a simple configuration. The NTSC video signal SV can be displayed with the same color reproducibility as broadcast.

At this time, as shown in FIG. 3, the clear vision processing circuit 30 shifts the timing of the horizontal synchronizing signal HD based on the control signal output from the system control circuit (not shown) to output the cathode ray tube. Display a 4: 3 aspect ratio display screen on the 16 display screens shifted to the right,
A margin is formed on the left side of the screen.

Further, when the luminance signal and the color difference signal of the adaptive field double speed system are input instead of the luminance signal and the color difference signal of the NTSC system (that is, the video signal of the clear vision system), the clear vision processing circuit 30 The luminance signal and chrominance signal one field before are used for, and for the moving image part, the luminance signal and chrominance signal are interpolated within the field so that the horizontal scanning frequency is 3
The signal is converted into a non-interlaced luminance signal and color difference signal at 0.478 [kHz].

Thereby, the clear vision processing circuit 30 improves the resolution of the luminance signal and the color difference signal.

Thus, the cathode ray tube 16 can display a video signal of the clear vision system, similarly to the case of displaying the video signal SV of the NTSC system.

The selection circuit 34 switches contacts based on the control signal SC1, and when a luminance signal and a color difference signal of the Vista Vision system are selected, the luminance signal and the color difference signal input to the aspect ratio conversion circuit 32 are directly transmitted to the selection circuit 12. Output.

Here, as shown in FIG.
In the SC system or the clear vision system, a large display image for theaters is transmitted as a video signal with an aspect ratio of 4: 3 by providing black display portions at the upper and lower ends.

Thus, in the display device 1, when displaying the video signal of the Vista Vision system, the cathode ray tube 16 is directly driven by the luminance signal and the color difference signal of the Vista Vision without converting the aspect ratio.

At this time, the deflection circuit 18 switches the operation based on the control signal SC1, thereby switching the horizontal and vertical deflection currents in conjunction with the selection circuit 34. As a result, as shown in FIG. The deflection yoke 22 is driven so that the original image of the system is displayed at a time immediately before the display area of the cathode ray tube 16.

Thus, in the display device 1, by switching the contacts of the selection circuits 12, 20, and 34 as necessary, in addition to the video signal of the high-definition television broadcast, the video signal of the NTSC system and the clear vision system can be displayed. it can.

Further, at this time, by switching the contact of the selection circuit 34 and switching the operation of the deflection circuit 18, the cathode ray tube 16
By effectively utilizing the display area, a display image of the Vista Vision system transmitted by the NTSC system or the Clear Vision system can be displayed.

The UV broadcast receiving circuit 36 receives the terrestrial UHF broadcast and VHF broadcast television signals via the antenna 38, and outputs the resulting video signal SV to the demodulation circuit 26 via the selection circuit 24. .

Thus, the display device 1 can receive a terrestrial television broadcast instead of a satellite broadcast by switching the contacts of the selection circuit 24.

Further, at this time, by processing the luminance signal and the color difference signal through the signal level correction circuit 28, the clear vision processing circuit 30, and the aspect ratio conversion circuit 32, the same color reproducibility as that of the high-definition television broadcasting can be obtained, and the terrestrial broadcasting can be performed. Transmitted
It can display NTSC and clear vision video signals.

The video signal processing circuit 40 receives a video signal SV output from an externally connected video device and separates the video signal SV into a luminance signal and a color difference signal.

Further, the video signal processing circuit 40 incorporates a signal level correction circuit and a clear vision processing circuit, and executes the signal level correction processing represented by the equations (1) to (3) on the separated luminance signal and color difference signal. The resolution is improved by the clear vision processing circuit.

Further, the video signal processing circuit 40 outputs the luminance signal and the color difference signal to the selection circuit 31, and outputs the synchronization signals HD and VD of the luminance signal and the color difference signal to the selection circuit 20.

The video tape recorder 42 outputs the luminance signal and the color difference signal of the high-definition television system to the selection circuit 12, and outputs the synchronization signals HD and VD of the luminance signal and the color difference signal to the selection circuit 20.

Thus, in the display device 1, various video signals input from a video tape recorder or an external device can be switched to the high-definition television broadcast by switching the contacts of the selection circuits 12, 20, and 31 as necessary. They are displayed with the same color reproducibility.

In response to this, the system control circuit (not shown) outputs control signals SC1, SC2, SC3 in response to a user operation, and switches the contacts of the selection circuits 12, 20, 24, 31, and 34, The display screen of the cathode ray tube 16 is switched (hereinafter, an image displayed on the entire display screen of the cathode ray tube 16 is referred to as a parent screen).

The sub-screen creation circuit 44 intermittently captures the luminance signal and the color difference signal input via the selection circuit 46, and sequentially outputs the signals at a predetermined timing, so that the horizontal and vertical scanning directions are respectively returned to the original screen. A sub-screen compressed to 1/3 (that is, a sub-screen having a compression ratio of 1/3) is generated.

Further, the sub-screen creation circuit 44 outputs the switching signal YS to switch the contacts of the selection circuit 14 at a predetermined timing, and superimposes the generated sub-screen on the parent screen.

As a result, in the display device 1, a high-definition television broadcast and a clear vision video signal are set as a main screen, and a high-definition television broadcast, a clear vision broadcast and an NTSC sub-screen can be displayed in the main screen. It has been made like that.

(G1-1) Picture-in Picture Circuit Here, as shown in FIG. 6, the picture-in picture circuit 44 includes a luminance signal YH,
The color difference signals Pb and Pr are supplied to the image memory circuit 50, and the luminance signal YH and the horizontal synchronizing signal HD of the color difference signals Pb and Pr are applied to the PLL.
(Phase locked loop).

Here, the PLL circuit 52 supplies the horizontal synchronization signal HD to a phase comparison circuit 54 composed of a three-state inverter circuit, and outputs an output signal of the phase comparison circuit 54 to a low-pass filter circuit (LPF) 56.

The voltage controlled oscillation circuit (VCO) 58 controls the oscillation frequency based on the output signal of the low-pass filter circuit 56, and outputs the oscillation output signal S6 to the selection circuit 60 and the clock frequency dividing circuit 62.
To the horizontal direction counter circuit 64 via

As a result, the horizontal counter circuit 64
S6 is sequentially counted, and the count result S7 is compared with the phase comparison circuit 54.
Output to

At this time, based on the count data DV input via the load terminal, the horizontal direction counter circuit 64 starts the count result S7 when the count value reaches 910, thereby dividing the oscillation output signal S6 by 910. Voltage-controlled oscillation circuit so that the phase of S7 matches the horizontal synchronization signal HD
Control 58.

As a result, as shown in FIG.
, The luminance signal YH input through the selection circuit 46
(FIG. 7 (A)), during one horizontal scanning period, 91
An oscillation output signal S6 (FIG. 7 (B)) which rises to the 0 pulse can be obtained.

Further, the horizontal counter circuit 64 has a built-in comparison circuit, and obtains a comparison result between the count value of the oscillation output signal S6 and a predetermined set value, thereby obtaining 720 pulses from the end of the front porch of the luminance signal YH to the start of the back porch. The horizontal reference signal SHW whose signal level rises during the period
(C) of FIG.

Thereby, in the display device 1, when a small screen is generated for a high-definition television broadcast or a clear vision system video signal input via the selection circuit 46,
One horizontal scanning period of the video signal is divided into 910 and processed.

Further, at this time, in the display device 1, during one horizontal scanning period, the video signal is processed at a timing of 720 samples at which valid image information is obtained.
Thus, the video signal is efficiently processed.

The selection circuit 60 switches contacts based on a control signal SC6 output from the system control circuit, and generates an oscillation output that is input via a 1/2 frequency dividing circuit 66 when generating a small screen for an NTSC video signal. The signal S6 is output to the clock dividing circuit 62.

As a result, the PLL circuit 52 controls the voltage-controlled oscillation circuit 58 so that the 1/2 frequency-divided signal of the oscillation output signal S6 is phase-synchronized with the NTSC horizontal synchronization signal HD.

Thus, in the display device 1, for the NTSC video signal, one horizontal scanning period is similarly divided into 910, and the video signal is processed at a timing of 720 samples from which valid image information is obtained. It has been done.

Thus, in this embodiment, the oscillation output signal S6
Is used as a reference clock signal to control the writing operation of the image memory circuit 50.

In practice, in the high-definition television broadcasting and the clear vision system, the horizontal synchronization signal has a frequency of 33.75 each.
[KHz] and 31.48 [kHz], and the difference is as small as 7%.

Therefore, a clock signal synchronized with the horizontal synchronizing signal can be easily generated by using a common PLL circuit as in this embodiment.

Therefore, if one horizontal scanning period is divided into 910 and processed, the writing operation of the image memory circuit 50 can be controlled by using a common control circuit, and the entire configuration can be simplified.

On the other hand, in the horizontal synchronization signal of the NTSC system, the frequency is set to 15.75 [kHz], and by comparing the phases by interposing the 1/2 frequency dividing circuit 66 as in this embodiment, N
As for the video signal of the TSC system, a clock signal synchronized with the horizontal synchronizing signal can be generated with the same circuit configuration as that of the high-definition television broadcasting and the clear vision system.

Therefore, in this case, similarly, one horizontal scanning period is set to 910 in both cases.
If the processing is performed in a divided manner, the writing operation of the image memory circuit 50 can be controlled by using a common control circuit, thereby simplifying the entire configuration.

The clock divider circuit 62 outputs the oscillation output signal S6 to the image memory circuit 50 as a reference signal for writing, and
Reference signals 4CK, 2CK, 1CK and 1 / 2CK generated by sequentially dividing the oscillation output signal S6 by 1/2 are output to the image memory circuit 50.

Thereby, the image memory circuit 50 outputs the reference signals 4CK, 2CK,
When the write pulse signal WCK rises based on 1CK, 1 / 2CK, and S6, the luminance signal Y and the color difference signal Pb,
It is designed to take in Pr.

The vertical direction counter circuit 70 receives, via the counter circuit 72, the vertical synchronizing signal VD of the luminance signal YH and the color difference signals Pb and Pr input through the selection circuit 46.

Further, the vertical direction counter circuit 70
After being reset by VD, the count result S7 of the horizontal counter circuit 64 is sequentially counted.

Further, at this time, the vertical counter circuit 70 sets the reference data D of the value 263, the value 525 or the value 563 for the NTSC system, the high-definition television broadcast or the clear vision system, respectively.
V is loaded, and the count result S7 is sequentially counted in the range up to the reference data.

Thereby, the vertical counter circuit 70 sets the selection circuit 46 based on the count result S7 of the horizontal counter circuit 64 as a reference.
, The number of lines of the luminance signal and the color difference signal input through the CPU can be detected.

Further, the vertical direction counter circuit 70 has a built-in comparison circuit, and obtains a result of comparison between a predetermined reference value and the count value, thereby obtaining a luminance signal YH (not shown) input through the selection circuit 46 as shown in FIG. 8 (A) and a reference signal whose signal level rises in the effective display area of the color difference signal.

Further, based on the thinning rate setting data DMV output from the system control circuit, the vertical direction counter circuit 70 counts the count result S7 (eighth) during the period in which the reference signal rises.
A vertical reference signal SVW that rises at a predetermined cycle in synchronization with FIG.

That is, when a small picture is generated for an NTSC video signal, a vertical reference signal SVW that rises every two cycles is generated when the parent picture is the Vista Vision scheme transmitted in the clear vision scheme (FIG. 8 (C)). .

On the other hand, when the parent screen is a high-definition television broadcast or a normal clear vision system, a vertical reference signal SVW that rises for two periods every three periods is generated (FIG. 8 (D)).

Further, when generating a normal clear vision type child screen, when the parent screen is the Vista vision type transmitted in the clear vision type or the normal clear vision type,
While the vertical reference signal SVW rising every four periods is generated (FIG. 8E), when the main screen is a high-definition television broadcast, the vertical reference signal SVW rising every three periods is generated.
Is generated (FIG. 8 (F)).

On the other hand, when generating a sub-screen of high-definition television broadcasting, when the main screen is the Vista Vision system transmitted by the clear vision system, the vertical screen generates a vertical reference signal SVW that rises every four cycles, whereas the main screen is generated. For high-definition television broadcasting or normal clear vision, 3
A vertical reference signal SVW that rises every cycle is generated.

The AND circuit 74 includes a horizontal reference signal SHW and a vertical reference signal S
The logical product signal DA of VW is output to the write clock generating circuit 76.

Thus, the write clock generating circuit 76 obtains an AND signal DA (FIG. 7 (D)) whose signal level rises at the timing of 720 samples at which valid image information can be obtained for each line determined by the thinning rate setting data DMV. be able to.

The write clock generating circuit 76 generates a write pulse signal WCK that rises at a predetermined cycle in synchronization with the output signal DA of the AND circuit 74 based on the thinning rate setting data DMH output from the system control circuit.

That is, when a small picture is generated for a video signal of the NTSC system and the normal clear vision system, a write pulse signal WCK which rises every four periods is generated (FIG. 7 (E)).

On the other hand, when generating a sub-screen of high-definition television broadcasting, a write pulse signal that rises every three cycles
WCK is generated (FIG. 7 (F)).

The field discriminating circuit 78 generates a discriminating signal FWR for the even field and the odd field based on the vertical synchronization signal VD output from the counter circuit 72, and outputs the discriminating signal FWR to the timing arbitration circuit 80.

As a result, the timing arbitration circuit 80 outputs the even field and odd field discrimination signals FR obtained from the read side.
On the basis of D, read timing and write timing do not match in the same memory area,
The write operation of the image memory circuit 50 is arbitrated.

Accordingly, as shown in FIGS. 9 and 10, the picture-in-picture circuit 44 allocates a common sampling pulse of 910 samples in one horizontal scanning period, and among the 720 samples from which valid image information is obtained, The luminance signal and the color difference signal input via the selection circuit 44 are intermittently stored in the image memory circuit according to the video signals of the main screen and the sub-screen.
It is made to take in 50.

That is, a write pulse signal is generated every three or four cycles.
By starting WCK, the horizontal direction is 720
A video signal of 240 and 180 samples, respectively, of the sample can be captured.

On the other hand, every three or four cycles, the vertical reference signal SV
If W is raised, the number of scanning lines in the vertical direction can be reduced to 1/3 or 1/4 to take in a video signal.

As a result, the picture-in-picture circuit 44 reduces the horizontal and vertical scanning directions to 1/3 according to the compression ratio of 1/3 when forming a small screen of a high-definition television broadcast, thereby reducing the luminance signal and the color difference. It is designed to capture signals.

Further, at this time, if the parent screen is of the Vistaignon system, the parent screen is enlarged and displayed as shown in FIG.
Set to 1/4.

On the other hand, a clear vision type sub-screen consisting of display images with an aspect ratio of 4: 3 is equivalently enlarged 4/3 times in the horizontal direction when displayed,
The thinning rate in the horizontal direction is set to 3/4 times the reduction rate of 1/3 (that is, 1/4 thinning rate), and a child screen is generated.

Further, in the parent screen of the Vista Vision system, the thinning rate in the vertical direction is set to 1/4 corresponding to the enlargement processing.

Thus, in a display image having an aspect ratio of 4: 3, a small screen having a roundness of 1 can be formed with a simple configuration by forming a small screen by correcting the horizontal size at the time of writing.

That is, when the luminance signal and the color difference signal are fetched into the image memory circuit 50, they are fetched in a form converted into a small screen in advance in accordance with the main screen, so that when reading the small screen from the image memory circuit 50, they are synchronized with the main screen. The child screen can be superimposed only by reading it at the timing, and the overall configuration can be simplified accordingly.

Furthermore, when a video signal is taken into the image memory circuit 50, the processing speed on the writing side can be reduced by converting the picture signal into a small screen in advance and the whole configuration can be simplified.

Further, the configuration of the image memory circuit 50 can be reduced accordingly.

Further, at this time, the common sampling of 910 samples is assigned to one horizontal scanning period and the processing is performed, so that the processing on the writing side can be simplified accordingly.

The image memory circuit 50 is configured to be able to store video signals for up to four screens, and the satellite broadcast receiving circuit 4 and the UV broadcast receiving circuit 36 corresponding to the small screens correspondingly store the video signals.
Based on the control signal output from the system control circuit,
The receiving channel is switched at a predetermined cycle.

As a result, the image memory circuit 50 stores a plurality of child screens in response to user operations, and can superimpose a plurality of child screens as necessary.

As shown in FIG. 11, on the read side of the picture-in-picture circuit 44, as in the write side, the PLL circuit 82
Generates a clock signal.

That is, the PLL circuit 82 supplies the horizontal synchronization signal DHD synchronized with the main screen to the phase comparison circuit 84 composed of a three-state inverter circuit, and outputs the output signal of the phase comparison circuit 84 to the low-pass filter circuit (LPF) 85. I do.

The oscillation frequency of the voltage controlled oscillator (VCO) 86 is controlled based on the output signal of the low-pass filter circuit 85, and the oscillation output signal S8 is output to the horizontal counter circuit 89 via the clock frequency dividing circuit 88. .

This allows the horizontal counter circuit 89 to output the oscillation output signal
S8 is counted sequentially, and the count result S9 is compared with the phase comparison circuit 84.
And outputs it to the vertical counter circuit 90.

At this time, based on the count data DDV input via the load terminal, the horizontal direction counter circuit 89 counts the count result S9 when the count value becomes 910 as in the write side.
And thereby controls the voltage-controlled oscillation circuit 86 so that the phase of the count result S9 obtained by dividing the oscillation output signal S8 by 910 is phase-synchronized with the horizontal synchronization signal DHD.

As a result, on the read side, similarly to the write side, an oscillation output signal S8 that rises 910 pulses during one horizontal operation period is obtained, and the child screen is processed based on the oscillation output signal S8. ing.

At this time, the horizontal counter circuit 89 generates a reference signal for reading in the horizontal scanning direction based on the luminance signal and the color difference signal of the main screen.

That is, the horizontal direction counter circuit 89 obtains a comparison result between the count value of the oscillation output signal S8 and a predetermined reference value input from the system control circuit by using the built-in comparison circuit, and On the right end side, a window signal SHR whose signal level rises at the timing of superimposing in the horizontal scanning direction is output.

That is, for the high-definition television broadcasting, the normal clear vision system, and the NTSC system child screen, the signal level of the window signal SHR is raised during the period of 240, 180, and 180 samples at the left and right ends of the main screen, respectively (FIG. 9). ).

The vertical counter circuit 90 is reset by a vertical synchronizing signal DVD synchronized with the main screen, and then the horizontal counter circuit 9 is reset.
The count result S9 of 0 is sequentially counted.

Further, at this time, the vertical direction counter circuit 90 sets the reference data of the value 525 and the value 563 for the high-definition television broadcasting or the clear vision system according to the type of the main screen.
DV1 is loaded, and the count result S9 is sequentially counted up to the load value.

As a result, the vertical counter circuit 90
With reference to S9, the number of lines on the main screen can be detected.

Furthermore, the vertical direction counter circuit 90 uses a built-in comparison circuit to generate a predetermined reference value DV set by the system control circuit.
A comparison result of W and the count value is obtained, whereby during a period determined according to the type of the main screen and the sub-screen,
It generates a window signal SVR whose signal level rises at the upper and lower ends of the main screen.

That is, when the main screen is a high-definition television broadcast, the window signal SVR is displayed for a period of 160 lines at both the upper and lower ends of the main screen.
Rise signal level.

On the other hand, when the parent screen is a normal clear vision system and the child screen is a high-definition television broadcasting, NTSC system, the signal level of the window signal SVR rises during the period of 160 lines at the upper and lower ends of the main screen, When the main screen is a high-definition television broadcasting and the sub screen is a normal clear vision system, the signal level of the window signal SVR rises during a period of 120 lines at both upper and lower ends of the main screen.

Further, when the parent screen is the Vista Vision system transmitted by the clear vision system, the signal level of the window signal SVR rises during a period of 120 lines at both upper and lower ends of the main screen.

The AND circuit 92 reads out the logical product signal DR of the window signals SHR and SVR and outputs it to the clock generation circuit 93.

As a result, the read clock generation circuit 93 can obtain the logical product signal DR whose signal level rises at the timing of scanning the four corners of the main screen.

The read clock generation circuit 93 generates a read clock signal RCK that rises in synchronization with the oscillation output signal S8 during the period when the AND signal DR rises, and outputs the read clock signal RCK to the image memory circuit 50.

At this time, the read clock generation circuit 93 stops the output of the read clock signal RCK for a predetermined period based on the read position setting signal SS output from the system control circuit.

The clock divider circuit 88 outputs an oscillation output signal S8 to the image memory circuit 50 as a reference signal for reading, and
Reference signals 4CKr, 2CKr, and 1CKr generated by sequentially dividing the oscillation output signal S8 by 1/2 are output to the image memory circuit 50.

Based on the vertical synchronization signal DVD output from the vertical counter circuit 90, the field discrimination circuit 96 discriminates an even field and an odd field discrimination signal FRD for the main screen.
And outputs the determination signal FRD to the timing arbitration circuit 80.

As a result, the picture-in-picture circuit 44 allocates a sampling pulse of 910 samples in one horizontal scanning period to the parent screen as well as the child screen, and reads out the child screen based on the sampling pulse. I have.

The key signal generation circuit 95 outputs the key signal YS to the selection circuit 14 based on the window signals SHR and SVR and the readout position setting signal SS, thereby switching the contacts of the selection circuit 14 and superimposing the child screen. I do.

At this time, with respect to the child screen and the parent screen, a common sampling pulse of 910 samples is allocated to one horizontal traveling period, the child screen is generated based on the sampling pulse, and the generated child screen is generated based on the timing of the parent screen. By reading, the child screen can be superimposed with a simple configuration as a whole.

Further, at this time, a sub-screen is generated by thinning out the number of lines corresponding to the horizontal scanning direction, and then superimposed on the main screen based on a common sampling pulse to display a sub-screen having correct roundness. be able to.

That is, as shown in FIG. 12, when a high-definition television broadcasting sub-screen is displayed on the parent screen of the high-definition television broadcasting, a sub-screen is generated by compressing to 1/3 in both the vertical and horizontal scanning directions. After that, the child screen having the roundness of 1 can be displayed by reading out at the timing of the parent screen.

On the other hand, as shown in FIG. 13, when a normal clear vision type child screen is displayed on the main screen of a high-definition television broadcast, the horizontal direction and the vertical direction are respectively reduced by 1/3 while maintaining the aspect ratio of 4: 3. After the child screen is generated by compressing it to 4 and 1/3 and read out at the timing of the parent screen, a child screen with a roundness of 1 can be displayed.

Further, as shown in FIG. 14, when displaying a small screen of the NTSC system on the main screen of the high-definition television broadcast, the horizontal and vertical directions of the NTSC system display screen of the interlaced system are respectively reduced by 1/4 and 1/4. By compressing to 2/3 to generate a child screen and reading it at the timing of the parent screen,
For clear vision broadcasting with an aspect ratio of 4: 3, the horizontal and vertical directions can be compressed to 1/4 and 1/3, respectively, to generate a sub-screen in the same way as when a sub-screen is generated,
Thus, a child screen with a roundness of 1 can be displayed.

In this embodiment, when the display device 1 displays an NTSC small screen, the vertical direction counter circuit 70 switches the timing of generating the window signal SV to simultaneously display three small screens on the left end of the main screen. It is made to be able to do.

On the other hand, as shown in Fig. 15, when a small screen of a high-definition television broadcast is displayed on a main screen of a normal clear vision system, the horizontal and vertical directions are compressed to 1/4 and 1/3, respectively. After the child screen is formed, the child screen having the roundness of 1 can be displayed by reading the child screen at the timing of the parent screen.

Further, as shown in FIG. 16, when a normal clear vision type child screen is displayed on a normal clear vision type main screen, the horizontal direction and the vertical direction are changed to 1/4 and 1/1, respectively, while maintaining the aspect ratio of 4: 3. After generating the child screen by compressing it to 3, the child screen with the roundness of 1 can be displayed by reading it out at the timing of the parent screen.

Further, as shown in FIG.
By switching the timing of the generation of the window signal SV and switching and outputting the timing of the horizontal synchronizing signal in the clear vision processing circuit 30, a blank is formed at the left end of the main screen, and a child screen with a roundness of 1 is formed in the blank portion. Can be displayed.

On the other hand, as shown in FIG. 18, when displaying a sub-screen of the NTSC system on the main screen of the normal clear vision system,
For NTSC display screens of the interlaced type, a child screen with a roundness of 1 can be displayed by generating a child screen by compressing the horizontal and vertical directions to 1/4 and 2/3, respectively. .

Further, as shown in FIGS. 19 and 20, when displaying a high-definition television broadcast and a small screen of the NTSC system on the parent screen of the Vistavision system, a small screen was generated by compressing in the vertical and horizontal directions. Thereafter, by reading out at the timing of the parent screen, a child screen with a roundness of 1 can be displayed.

Further, at this time, the same color reproducibility can be obtained between the parent screen and the child screen by correcting the signal levels of the respective luminance signals and color difference signals according to the relations of equations (1) to (6). A display image without discomfort can be obtained.

(G2) Operation of Embodiment In the above configuration, the video signal of the high-definition television broadcast among the video signals received by the satellite broadcast receiving circuit 4 is demodulated by the demodulation circuit 6, and then the signal level correction circuit 8, The signal is output to the cathode ray tube 16 via the selection circuits 12 and 14 and the matrix circuit 10, and is displayed as a parent screen.

On the other hand, the video signal of the clear vision system is demodulated by the demodulation circuit 26 via the selection circuit 24, and then the signal level is corrected by the signal level correction circuit 28.

Further, after being processed by the clear vision processing circuit 30, the aspect ratio of the Vista Vision video signal is converted by the aspect ratio conversion circuit 32.

Thus, the clear vision system video signal received by the satellite broadcast receiving circuit 4 is supplied to the cathode ray tube 16 via the matrix circuit 10 and is displayed as a parent screen.

Similarly, the video signal received by the UV broadcast receiving circuit 36 is demodulated by the demodulation circuit 26 via the selection circuit 24,
The signal level is corrected by the signal level correction circuit 28, and the aspect ratio is converted by the aspect ratio conversion circuit 32 in the video signal of the Vista Vision system.

As a result, the clear vision and NTSC video signals received by the UV broadcast receiving circuit 36 are displayed as the main screen.

On the other hand, the video signals of the clear vision system and the NTSC system and the video signal of the high-definition television broadcast input through the video signal processing circuit 40 and the video tape recorder 42 are fetched through the selection circuit 12 and Displayed as a screen.

Further, the video signal received via the UV broadcast receiving circuit 36 and the satellite broadcast receiving circuit 4 is taken into the small screen creating circuit 44 via the selecting circuit 46, and a small screen is created.

At this time, in each video signal, one horizontal scanning period is 91
The image memory circuit 50 is divided into 0, and 720 samples from which valid image information is obtained are thinned out according to the compression ratio.
Is stored in

At this time, in the clear vision system video signal,
When displayed on the main screen, the thinning rate is corrected in advance by the amount that changes in the horizontal direction to form a sub-screen, whereby a sub-screen with a roundness of 1 can be formed with a simple configuration.

Correspondingly, in the vertical direction, the number of lines is thinned out according to the compression ratio and stored in the image memory circuit 50.

Thus, the video signals of the child screens stored in the image memory 50 are sequentially read out at the timing of the parent screen, whereby a child screen with a roundness of 1 can be displayed in the desired parent screen.

(G3) Effect of Embodiment According to the above configuration, one horizontal scanning period is divided into 910,
When generating a sub-screen by thinning out according to the compression ratio, the sub-screen is formed by correcting the thinning-out ratio for the clear vision system and NTSC video signals to form a sub-screen with a roundness of 1 with a simple configuration. Can be formed.

(G4) Other Embodiments In the above-described embodiment, the case where a small screen with a compression ratio of 1/3 was formed was described. However, the present invention is not limited to this, and various compression ratios may be set as necessary. It can be widely applied when forming a screen.

H Effects of the Invention As described above, according to the present invention, when forming a sub-screen for a video signal having an aspect ratio of 4: 3, in the horizontal direction, when forming a sub-screen for a video signal having an aspect ratio of 16: 9, After sampling with the same sampling number, by thinning out the video signal with an aspect ratio of 16: 9 at a thinning rate of 3/4 times when forming a child screen,
A sub-screen with a roundness of 1 can be formed in the same manner as when a sub-screen is formed for a video signal having an aspect ratio of 16: 9, and the overall configuration can be simplified accordingly.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a display device according to an embodiment of the present invention, FIGS. 2 to 5 are schematic diagrams showing display images thereof, and FIG. 6 shows a writing side of a picture-in picture circuit. Block diagrams, FIGS. 7 and 8 are signal waveform diagrams for explaining the operation, FIGS. 9 and 10 are charts showing thinning rates,
FIG. 11 is a block diagram showing the read side of the picture-in picture circuit, and FIGS. 12 to 20 are schematic diagrams showing the child screens. 1 display device 44 picture-in-picture circuit 5
2, 82: PLL circuit, 50: Image memory circuit.

Claims (1)

(57) [Claims] 1. A main screen of a video signal having an aspect ratio of 16: 9 or 4: 3 and an aspect ratio of 16: 9.
Or in a display device that switches the video signal of aspect ratio 4: 3 to form a sub-screen and displays the sub-screen in the main screen, for the video signal of the aspect ratio 16: 9, in the horizontal scanning direction, After sampling the video signal having the aspect ratio of 16: 9 at a predetermined sampling number, the video signal of the aspect ratio of 16: 9 is thinned out at the thinning rate determined by the compression rate of the small screen, and the line of the video signal having the aspect ratio of 16: 9 is obtained. Is thinned out according to the compression ratio to form the sub-screen.For the video signal having the aspect ratio of 4: 3, the video signal having the aspect ratio of 4: 3 is sampled at the sampling number in the horizontal scanning direction. After that, the above thinning rate
The sub-screen is formed by thinning at a thinning rate of 3/4 and thinning the video signal lines having the aspect ratio of 4: 3 in the vertical scanning direction according to the compression ratio. Display device.