JP2539919B2 - HDTV receiver time axis compression device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a high-vision receiver configured to display a reproduced image of an NTSC television signal converted into progressive scanning on a high-resolution display. More specifically, the present invention relates to a time axis compression device including a circuit for time axis compression so that the linearity of a reproduced image does not change by digital processing.

[Prior Art] A reproduced image of an NTSC television signal converted into progressive scanning (hereinafter referred to as an NTSC signal) has a frame frequency of 59.94 Hz and a horizontal frequency of 31.47 KHz.

On the other hand, the high frequency signal has a field frequency of 60H.
z, horizontal frequency is 33.75KHz. Therefore, the vertical and horizontal frequencies of the NTSC signal and the high-vision signal are very close to each other, so that the NTSC signal can be displayed on the high-vision display. At this time, the ratio of the vertical blanking period to one frame period of the display for NTSC and the display for high-vision is defined to be exactly the same value, so that there is no problem in vertical display.

However, while the aspect ratio of NTSC signals is 4: 3, the aspect ratio of high-vision signals is 16: 9,
The ratio of the horizontal blanking period to one horizontal scanning period of the display for NTSC and the display for high-vision is about 5: 4. Therefore, if the ratio in the vertical direction is kept constant and the ratio of the number of unit pixels of the NTSC signal and the high-vision signal in one horizontal scanning period is calculated from these values,
It will be about 4: 5.

That is, in order to display the NTSC signal on the display for high-vision while maintaining its linearity, it must be compressed about 4/5 times in the horizontal direction. In this way, when compressing in the horizontal direction about 4/5 times, a method of changing the horizontal deflection current of the high-vision display and compressing to about 4/5 times is conceivable.

FIG. 4 is a block diagram showing a configuration of a time axis compression device of a conventional high-vision receiver. In FIG.
Is an NTSC signal input terminal, (2) is an A / D converter that receives an NTSC signal that arrives at the input terminal (1) and converts it into a digital signal, and (3) is the A / D converter (2 ). A synchronization / timing pulse generation circuit that generates a clock and a timing pulse using the output signal of
The output signals of the D converter (2) and the synchronization / timing pulse generation circuit (3) are input, and the output signal of the A / D converter (2) is digitally processed to separate luminance signal color signals and progressive scan conversion. ID to output RGB signal
ROVED DEFINITION) TV decoder.

(6) to (8) are D / A converters to which the output of the IDTV decoder (4) is input, and (9) are the D / A converters (6) to
A video circuit having the output of (8) as an input; (10) a synchronization circuit having the output of the synchronization / timing pulse generation circuit (3) as an input and separating a horizontal synchronization signal and a vertical synchronization signal;
(11) is a deflection circuit that receives the outputs of the synchronization / timing pulse generation circuit (3) and the synchronization circuit (10) as input, determines and outputs horizontal deflection current and vertical deflection current, and (12) is the video circuit (9). ) Output and the output of the deflection circuit (11) as input.

 Next, the operation of the above configuration will be described.

The analog NTSC signal that arrives at the input terminal (1) is A /
It is input to the D converter (2) and converted into a digital amount of NTSC signal. The output signal of the A / D converter (2) is input to the synchronization / timing pulse generation circuit (3) and the IDTV decoder (4).

The synchronization / timing pulse generation circuit (3) generates a clock synchronized with the output signal of the A / D converter (2),
A signal indicating that a clock and various timing pulses are output to the IDTV decoder (4) and at the same time a synchronization signal is received by the synchronization circuit (10) and an NTSC signal is received by the deflection circuit (11) (hereinafter referred to as NTSC determination signal). ) Are output respectively.

On the other hand, the IDTV decoder (4) digitally processes the output signal of the A / D converter (2) to perform luminance signal color signal separation and progressive scan conversion, and the frame frequency is 59.94H.
z, 525 scanning lines, and progressive scanning RGB signals are output to the D / A converters (6) to (8) in the next stage. At this time, IDTV
The digital processing of the decoder (4) is controlled by the clock output from the synchronization / timing pulse generation circuit (3).

Next, each of the D / A converters (6) to (8) converts the digital amount of input into an analog amount of signal, and then amplifies the analog amount of signal in the video circuit (9),
Output to high-vision display (12).

The synchronization circuit (10) separates the horizontal synchronization signal and the vertical synchronization signal from the synchronization signal output from the synchronization / timing pulse generation circuit (3) and outputs the horizontal synchronization signal and the vertical synchronization signal to the deflection circuit (11). The deflection circuit (11) determines a horizontal deflection current and a vertical deflection current from the output of the synchronization circuit (10) and outputs them to the high-vision display (12).

As described above, when the input of the video circuit (9) is the output of the D / A converters (6) to (8), the output of the deflection circuit (11) is input to the high-definition signal of the video circuit (9). If it remains matched with the vertical direction, the information is 4/5 in the horizontal direction with respect to the vertical direction, so the image stretched 5/4 times in the horizontal direction becomes the high-vision display (12). Is displayed. Therefore, in this case, in order to display the output of the video circuit (9) on the high-vision display (12) while maintaining the linearity, the horizontal deflection current of the output of the deflection circuit (11) is changed to change the high-vision display. (12)
It is necessary to compress the display of by 4/5 times in the horizontal direction.

FIG. 5 is a diagram showing the relationship between the video signal and the horizontal deflection current. FIG. 5 (a) shows the case where the input of the video circuit (9) is a high-vision signal, and FIG. 5 (b) shows the video circuit (9). The case where the input is the output of the D / A converters (6) to (8) is shown. Fifth
In the figure (b), the value of the horizontal deflection current is made smaller than that in the case of the figure 5 (a), and the display on the high-vision display (12) is compressed 4/5 times in the horizontal direction.

FIG. 6 is a diagram showing a display on the high-vision display (12). In the case of FIG. 5 (a), it becomes as shown in FIG. 6 (a), and in the case of FIG. 5 (b). Fig. 6 (b)
It becomes as shown in. The shaded portion in FIG. 6B is the blanking level.

The horizontal deflection current output from the deflection circuit (11) is switched by the NTSC determination signal output from the synchronization / timing pulse generation circuit (3).
High-vision display (12) is a high-vision signal and
The NTSC signal can be displayed while maintaining the correct linearity.

[Problems to be Solved by the Invention] Since the conventional time axis compression device for the high-vision receiver is configured as described above, the deflection circuit is operated by the NTSC determination signal in order to perform time compression in the horizontal direction. The horizontal deflection current has to be switched, the configuration of the deflection circuit becomes complicated, and the color deviation of the high-vision display must be adjusted in accordance with two deflection widths.

The present invention has been made to solve the above problems, and it is an object of the present invention to provide a time axis compression device for a high-vision receiver capable of time axis compression in the horizontal direction without switching the horizontal deflection current. To aim.

[Means for Solving the Problems] A time base compression apparatus for a high definition receiver according to the present invention is an A / D conversion means for converting an NTSC composite television signal into a digital amount signal, and this A / D conversion. A synchronization / timing pulse generation means for generating a clock and a timing pulse from the output signal of the means, the output signal of the A / D conversion means and the output signal of the synchronization / timing pulse generation means are input, and the A / D conversion is performed. An IDTV decoder for converting the composite television signal of the NTSC system to a signal for progressive scanning of digital amount, and a time axis compression means for horizontally compressing the output signal of the digital amount of the IDTV decoder in the horizontal direction, The time axis compression means is a line memory that receives the output signal of the IDTV decoder, and
Using the output signal of the timing pulse generating means, the line memory is composed of a horizontal synchronizing means for outputting a control signal for horizontally compressing the output signal of the IDTV decoder in the horizontal direction. The output signal of the timing pulse generating means is used to reset every horizontal scanning period.

[Operation] According to the present invention, an A / D conversion means for converting a composite television signal of the NTSC system into a digital signal, and the A / D conversion means
A synchronization / timing pulse generating means for generating a clock and a timing pulse from the output signal of the A / D converting means, the output signal of the A / D converting means and the output signal of the synchronizing / timing pulse generating means are input, and the A / D converted N
It is equipped with an IDTV decoder that converts a TSC composite television signal into a digital progressive scan signal and a time axis compression means that horizontally compresses the digital output signal of this IDTV decoder in the horizontal direction. The axial compression means is
Using the line memory that receives the output signal of the IDTV decoder and the output signal of the synchronization / timing pulse generation means, output a control signal that horizontally compresses the output signal of the IDTV decoder to the line memory in the horizontal direction. The horizontal synchronizing means for resetting the horizontal synchronizing means is reset every horizontal scanning period by using the output signal of the synchronizing / timing pulse generating means.
The decoder and the time axis compression means can be synchronized with each other, and the horizontal position at power-on can be fixed.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a time axis compression device of a high-vision receiver according to an embodiment of the present invention. In FIG. 1, (1) to (4) and (6) to (12) are the fourth. Since it is the same as the conventional example shown in the figure, the same reference numerals are given to corresponding portions, and detailed description thereof will be omitted.

In FIG. 1, (5) is a time axis compression circuit, which receives the output of the IDTV decoder (4) and the output of the synchronization / timing pulse generation circuit (3) as input, and outputs the RGB output signal approximately 4/5 times in the horizontal direction. Compress the time axis.

FIG. 2 is a block diagram showing a concrete example of the configuration of the time axis compression circuit (5), in which the RGB output signals from the IDTV decoder (4) are respectively inputted and the horizontal direction is approximately 4/5 times. Line memory (13), (14), (15)
And a horizontal synchronizing circuit (16) for controlling the operations of these line memories (13), (14) and (15).

FIG. 3 is a block diagram showing a concrete configuration of the horizontal synchronizing circuit (16), which shows two horizontal counters (17), (2
1), a phase comparator (18), a loop filter (19) and a voltage controlled oscillator (hereinafter referred to as VCO) (20).

 Next, the operation of the above configuration will be described.

The analog NTSC signal that arrives at the input terminal (1) is A /
It is input to the D converter (2) and converted into a digital amount of NTSC signal. The output of the A / D converter (2) is input to the synchronization / timing pulse generation circuit (3) and the IDTV decoder (4).

The synchronization / timing pulse generation circuit (3) generates a clock synchronized with the output signal of the A / D converter (2),
Clocks and various timing pulses are output to the IDTV decoder (4) and the time axis compression circuit (5), and at the same time, a synchronization signal is output to the synchronization circuit (10).

Next, the IDTV decoder (4) is the above A / D converter (2)
The output of is digitally processed, the luminance signal and the color signal are separated and the sequential scanning conversion is performed, and the frame frequency is 59.94Hz,
An RGB signal of 525 scanning lines and progressive scanning is output to the time axis compression circuit (5) at the next stage. At this time, IDTV decoder (4)
Is controlled by the output clock of the synchronization / timing pulse generation circuit (3).

Then, the time axis compression circuit (5) horizontally compresses the RGB signal output from the IDTV decoder (4) by about 4/5 times by digital processing. The time axis compression operation will be described in more detail below.

The RGB outputs of the IDTV decoder (4) are input to the line memories (13), (14), (15) and compressed on the time axis. At this time, the operation control of each line memory (13) to (15) is performed by the output of the horizontal synchronizing circuit (16). That is, the clock (WCK) output from the synchronization / timing pulse generation circuit (3) is the IDTV decoder (4).
Horizontal synchronization is performed at the same frequency as the transmission rate of the output data of, and the horizontal counter (17) counts the clock (WCK).

The horizontal counter (21) counts the output clock (RCK) of the VCO (20). These Horizontal Counters (17)
The number of samples for one horizontal scanning period is set in advance in (21) and (21), and the set value of the horizontal counter (17) is 4/5 times the set value of the horizontal counter (21).

Next, the outputs of both horizontal counters (17) and (21) are input to the phase comparator (18) and the phases are compared every horizontal scanning period. The output of the phase comparator (18) is integrated by the loop filter (19) and becomes the control voltage of the VCO (20). As described above, when the loop of the horizontal synchronization circuit (16) becomes stable, a clock horizontally synchronized with the output of the VCO (20) can obtain a clock whose frequency is 5/4 times that of the clock of the horizontal counter (17). To be Therefore, the write clock (WCK) of each line memory (13), (14), (15)
, And a reset pulse (WRT) obtained from the horizontal counter (17) is used for reset.

Similarly, the above line memories (13), (14), (15)
The read clock (RCK) is used, and the reset pulse (RRT) obtained from the horizontal counter (21) is used for reset. Further, in order to determine the horizontal position when the power is turned on, the horizontal counter (17) is reset by the horizontal timing pulse (HD) output from the synchronization / timing pulse generation circuit (3). Therefore, the output of the IDTV decoder (4) is (RCK) of each line memory (13), (14), (15).
Is horizontally synchronized with (WCK), and (RCK) is 5/4 of (WCK)
Since the frequency is doubled, the time axis is horizontally compressed to 4/5 times.

As described above, the time-axis compressed output of the time-axis compression circuit (5) is input to the D / A converters (6) to (8) and converted into an analog signal, and then the video circuit ( It is input to 9), amplified here, and sent to the high-vision display (12).

The synchronization signal output from the synchronization / timing pulse generation circuit (3) is input to the synchronization circuit (10),
Deflection circuit (1
1) sent to. The deflection circuit (11) is the synchronization circuit (1
The horizontal deflection current and the vertical deflection current are determined from the output of 0) and output to the high-vision display (12). Here, the horizontal deflection current of the output of the deflection circuit (11) is adjusted to the horizontal deflection width of the high-vision signal, and the high-vision display (12) outputs the output signal of the video circuit (9) to the output of the deflection circuit (11). Display according to current.

[Effects of the Invention] As described above, according to the time base compression device for a high-vision receiver according to the present invention, an A / D conversion means for converting an NTSC composite television signal into a digital amount signal, A synchronization / timing pulse generation means for generating a clock and a timing pulse from the output signal of the A / D conversion means, the output signal of the A / D conversion means and the output signal of the synchronization / timing pulse generation means are input, and the above A /
An IDTV decoder for converting the D-converted composite TV signal of the NTSC system into a digital progressive scan signal, and a time axis compression means for horizontally compressing the output signal of this IDTV decoder in the horizontal direction. The time-axis compression means includes a line memory that receives the output signal of the IDTV decoder and an output signal of the synchronization / timing pulse generation means, and outputs the output signal of the IDTV decoder to the line memory in the horizontal direction. And a horizontal synchronizing means for outputting a control signal for time-axis compression. The horizontal synchronizing means is reset every horizontal scanning period by using the output signal of the synchronizing / timing pulse generating means. The IDTV decoder and the time axis compression means can be synchronized with each other, and the horizontal position at power-on can be determined. You.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a time axis compression device of a high-vision receiver according to an embodiment of the present invention, FIG. 2 is a block diagram showing a specific configuration of the time axis compression circuit, and FIG. 3 is a horizontal synchronization circuit. FIG. 4 is a block diagram showing a concrete configuration of the above, FIG. 4 is a block diagram showing a configuration of a time axis compression device of a conventional high-vision receiver, and FIG. 5 is a relationship between a video signal and a horizontal deflection current of the conventional time axis compression device. FIG. 6 is a diagram showing a display on the high-vision display. (1) …… NTSC signal input terminal, (2) …… A / D converter, (3) …… Synchronization / timing pulse generation circuit,
(4) …… IDTV decoder, (5) …… Time axis compression circuit,
(6), (7), (8) ... D / A converter, (9) ... video circuit, (10) ... synchronization circuit, (11) ... deflection circuit,
(12) …… High-vision display. The same reference numerals in the drawings indicate the same or corresponding parts.

Claims (1)

(57) [Claims] 1. An A / D converting means for converting an NTSC composite television signal into a digital amount signal, and a synchronizing / timing pulse generating means for generating a clock and a timing pulse from an output signal of the A / D converting means. , And the output signal of the A / D conversion means and the output signal of the synchronization / timing pulse generation means are input, and the A / D-converted composite NTSC system television signal is converted into a digital progressive scan signal. The IDTV decoder for conversion and the time axis compression means for horizontally compressing the output signal of the digital amount of the IDTV decoder are provided. The time axis compression means is a line to which the output signal of the IDTV decoder is input. Control for horizontally compressing the output signal of the IDTV decoder in the line memory by using the output signal of the memory and the synchronization / timing pulse generation means. A horizontal synchronizing means for outputting a signal, and the horizontal synchronizing means is reset every horizontal scanning period by using the output signal of the synchronizing / timing pulse generating means. apparatus.