JPH0698276A - Scroll controller - Google Patents

Abstract

PURPOSE:To provide a stable scroll operation in a zoom display mode in field double speed display and to perform scroll processing so as to set the positions of an image on the upper and lower sides in the zoom display mode appropriately. CONSTITUTION:A field double speed processing timing controller 41 which supplies a control signal required for the processing of a field double speed processing means provided with field memory 12, 22, and 23 to which an input video signal is supplied is provided at the field double speed processing means, and a display video to which field double speed is applied is scrolled upward and downward by shifting a VSYNC (SHIFTED) which supplies a vertical synchronizing signal VSYNC in the input video signal before processing to the controller by shifting for a prescribed time and also, shifting a readout start address RHINC in the control signal required for the processing. Also, the controller is composed so that a video display part can be displayed at appropriate upper and lower positions based on the data of the blank part of the video signal detected at a blank detection circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scroll control device such as a television receiver, for example, in an HDTV (high definition television) receiver having a CRT corresponding to an aspect ratio of 16: 9. The present invention relates to a vertical scroll control device for a video display position when displaying a video by an NTSC television signal.

[0002]

2. Description of the Related Art For example, in an HDTV (high-definition television) set, as one method of achieving compatibility with 4: 3 current NTSC system TV broadcasting, a horizontal scanning frequency of HDTV is set to a horizontal scanning frequency by field double speed processing. There is a method of making the value close to the frequency and sharing the CRT deflection circuit with the HDTV. In this case, as a video display mode on the screen, as shown in FIG. 2, a "full display mode" in which the width is widened to fill the screen with an aspect ratio of 16: 9.
A, a "normal display mode" in which a non-display part is provided on the left and right to display at an aspect ratio of 4: 3, and a "zoom display mode" in which the image is enlarged to the full width of the screen and the upper and lower parts of the image are cut off C or the like is adopted.

For example, when the software recorded by the current NTSC system of 4: 3 is displayed in the "normal display mode" on the screen of 16: 9 aspect ratio,
As shown in FIG. 19A, there are left and right portions where no image is displayed (hereinafter referred to as blank portions). For this reason, when software recorded in the current NTSC system of 4: 3 in Vista size or Cinemascope size is displayed in the "normal display mode",
As shown in FIG. 19B, not only the left and right sides but also the blank portions are formed above and below. Therefore, by using the "zoom display mode" described above, the image is enlarged as shown in FIG. 19C, the left and right widths of the image are fully filled, and the upper and lower partial images are overscanned to display the CRT image. The display screen can be used effectively.

By the way, in the zoom display mode of the above-mentioned display modes, the video display position on the screen is scrolled up and down so that the display portion of the video can be selected. For example, as shown in D and E of FIG. 2, it is possible to display the image display position from the center C, such as a zoom position down D for scrolling down and displaying, or a zoom position up E for scrolling up and displaying. Be seen.

An example of using such a scroll function is shown. The width of the upper and lower blank portions in the software recorded in the Vista size or the cinemascope size, that is, the upper and lower display positions of the image is actually different for each software. Is quite different to. Therefore, FIG.
As shown in Fig. 20, the software whose image is on the upper side (the width of the upper blank part is narrower than that of the lower blank part) is displayed on the screen with the aspect ratio of 16: 9 in Fig. 20 (b).
As shown in FIG.
As shown in (c), when the image is displayed in the "zoom display mode" as it is, the image is biased to the upper side and the blank portion is displayed on the lower side. Further, as shown in FIG. 20 (d), the software in which the image is displayed at the bottom (the width of the lower blank portion is narrower than that of the upper blank portion) is set in the "normal display mode" as shown in FIG. 20 (e). Therefore, if the image is displayed in the "zoom display mode" as it is as shown in FIG.
The image is biased to the lower side and the blank portion is displayed on the upper side. Furthermore, when the image is displayed in the state as shown in FIG. 19C in the “zoom display mode”, there is a problem that the subtitle exists in the overscan portion below the image and the subtitle is not displayed on the screen.

Therefore, utilizing this scroll function,
When the image is biased to the upper or lower as shown in FIGS. 20 (c) and 20 (f), the user uses the scroll function to move the image in the vertical direction while looking at the screen. As shown in FIG. 20 (g), it is possible to make adjustment so that the top and bottom of the image are not biased. Also, when it is desired to display a subtitle hidden in the overscan portion at the bottom of the image, the scroll function is used to adjust the subtitle to be displayed by scrolling upward as shown in FIG. be able to. Alternatively, although the scroll function is not used, the image enlargement ratio is variably set continuously or stepwise within the range of the "normal display mode" and the "zoom display mode", as shown in FIG. As described above, it is also known to make adjustment so that only the blank portions above and below the image are not displayed on the screen, which allows the subtitles and the like below the image to be displayed.

In order to perform the scrolling as described above, as shown on the side of the display screen in FIG. 2, for example, a deflection system of a CRT display as a video display means is used with respect to the original vertical synchronizing signal VSYNC. Give V
It is necessary to move SYNC around in time.

In the prior art, (1) a method of moving the video signal itself by moving the read start address of the video signal from the field memory used in the field double speed processing, (2) the original before the field double speed processing The method of moving the V sync signal of (1) back and forth in the countdown type synchronous reproduction circuit to realize the vertical scrolling operation of the video display position, (3) V sync after the field double speed processing is performed in the countdown type synchronous reproduction circuit. Three types of methods have been considered, namely, a method of moving to, and a vertical scrolling operation of the video display position.

[0009]

[Problems to be Solved by the Invention] However, the above 3
Each method has the following problems. In method (1), as the video display position scrolls up and down as shown in FIG. 3, in principle, in the memory for one field, overtaking occurs between the write and read timings, and scroll down (video Top display) sometimes 1
The image ahead of the field appears on the upper part of the screen (b in the same figure), and when scrolling up (displaying the lower part of the image), the image one field before appears on the lower part of the screen (c). As long as this method is used, two fields of memory are needed to avoid overtaking.

In the method (2), the problem of overtaking does not occur, but since the system clock required for digital processing is generated by using the PLL from the input synchronizing signal, the image display position is changed vertically as shown in FIG. As the image is being read, the unstable clock region generated in the original V blanking interval overlaps with the read image region, the lower part of the image becomes unstable when scrolling up (a and b in the same figure), and when scrolling down. There is a problem that the upper part becomes unstable. That is, although the field double speed processing is performed with reference to the shifted V synchronization, the unstable position of the system clock remains at the original position.
When scrolling up, a double-speed image section that is output is affected and the lower part of the displayed image is affected and becomes unstable in every alternate field. Therefore, the lower part of the image is reproduced as a double image of a stable field and an unstable field as shown in FIG. Similarly, when scrolling down, the upper part of the display image is similarly affected and becomes unstable every other field.

In the method (3), the increase of the unstable region at the upper part of the image due to the two-stage PLL in the normal display,
It always remains because the VSYNC position cannot be moved when writing, and especially tape playback with poor SKEW characteristics (8 mm
Etc.) and becomes a big problem.

There is also a problem in that the user has to adjust the scroll and zoom magnifications each time he or she wants to view different software, which complicates the adjustment.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above problems in the prior art and to realize a stable scrolling operation and a good zoom display without increasing the memory. It is another object of the present invention to automatically display an image at an appropriate vertical position and an appropriate enlargement ratio without the user having to adjust the scroll or zoom.

[0014]

A scroll control device for double-speed field display according to the present invention supplies a control signal required for double-speed field processing to field double-speed processing means having a field memory to which an input video signal is supplied. A field double speed processing timing controller is provided, and the vertical synchronization signal in the input video signal before the field double speed processing is shifted for a predetermined time and supplied to the field double speed processing timing controller, and reading out of the control signal necessary for the field double speed processing is started. By shifting the address by a predetermined value, the video displayed on the screen of the video display means for the field double speed display is scrolled up and down. Furthermore, an aspect conversion means for converting the aspect ratio of the video displayed on the screen of the video display means and blanking the non-display area is provided, and the video display means positions the non-display area outside the screen. Overscanned.

The target scroll control amount is divided into about half and half for the vertical synchronizing signal shift and the read start address shift. As a means for this, the shift amount of the read address is set by the digital value consisting of the upper digit excluding the LSB of the digital set value of the scroll control amount, and the shift amount of the vertical synchronizing signal is set by the digital value obtained by adding the LSB to the digital value. A control register for setting is provided. Also, the scroll control device in the double-speed display of the field is HDTV / NTSC.
When applied to a television receiver, a scrolling operation is possible in which an unstable portion of an image is not displayed in the zoom display mode.

Further, a blank detection circuit for detecting an interval between upper and lower blank portions which are non-video display portions in the display image based on the input video signal and horizontal and vertical synchronizing signals, and a vertical position of the display image are detected. Based on the variable scroll processing unit and the information detected by the blank detection circuit, the vertical position with respect to the display screen is calculated for the video display portion of the display image, and based on the calculated result, the display screen The scroll control device is configured to include a control unit capable of outputting a control signal for matching the upper and lower center positions and the upper and lower center positions of the video display portion to the scroll processing unit, and an aspect ratio of 16: 9. It was decided to mount it on a television receiver having a display screen corresponding to.

Further, in the zoom mode in which the zoom processing section for performing the video signal processing capable of changing the magnification of the display image stepwise or continuously and displaying it on the display screen is operable, the control section is provided. Calculates the vertical position and size of the video display portion with respect to the display screen based on the information detected by the blank detection circuit, and based on these calculation results, the vertical and / or left and right blank portions are displayed on the display screen. A control signal for varying the enlargement ratio of the display image is output to the zoom processing unit so that the display image is out of the range, and based on the calculated vertical position with respect to the display screen, the center at the top and bottom of the display screen is displayed. A control signal for matching the position and the center position above and below the image display portion can be output to the scroll processing unit. Configure the roll control device, the aspect ratio of 16: was be mounted on a television receiver having a display screen corresponding to 9.

[0018]

According to this structure, the scroll control amount is divided into the shift of the read start address and the shift of the vertical synchronizing position of the input video signal in the field double speed process, whereby the respective shift amounts can be reduced. It is possible to prevent the video overtaking phenomenon caused by the shift of the read start address and the unstable area of the video caused by the shift of the vertical synchronization position from entering the video display area, and a stable scroll operation can be performed.

Further, each section of the upper and lower blank portions is detected from the video signal, and the vertical position of the image is calculated based on the detected data. Then, according to the calculated data, the scroll control and the zoom control can be performed so that the vertical position and the enlargement ratio of the display image are optimal.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As an embodiment of the present invention, an example applied to a current HDTV set capable of receiving an NTSC television signal will be described below. Figure 1
Is a block diagram showing a basic configuration of an HDTV set, and its configuration will be described together with operations. BS, UH
When various broadcasts such as F, VHF, and CATV are received by the tuner 1 and the current broadcast is selected, SW1 is selected between the external VIDEO input and Y in the video signal processing (1) circuit 2. Each processing such as / C separation, chroma decoding, and sync separation is performed, and the luminance + color difference signals (Y, RY,
(B-Y) and a synchronizing signal in the form of a field double speed and aspect converter 3. Here, processing such as field double speed, scroll at the time of zooming, aspect conversion, etc. is performed, and the video signal and the sync signal, which have become double speed, are respectively SW4
Is input to the video signal processing (2) circuit 4 and the deflection processing circuit 6 via SW5. In the video signal processing (2) circuit 4, the luminance + color difference signal is converted into RGB and amplified, and the output is supplied to the CRT 7. The deflection processing circuit 6 generates a deflection waveform from the synchronization signal and supplies it to the deflection yoke DY of the CRT 7.

When the HD signal is selected,
The output of the tuner 1 is input to the decoder 5 by the SW3 when the broadcast is received, and is directly input when the external input is made. Here, after being converted into a baseband signal and selected by SW2 between the baseband signal and an external input, a video signal and a sync signal are respectively selected by SW4 and SW5. As a method of the decoder 5, the MUSE method can be mentioned here, but all the methods that will be realized as HD standards in the future will be targeted. Further, the same applies to the current broadcasting, and the NTSC will be described here as an example, but the present invention can also cover all other standards and standards to be realized in the future.

The scroll control device according to the present embodiment is realized by the field double speed and aspect conversion section 3 described above, and FIG. 5 shows its internal structure in a block diagram. Hereinafter, with respect to the field double speed including the scroll control operation according to the present invention and the processing operation of the aspect conversion unit 3, two examples of the example 1: + 30H scroll (upward almost maximum value) and the example 2: -30H scroll (downward almost maximum value) will be described. A case will be described as an example. It should be noted that the video signal is in the 3ch component signal format of Y, RY, and BY, but the description will be given here using Ych, and description of the other channels is the same, and therefore will be omitted. 6A shows the internal structure of the field memory 12, and FIG. 6B shows the operation of the internal pointer.

(1) Processing on Writing Side The video signal passes through the LPF 10, is converted into a digital signal by the A / D converter 11, and is written in the FieldMemory 12. This operation is performed by the field double speed processing timing controller (FieldDoublerTimingController) 41, and WCK, WVCLR, WHCLR and countdown & scroll control (Countdown & Scroll control) part 4
Controlled by the WHINC signal generated by 3, the video signal is stored at a predetermined address in the memory according to the scroll condition.

The meanings of the signals used in the write control are as follows. WCK-Write system clock. In this example, 8 fsc ≈ 14.32 MH _Z. Sampling frequency of A / D.
The internal write address pointer is incremented in synchronization with this rising. WVCLR-Field memory V period address clear pulse. When this is H, the internal write address pointer becomes address 0 at the rise of WCK. WHCLR-field memory H cycle address clear pulse. When this is H, the internal write address pointer becomes the start address of the line unit at that time at the rise of WCK. WHINC-Field memory line address increment pulse. When this is H, the internal write address pointer becomes the address of the next line at the rising edge of WCK. In this embodiment, WHINC is the same signal as WHCLR.

At this time, first, the Coun of the aspect conversion unit
In the tdown & Scroll control part 43, shift by an amount corresponding to half of the scroll amount for the purpose of the original V synchronization and input to the FieldDoublerTimingController 41 (the remaining half scroll operation is realized by the read side operation as described later). To). That is, in Example 1, the shift is performed 15H behind, and in Example 2, the shift is performed 15H before. By this method, the unstable area on the writing side as shown in FIG. 4a does not enter the display area but is driven into the non-display area as shown in FIG. 7a. FieldDoublerTimingController
Reference numeral 41 creates all the signals to be supplied to the FieldMemory 12 based on this shifted V synchronization timing. FIG. 6B shows the relationship between each control pulse and the operation of the write address pointer (WriteAddrPointer) 51 and the read address pointer (ReadAddrPointer) 52 at that time, and FIG. 8A shows the timing of each pulse on the write side. ing. Here, WHCLR and WHIN
C is the same, and data is stored in the memory in order from address 0 of the cell. In Example 1, since the WVCLR pulse is output at a position delayed by 15H from the phase of the original V sync, the image shifted to 15H is captured in the memory as shown in FIG. 8b. The remaining 15H of scrolling is realized by the processing on the reading side. Example 2 is 1 as well
The video is shifted down by 5H, and the rest is processed on the reading side.

(2) Processing on the reading side Next, the start address (line address) at the time of reading the memory is advanced to further scroll the display screen. Since the amount of advance of the start address is halved even when scrolling up, the overtaking area can be driven into the non-display area as compared with FIG. 3c. That is, in order to realize the scroll operation in the V direction, the V sync of the input video signal is first shifted (delayed) as shown in FIG. 7A, and then the field double speed processing is performed, as shown in FIG. 7B. At that time, by starting the address from which the read start address from the memory is advanced (first), both the problematic occurrence of the unstable area and the occurrence of the overtaking area are offset, and stable scrolling operation is realized. It Thus, the scroll amount at this time is the V-synchronous shift amount (FIG. 7A) and the address advance amount (FIG. 7A).
Both of b) are combined, and it is possible to control so as to obtain a desired scroll amount by adjusting the amounts thereof.

The read control operation will be described below, but here, the control of the field memory differs greatly depending on the scroll direction (±), that is, between the first and second examples. In this case, the meaning of each signal used in the memory read control is as follows. RCK-Write side system clock. In this example, 8 fsc ≈ 14.32 MH _Z. Sampling frequency of A / D.
The internal read address pointer is incremented in synchronization with this rising. RVCLR-Field memory V period address clear pulse. When this is H, the internal read address pointer becomes address 0 at the rise of RCK. RHCLR-H address clear pulse for field memory. When this is H, the internal read address pointer becomes the start address of the line unit at that time at the rise of RCK. RHINC-Line memory line address increment pulse. When this is H, the internal write address pointer becomes the address of the next line at the rise of RCK. In this example, the method of creating the RHIN C varies greatly depending on the scroll direction.

<Case of Example 1> The remaining 15H of video data must be advanced on the double speed reading side. Therefore, during the H period section immediately after the RVCLR pulse, RHIN
C pulse is continuously given to 15 memories, and ReadAddrPo
The inter 52 is the address 15 hours ahead. In this way, the target + 30H scroll is achieved in total.
FIG. 9 shows each pulse used on the read side. As shown enlarged in the lower part of the figure, ReadAddrPoin is synchronized with the rising edge of RCK in the H section of each RHINC pulse.
The ter 52 transits to the next line address. This operation is performed immediately after RVCLR which is given to the memory in a 2V cycle (double speed cycle, 120H _{Z in} this example), and the read data is read from the 2Hth memory cell array (MemoryCellArray) 5
It is composed of the video signal of the 16th line stored in 0. After that, RHCLD and RHI1C become the same and are read out in order. FIG. 10a shows the positional relationship of the read video signals. Since the reading side advances by 15H, even the portion where the data is not stored on the writing side is read. This appears as an invalid image at the bottom, but this is a non-display area that is overscanned, and as shown in FIG. 10b, it is replaced with a blanking signal by the horizontal compression section (Horizontal Compression) 42 in the subsequent stage, so there is a problem. Absent.

<Case of Example 2> The remaining 15H of video data must be delayed on the double speed reading side. Therefore, the next 16H cycle of the RVCLR pulse is RHINC.
Is stopped and the value of ReadAddrPointer 52 is not incremented at address 0, so that the address is delayed by 15H. In this way, the desired scroll of -30H is realized. FIG. 11 shows each pulse used on the read side. As shown enlarged in the lower part of the figure, the ReadAddrPointer 52 remains at address 0 in the section where there is no RHINC pulse. (The period of speed, in this example 120H _Z) This operation 2V period occurs immediately after the RVCLR given to memory, increments the line address when it reaches the 16H-th is resumed, first stored in MemoryCellArray 50 The video signal of the line is read. Or later,
RHCLR and RHINC are the same and are read in order. FIG. 12a shows the positional relationship of the read video signals. Since the reading side repeats reading the line of address 0 15 times, the same data is repeated for the upper 15H, but this is a non-display area where overscan occurs, and as shown in FIG. Horizontal
There is no problem because it is replaced by the blanking signal by the Compression 42. As described above, the video signal read from the field memory for performing the field double speed and the aspect conversion together with the scroll control is shown in FIG.
b and Figure 12b, HorizontalCompressti
The upper and lower parts of on42 are replaced by blanking,
It is output through the D / A converter 13 and the LPF 14. Note that for normal and full display, the unstable area is moved to the blanking section, so a position that is slightly scrolled down as shown in FIG. 13 is optimal. It is preferable to set the center at this position also for zoom display, and this deviation can be uniformly handled by the deflection system.

(3) Distribution of scroll control amount Thus, the required scroll control amount is VSYNC.
Of the memory read and the amount of memory read. For that purpose, for example, as shown in FIG.
A control register 60 that receives setting control through a control bus is provided in the scroll control portion 43.
The control register 60 performs the following two types of arithmetic processing corresponding to the control register value set as shown in the lower part of the figure. A. Memory read movement amount Only the upper 6 bits (D1 to D5) of the V scroll setting value 7 bits of the control register are used. B. VSYNC movement amount The value obtained by adding LSB (D0) to the memory read movement amount (A) is used. This creates two movement amounts. In the calculation of (B) above, the movement resolution is set to 1H by adding LSB. If this addition is not performed, the change widths (steps) of the two coincide with each other, resulting in scrolling in 2H units. In the actual set, as described above, the position scrolled down a little is treated as the center value in consideration of the unstable section of the VTR reproduction in the normal state. From the value thus obtained, as shown in FIG.
INCGenerate part 61 and Countdown & Scroll contr
Each control signal is created by the ol part 43, and (A)
Can be supplied to the memory read control unit and (B) to the VSYNC movement control unit to realize a desired amount of scroll control.

Next, a scroll control device which is another embodiment of the present invention will be described. In the present embodiment, in the zoom display mode, the upper and lower sections of the blank portion of the image are detected from the video signal, the vertical position and size of the video display portion are calculated based on this, and the image is calculated based on these calculation results. The zoom control is performed so that the blank portions on the left, right, top, bottom, and left of the display screen are out of the range of the display screen, and the scroll control is performed so that the center positions of the video display portion and the display screen in the vertical direction match.

The block diagram of FIG. 16 shows a main part of a television receiver to which the scroll control device of this embodiment is applied. Reference numeral 71 shown in the figure is an input terminal to which an image signal received / selected by an external source or an antenna / tuner unit (not shown) is input, and 72 is a horizontal time axis compression of the input image signal by digital arithmetic processing. The horizontal time axis compression unit that performs size conversion in the horizontal direction of the displayed image by 73, 73 performs various video signal processing on the signal that has passed through the horizontal time axis compression unit, and finally outputs the amplified RGB signal. The video output unit 74 is a CRT that is displayed by scanning the RGB signals input from the video output unit 73 as an electron beam, and in this case, has a screen having a size corresponding to an aspect ratio of 16: 9. .

Reference numeral 75 is a sync separation circuit for extracting a vertical / horizontal sync signal from the video signal, and 76 is a vertical deflection sawtooth wave generation circuit for generating a vertical deflection sawtooth wave based on the vertical synchronization signal input from the sync separation circuit 75, Reference numeral 77 is an amplitude control unit for changing the amplitude of the vertical deflection sawtooth wave. Reference numeral 78 denotes a vertical deflection output circuit that amplifies the vertical deflection sawtooth wave input from the amplitude controller and outputs it as a vertical deflection current. By supplying this vertical deflection current to the deflection yoke DY, the CRT 74 performs vertical scanning.

Reference numeral 79 is a blank detection circuit, which displays the input video signal as blanks above and below based on the video signal input from the input terminal 71 and the vertical / horizontal synchronization signal input from the sync separation circuit 80. Area is detected. Then, the detected data is output to the CPU 80.

The CPU 80 is composed of a microcomputer or the like, and outputs control signals to the horizontal time axis compression unit 72, the vertical deflection sawtooth wave generation circuit 76, and the amplitude control unit 77 shown in the figure, and also to a circuit unit (not shown) or the like. A control signal is output to control the operation of each circuit unit.

With the above-described structure, in this embodiment, scroll control for changing the vertical position of the image and zoom control for displaying the image by changing the enlargement ratio of the image are possible. That is, in order to control the vertical position (scrolling) of the image, the CPU 80 outputs a control signal to the vertical deflection sawtooth wave generation circuit 76 shown in the figure to scroll the phase of the vertical deflection sawtooth wave with respect to the video signal. It is possible by changing it according to the amount. To control the image enlargement ratio (zoom), a control signal is output to the horizontal time axis compression unit 72 to change the horizontal enlargement ratio of the image, and a control signal is output to the amplitude control unit 77. Then, the amplitude of the vertical deflection sawtooth wave is changed to change the scanning width in the vertical direction.

Further, in the present embodiment, when the zoom display mode is set, the CPU 80 causes the blank detection circuit 7 to operate.
The upper and lower display positions and sizes of the video display portion are calculated based on the detection data input from 9, and the scroll is performed so that the video display portion is displayed at an appropriate vertical position and an appropriate enlargement ratio based on these calculation results. Control and zoom control are performed.

Reference numeral 81 denotes an operation unit, which allows the user to input instruction information such as selection of volume, channel, source, etc., in addition to the instruction to switch the image display modes such as normal and zoom. The CPU 80 performs various control operations according to the input instruction information.

A concrete example of the blank detection circuit 79 is shown in the block circuit diagram of FIG. A shown in the figure is a comparator, which compares the level of the input video signal with the comparison voltage Er set to a predetermined level. When the level of the video signal is equal to or higher than the comparison voltage Er, the H level is changed. Is output. Reference numeral 82 denotes a pulse generation circuit, which is composed of, for example, a retriggerable monostable multivibrator or the like, and outputs one H level pulse set to a predetermined width when the output from the comparator A rises to H level. Reference numeral 83 denotes a blank detection trigger output circuit on the upper side of the image, which is composed of, for example, a monostable multivibrator or the like. Output to 84.

Further, reference numeral 86 inverts the phase of the pulse output from the pulse generating circuit 82 to make the next window circuit 8
It is an inverter that outputs to 7. This window circuit 8
A window pulse, which will be described later, is input to CPU 7 from CPU 80. For example, when this window pulse is set to L level, the switch inside window circuit 87 is turned off and the conduction of signals is cut off. Reference numeral 88 denotes a trigger output circuit for blank detection on the lower side of the image,
The pulse output from the pulse generation circuit 82 having the opposite phase by 6 is input via the window circuit 87. When the input pulse rises to H level, one trigger pulse is output to the blank detection latch circuit 89 on the lower side of the image.

Reference numeral 85 denotes a counter, and this counter 85
A horizontal synchronizing signal and a vertical synchronizing signal as a reset signal are input to the. Then, the number of input horizontal synchronizing signals is counted, and when the vertical synchronizing signal is input, the count number is reset and counting is started again from 0.
That is, the number of horizontal synchronization signals in one field is counted along the time axis, and the count value of the horizontal synchronization signals that is incremented by this counting operation is used as the blank detection latch circuit 84 on the upper side of the image and the lower side of the image. It is output to the side blank detection latch circuit 89. For example, when a trigger pulse is input from the trigger output circuit 83 to the blank detection latch circuit 84 on the upper side of the image, the latch circuit 84 holds the count value of the horizontal synchronization signal at the time when the trigger pulse is input, This data will be output to the CPU 80. Then, the vertical synchronizing signal as a reset signal is input to the latch circuit 84, but at the time when the vertical synchronizing signal is input to the latch circuit 84, the held data must be reset. Becomes By the same operation, the latch circuit 89 for blank detection on the lower side of the image also latches the data of the count value of the horizontal synchronizing signal at the time when the trigger pulse is input and outputs it to the CPU, and the reset signal (vertical synchronizing signal) is output. The data held at the time of input is reset.

Here, the operation of the blank detection circuit 79 in the above configuration will be described with reference to the timing chart of FIG. The signal shown in FIG. 18A is the comparator A
Shows a waveform of a video signal input to the input terminal, and the alternate long and short dash line in this figure represents the threshold level T, which corresponds to the reference voltage Er of the comparator A. Further, V ₁ and V ₂ represent vertical synchronizing signals, H represents a horizontal synchronizing signal, and B ₁ and B ₂ correspond to upper and lower blank portions. 18B shows the output of the comparator A, and FIG. 18C shows the output of the pulse generation circuit 82. 18D shows the output of the blank detection trigger output circuit 83 on the upper side of the image. FIG. 18E shows the latch circuit 8 for blank detection on the upper side of the image.
4, the latch circuit 84 holds the count value of the horizontal synchronizing signal and outputs it to the CPU 80 during the period when the waveform is at the H level in the figure. 18F shows the output of the window pulse, FIG. 18G shows the output of the blank detection trigger output circuit 88 on the lower side of the image, and FIG. 18H shows the blank detection latch circuit on the lower side of the image. The output of FIG. 1 is shown in the same manner as the case of the blank detection latch circuit 84 on the upper side of the image.
During the period in which the output of 8 (h) is at the H level, it indicates that the count value of the horizontal synchronizing signal is held and is output to the CPU 80.

The comparator A compares the level of the input video signal with the threshold level T shown in FIG.
Compared with (reference voltage Er), when the video signal level is equal to or higher than the threshold level T, the H level is output. In the period T _{0 to} T ₁ after the vertical synchronizing signal V ₁ of the video signal shown in FIG. 18A has passed, the video signal is a non-video display section having no brightness, and this section is the image display. In this case, the upper blank portion B ₁ is formed. Since the level of the video signal of the interval is below the threshold level T, in T ₀ through T ₁ period 1
The output of the comparator shown in 8 (b) becomes L level.

When the blank portion B _{1 on} the upper side of the video signal ends at time T ₁ and the brightness rises (indicating that some video is displayed) and the level of the video signal exceeds the threshold level T, the comparator A sets the H level. Will be output. In response to the H level output of the comparator A, the pulse generation circuit 82 shown in FIG. 18C also outputs one pulse having a predetermined width (corresponding to several H) at the time T ₁ .

By the way, in the video signal shown in FIG. 18A, since the horizontal synchronizing signal H is inserted at a constant interval,
In the part where the video is displayed in the video signal,
The output of the comparator A becomes L level for each horizontal synchronizing signal H. Therefore, in the period shown as the video signal level being equal to or higher than the threshold level T, such as the period from T _{1 to} T ₂ , the output of the comparator A is at the L level at the time of the horizontal synchronizing signal H and at the time of the video signal. Then, the state of outputting the H level is continuous. As described above, since the pulse generation circuit 82 is retriggerable, the pulse generated by the pulse generation circuit 82 has a predetermined time (equivalent to several H) during the period when the video signal level is equal to or higher than the threshold level T. Before the output is stopped after a certain period of time, the H level is input from the comparator A. Therefore, for example, in the period of T _{1 to} T ₂ , the pulse generation circuit 82 continuously outputs the H level.

When the pulse of the pulse generation circuit 82 rises at time T ₁ , a trigger pulse is output from the blank detection trigger output circuit 83 on the upper side of the image as shown in FIG. 18D. With this trigger output,
As shown in FIG. 8 (e), the blank detection latch circuit 84 on the upper side of the image holds the data of the count value of the horizontal synchronizing signal input from the counter 85 at time T ₁ and outputs this data to the CPU 80. Will be done.

At this time T ₁ , the CPU 80 determines that the upper blank portion is finished, and
The window pulse shown in (f) is set to L level, and control is performed in the window circuit 87 so as to cut off signal conduction. As will be described later, when the level of the video signal becomes equal to or lower than the threshold level T in a period that is not a blank portion such as T _{2 to} T ₄ , the pulse of the pulse generation circuit 82 rises at T _3. The trigger output circuit 88 for detecting the blank on the lower side of the image does not operate in response to the decrease. It should be noted that the time for outputting the window pulse of the L level has a certain degree of symmetry in the upper and lower blank portions, so that the CPU 80
Can almost predict the time when the lower blank portion starts from the data of the count value of the horizontal synchronizing signal input at time T ₁ . Then, a time point before the predicted start time of the lower blank portion to some extent (time point T _{5 in} this case) is set, and the L level of the window pulse is set until the set time is reached. It will be continued.

When the level of the video signal of FIG. 18 (a) becomes lower than the threshold level T in the period of T _{2 to} T ₄ (in this case, some video is displayed, but a portion with extremely low brightness is shown), The output of the comparator A in FIG. 18B becomes L level during the period of T _{2 to} T ₄ . Since the output of the comparator A becomes the L level at the time point T ₂ , the output of the pulse generation circuit 82 in FIG. 18C is at the time point T ₃ when a time for outputting a predetermined pulse width has elapsed from the time point T ₂ . The pulse output is stopped. In this T ₃ time, since the pulse output of the pulse generating circuit 82 falls, the pulse output of the rising is the reverse phase are output to the window circuit 87 by passing through the inverter. However, this window circuit 87
Is in a non-conductive state because the window pulse is at the L level during the period from the time point T _{1 to the} time point T _{5 which} will be described later. This pulse output is not input to the blank detection trigger output circuit 88 on the lower side of the image. . Therefore, T
_{At the 3rd} point of time, the blank detection trigger output circuit 88 on the lower side of the image does not operate. In this way, even when the signal level becomes lower than the threshold level T in the image display portion other than the blank portion, this will not be erroneously detected as the start time point of the lower blank portion. .

When the level of the video signal again becomes equal to or higher than the threshold level T at the time point T ₄ , the comparator A outputs the H level. Then, by this output, a trigger pulse is output from the blank detection trigger output circuit 83 on the upper side of the image shown in FIG. 18D to the blank detection latch circuit 84 on the upper side of the image, but the blank detection on the upper side of the image is detected. Since the vertical synchronizing signal that is the reset signal is not input to the latch circuit 84 for vertical after the vertical synchronizing signal V ₁ , as shown in FIG. The data of the count value of the horizontal synchronizing signal held at _one time point is still held.

In the period of T _{4 to} T ₆ , the output of the comparator A is the horizontal synchronizing signal H as in the period of T _{1 to} T _2.
At the time point of, the L level is output, and at the time of the video signal, the H level is output, whereby the pulse generating circuit 82 continuously outputs the pulse.

By the way, at time T ₅ , the CPU 80
Since it is the time to end the L level output of the window pulse set in step 3, the L level output of the window pulse is set to the H level at time T ₅ . As a result, the window circuit 87 is made conductive and the inverter 8
The pulse of the pulse generation circuit 82 having the opposite phase via 6 can be input to the blank detection trigger output circuit 89 on the lower side of the image.

When the level of the video signal becomes equal to or lower than the threshold level T at time T ₆ , the output of the comparator A becomes L level, which causes the pulse generation circuit 8 to operate.
With respect to the output of No. 2, the pulse output is stopped at the time point T ₇ after the time when the predetermined pulse width is output from the time point T ₆ . Then, in the T ₇ point, the pulse output of the pulse generating circuit 82 falls to L level, by passing through the inverter 86 for the trigger output circuit 89 of the blank detection image lower, the pulse generating circuit The pulse 82 rises to the H level and is input. The blank detection trigger output circuit 89 on the lower side of the image is
Since the trigger pulse is output according to the rising edge of the input pulse, the trigger pulse is output at the time point T ₇ as shown in FIG. 18 (g). As a result of this trigger pulse, as shown in FIG. 18H, the blank detection latch circuit 89 on the lower side of the image latches the data of the count value of the horizontal synchronizing signal at the time point T ₇ , Output to the CPU 80. Where T ₆
As can be seen from FIG. 18A, the period up to T ₈ corresponds to the blank portion B ₂ on the lower side of the display image. Therefore, T ₇
The data of the count value of the horizontal synchronizing signal latched at the time point is used as the lower blank detection data. Although the lower blank portion actually starts from the time point T ₆ , the pulse output time set by the pulse generation circuit 82 causes the C
T ₆ from T ₇ when the data is input in PU80
By calculating the time point, the correct start time point of the lower blank portion can be determined.

In this way, when the lower blank portion B ₂ ends after the time T ₈ and reaches the vertical sync signal V ₂ of the next field, this vertical sync signal is applied to the sync separation circuit 75 shown in FIG. Is input to both latch circuits 84 and 85. Thus, at the time T ₈ Fig 18 (e),
As shown in (h), each data held in both latch circuits 84 and 85 is reset. Further, at this time, the vertical synchronizing signal is similarly input to the counter 85, the count value is reset, and the number of horizontal synchronizing signals H of the video signal in the fields after the vertical synchronizing signal V _{2 is} counted again from 0. It will be.

In this way, the data obtained by detecting the positions in the video signals of the upper and lower blank portions from the blank detection circuit 79 is supplied to the CPU 80 for each field. Therefore, in the CPU 80,
Based on this data, the vertical position of the display image due to the deviation of the upper and lower blank part widths and the size of the image display unit with respect to the display screen are calculated. Then, based on the result of calculating these, for example, the enlargement ratio at which the blank parts at the top, bottom, left, and right of the image are out of the range of the display screen, and the center positions of the display screen and the video display part in the vertical direction match Set the scroll amount. The CPU 80 sends each control signal corresponding to the data set in this way to
6, the horizontal time axis compression unit 72 (variable horizontal size of the image), the amplitude control unit 77 (variable vertical size of the image), and the vertical deflection sawtooth wave generation circuit 76 (variable vertical position) are output.

As described above, the blank detection circuit 79
The CPU 80 performs control on the basis of the data detected in step S1, so that the image display is performed at the zoom ratio and the vertical position that are optimal according to the video source in the zoom display mode. That is, in the present embodiment, the above-described FIG.
As shown in 0 (a) or FIG. 20 (d), even if the video source is such that the video position is originally biased in the vertical direction, when the zoom display mode is set, for example, As shown in FIG. 20 (c) or FIG. 20 (f), the enlargement ratio is set so that the blank part of the image is outside the range of the display screen, and at the same time, FIG. 20 (c) to FIG. 20 (g) or FIG. From FIG. 20 (g) to FIG. 20 (g), position adjustment is automatically performed so that the image display portion is not displaced in the vertical direction.

By the way, when the image is enlarged to such an extent that the upper, lower, left and right blank portions are not displayed as shown in FIG. 20G, the upper and lower parts of the screen are actually overscanned as shown in FIG. 19C. In some sources such as movies, the subtitle displayed at the bottom of the screen may not be visible. Therefore, FIG. 20 (h)
It may be controlled so that at least the upper and lower blank portions are enlarged so that they cannot be seen, as shown in FIG. Even in this case, if there is a deviation in the vertical position of the image, it is naturally controlled to correct the vertical position. Alternatively, as shown in FIG. 20 (i), the scroll-up may be controlled until the lower overscan portion disappears. Therefore, the CPU 80 enables automatic control of the enlargement ratio in the zoom display mode to be selected from the display methods shown in FIGS. 20 (g), 20 (h), and 20 (i) by the user's input operation. It is also conceivable that the operation unit 81 is configured.

Although the above-described operation of the CPU 80 sets the enlargement ratio and the scroll amount of the display image based on the detection data of the blank portion in the video signal for each field, it detects a plurality of fields for a predetermined period. The data is input, the average value of these values is calculated, the enlargement ratio of the display image and the scroll amount are fixedly set based on the data based on the average value, and thereafter, the control signal based on the data is output. May be done.

Regarding the timing of blank portion detection for automatic control of image scrolling and zooming in this embodiment, for example, it is performed every time the channel or video source is switched, or every predetermined time. It is conceivable that the detection operation is performed based on the instruction from the operation unit of the user.

In this embodiment, the vertical position of the image and the enlargement ratio are automatically controlled in the zoom display mode, but only the vertical position of the image is controlled in the normal display mode. May be done. In this case, the widths of the upper and lower blank portions of the image can be made uniform.

Further, the scroll control of the upper and lower sides of the image in this embodiment is performed by the CPU 80 by outputting a control signal to the vertical deflection sawtooth wave generating circuit 76 shown in FIG. 16 to control it. May be used, for example, it may be realized by the control at the time of writing and reading in the field memory after the field double speed processing described in FIG. 1 as the previous embodiment. Therefore, when the circuit configuration of FIG. 17 of the present embodiment is applied to the television receiver of FIG. 1, although not shown, the control signal of the CPU 80 for adjusting the vertical position of the image is the vertical deflection. Instead of being output to the system, it is output to the field double speed and aspect conversion unit 3 shown in FIG. Then, the countdown and scroll control portion 43 (shown in FIG. 5) inside the field double speed / aspect converter 3 performs a processing operation in accordance with the control signal, so that vertical scrolling is performed. . In this case as well, in order to move the unstable area of the image to the non-display section (blanking section), it is preferable to set the position slightly scrolled down as the center position of the image display portion, as in the previous embodiment.

[0061]

According to the scroll control device of the present invention configured as described above, the field memory has one
A field is enough, and both an image passing phenomenon caused by the movement of the read start address and an unstable portion of the image caused by the movement of the original V sync position do not enter the image display area, and stable operation is realized. . Further, during normal or full display, the image can be scrolled down a little and the unstable area generated in an unstable image such as a VTR can be moved to the non-display area.

Further, each section of the upper and lower blank portions of the display image is detected, and based on the detected data, control is performed so that the enlargement ratio of the image and the upper and lower video display positions are appropriate. By doing so, the user is freed from the trouble of having to correct the vertical position and the like of the image each time he or she views a different video source.

[Brief description of drawings]

FIG. 1 is a block diagram showing a basic configuration of an HDTV receiver to which the present invention is applied.

FIG. 2 is an explanatory diagram illustrating a video display mode.

FIG. 3 is a time chart for explaining a scroll operation.

FIG. 4 is a time chart and an explanatory diagram for explaining an unstable region in a scroll operation.

FIG. 5 is a block diagram showing a basic configuration of a field double speed and aspect conversion unit.

FIG. 6 is a block diagram showing an internal configuration of a field memory and an explanatory diagram for explaining its operation.

FIG. 7 is a time chart and an explanatory diagram for explaining a scroll operation according to the present invention.

FIG. 8 is a time chart and an explanatory diagram for explaining a write operation of the scroll control device according to the present invention.

FIG. 9 is a time chart and an explanatory diagram for explaining a read operation at the time of scrolling up of the scroll control device according to the present invention.

FIG. 10 is an explanatory diagram for explaining a video signal at the time of scrolling up, which is obtained by the scroll control device of the present invention.

FIG. 11 is a time chart and an explanatory diagram for explaining a read operation at the time of scrolling down of the scroll control device according to the present invention.

FIG. 12 is an explanatory diagram for explaining a video signal at the time of scrolling down, which is obtained by the scroll control device of the present invention.

FIG. 13 shows V in the scroll control device according to the present invention.
It is a time chart for explaining a center.

FIG. 14 is an explanatory diagram for explaining a method and means for distributing scroll control amounts in the scroll control device according to the present invention.

15 is a block diagram showing a configuration for performing scroll control based on the distributed scroll control amount in FIG.

FIG. 16 is a block diagram showing a main part of a television receiver to which a scroll control device according to another embodiment is applied.

FIG. 17 is a block diagram showing a configuration of a blank detection circuit of a scroll control device according to another embodiment.

FIG. 18 is a timing chart showing the operation of the blank detection circuit in another embodiment.

FIG. 19 is an explanatory diagram showing a state where a video source of a Vista size or a cinemascope size corresponding to an aspect ratio of 4: 3 is displayed on a screen having an aspect ratio of 16: 9.

FIG. 20 is an explanatory diagram showing an image display state in another embodiment.

[Explanation of symbols]

 1 tuner 2 video signal processing (1) circuit 3 field double speed and aspect converter 4 video signal processing (2) circuit 5 decoder 6 deflection processing circuit 7, 74 CRT 12, 22, 32 field memory 40 PLL circuit 41 field double speed processing timing Controller 42 Aspect conversion part 43 Countdown and scroll control part 50 Memory cell array 51 Write address pointer 52 Read address pointer 53 Write port 54 Read port 60 Control register 72 Horizontal time axis compression part 76 Vertical deflection sawtooth wave generation circuit 77 Amplitude control part 78 Vertical Deflection output circuit 79 Blank detection circuit 80 CPU 81 Operation unit 82 Pulse generation circuit 85 Counter 83, 88 Trigger output circuit 84, 89 Latch circuit A comparator Data

[Procedure amendment]

[Submission date] April 30, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0024

[Correction method] Change

[Correction content]

The meanings of the signals used in the write control are as follows. WCK-Write system clock. In this example
4 fsc ≈ 14.32 MH _Z. Sampling frequency of A / D.
The internal write address pointer is incremented in synchronization with this rising. WVCLR-Field memory V period address clear pulse. When this is H, the internal write address pointer becomes address 0 at the rise of WCK. WHCLR-field memory H cycle address clear pulse. When this is H, the internal write address pointer becomes the start address of the line unit at that time at the rise of WCK. WHINC-Field memory line address increment pulse. When this is H, the internal write address pointer becomes the address of the next line at the rising edge of WCK. In this embodiment, WHINC is the same signal as WHCLR.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] 0027

[Correction method] Change

[Correction content]

The read control operation will be described below, but here, the control of the field memory differs greatly depending on the scroll direction (±), that is, between the first and second examples. In this case, the meaning of each signal used in the memory read control is as follows. RCK- Read side system clock. In this example, 8 fsc ≈ 28.64 MH _Z. Sampling frequency of D / A.
The internal read address pointer is incremented in synchronization with this rising. RVCLR-Field memory V period address clear pulse. When this is H, the internal read address pointer becomes address 0 at the rise of RCK. RHCLR-H address clear pulse for field memory. When this is H, the internal read address pointer becomes the start address of the line unit at that time at the rise of RCK. RHINC-Line memory line address increment pulse. When this is H, the internal write address pointer becomes the address of the next line at the rise of RCK. In this example, the method of creating the RHIN C varies greatly depending on the scroll direction.

Claims (9)

[Claims] 1. A field double speed processing means for multiplying and converting a field frequency of an input video signal, comprising a field memory in which write and read operations are controlled respectively, and write and read operations in the field double speed processing means. The field double speed processing timing controller is provided with a field double speed processing timing controller for supplying a necessary control signal, and a video display means to which the output video signal of the field double speed processing means is supplied and which is synchronously driven by a scanning frequency converted by multiplication. The vertical synchronizing signal in the input video signal is supplied after being shifted for a predetermined time, and the read start address in the control signal necessary for the read operation supplied to the field memory is shifted by a predetermined value, thereby The image displayed on the screen of the display means. A scroll control device for double-speed field display, which scrolls an image up and down. 2. The output video signal of the field double speed processing means is supplied, the video signal is converted so as to match the aspect ratio of the video displayed on the screen of the video display means, and the video signal in the non-display area is blocked. The image display means includes a function of making the scanning width at least in the vertical direction excessive so that the non-display area is located outside the screen in preparation for the aspect conversion means for replacing with the ranking signal. Scroll control device for double-speed field display. 3. The shift amount of the read start address supplied to the field memory is made to correspond to almost half of the target scroll control amount, and the shift amount of the vertical synchronizing signal in the input video signal supplied to the field double speed timing controller. The scroll control device for double-speed field display according to claim 1 or 2, wherein the scroll control amount for the purpose is equivalent to the remainder. 4. A first set value for setting a shift amount of a read address to be supplied to the field memory by a digital value consisting of only the upper digit excluding the lowest digit of the digital set value for setting the target scroll control amount. And a control register having a second set value for setting the shift amount of the vertical synchronizing signal supplied to the field double speed timing controller by a digital value obtained by adding the least significant digit to the first set value. 3. A scroll control device for double-speed field display according to item 3. 5. A field double speed and aspect conversion processing means having a field memory to which an input video signal is supplied, a field double speed processing timing controller which supplies a control signal necessary for field double speed processing, a field double speed and aspect conversion processing. HDTV equipped with a video display means for displaying a video according to a video signal
In a / NTSC television receiver, the vertical synchronizing signal in the input video signal is supplied to the field double speed processing timing controller after being shifted for a predetermined time, and the read start address in the control signal necessary for the field double speed processing is supplied. Is shifted by a predetermined value to scroll the image displayed on the screen of the image display means up and down.
TV / NTSC television receiver. 6. In various display modes of an image by a field double speed and aspect-converted image signal, a small amount of the image is scrolled downward to move an unstable region of the image to a non-display region. 5. An HDTV / NTSC television receiver according to item 5. 7. A blank detecting means for detecting a section of upper and lower blank portions which are non-video display portions in a display image based on an input video signal and horizontal and vertical synchronizing signals, and a vertical position of the display image. Variable scrolling means, based on the information detected by the blank detection means,
A vertical position with respect to the display screen is calculated for the video display portion in the display image, and based on the calculated result, a control signal for matching the upper and lower center positions of the display screen with the upper and lower center positions of the video display portion is set. A scroll control device comprising: a control unit capable of outputting to the scroll unit. 8. A zoom means for performing video signal processing capable of varying the magnification of a display image stepwise or continuously and displaying the image on the display screen, in a zoom mode in which the zoom means is operable, The control unit calculates the vertical position and the size with respect to the display screen for the video display portion based on the information detected by the blank detection means, and based on the calculated size of the video display portion with respect to the display screen. Then, a control signal for varying the enlargement ratio of the display image is output to the zoom means so that the upper and lower and / or left and right blank portions are out of the range of the display screen. Based on the vertical position with respect to the display screen,
The control signal for making the center position above and below the display screen position and the center position above and below the image display portion coincide with each other is output to the scroll means. Scroll controller. 9. The scroll control device according to claim 7, wherein the scroll control device is mounted on a television receiver having the display screen corresponding to an aspect ratio of 16: 9.