JP3520544B2 - Video signal display method, video signal display device, and television device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal display method for displaying and processing video signals of various television systems,
The present invention relates to a video signal display device that executes this video signal display method, and a television device that includes this video signal display device and that can perform appropriate video display of various television systems.

[0002]

2. Description of the Related Art Conventionally, in a television device having a display such as a CRT, an NTSC system or a PAL system in which an aspect ratio of a display surface is 4: 3,
There is a high-definition (HDTV) system in which the aspect ratio of the display surface is 16: 9. This HDTV television is equipped with an aspect conversion means for converting the aspect ratio so that the NTSC or P
It is general that the current AL system broadcast can be displayed. In the case of displaying the image after the aspect conversion, a frame signal is added to the blank portion generated as a result of the time axis compression in the horizontal direction by the signal processing, or the child screen is displayed.

By the way, the final effective image display area in the CRT type display is determined by the amount of overscan caused by the deflection process. This overscan amount is because the video signal of the home video display is such that the effective video area is subtly different depending on the broadcasting station, and the video signal of all video signals such as the VTR and the external decoder which are subtly different. It is set to a large overscan amount so that the image loss of the display image does not occur in the section. That is, as shown in FIG. 19A, even if the display area of a certain video signal is within the range of Condition 1 indicated by the alternate long and short dash line, the display areas of other different video signals are indicated by the alternate long and two short dashes line. Even if the range of Condition 2 is set, the area indicated by the solid line is set as the effective display area so as not to cause image loss.

Further, in a commercial monitor display, overscan can be switched to underscan to check all parts of the input video signal. That is, as shown in FIG. 19B, the display image displayed on the CRT is slightly smaller than the displayable range of the CRT, and the periphery of the image is a non-display portion. Further, in the computer display, since the conditions of the signal source are varied, it is necessary that the horizontal display position can be easily adjusted. That is, as shown in FIG. 19C, it is possible to move the display image left and right with respect to the possible display range of the CRT.

[0005]

However, 16:
On a display having an aspect ratio of 9, when a video signal having an aspect ratio of 4: 3 is subjected to aspect conversion and displayed, since the frame signal is added as described above,
The final effective display range is the width of this frame signal (timing)
And is not related to the amount of overscan caused by the deflection processing. Therefore, when an overscan amount that exceeds the design specifications is required due to the input signal conditions,
The aspect conversion LSI must be changed at the design level, which makes it practically impossible. Such an input condition has recently been found, for example, in a part of Europe where a defective section (scramble remaining) is present at the right end of the output image of the descrambling decoder (Canalplus decoder). In addition, when trying to remove by increasing the overscan amount, as shown in FIG.
As shown in (a), the added frame portion is also enlarged in the arrow direction due to the overscan, and there is a problem that the scrambled residue cannot be removed from the screen.

Under-scanning is also required in the case of a commercial monitor display having an aspect ratio of 16: 9, but if under-scanning is performed, the size of the displayed image becomes small as shown in FIG. 20 (b). There is also a problem in that the added frame is also small, and it is not possible to perform underscan for checking all the video signals. Furthermore, in the case of a computer display with an aspect ratio of 16: 9, when trying to move the display image to the left or right, the frame added with the movement of the display image also moves as shown in FIG. There was a problem that only the position could not be moved.

Therefore, according to the present invention, in a display image to which a frame is added, as shown in FIG. 21A, only the position of the display image is overscanned while the frame is fixed, or as shown in FIG. In addition, a video signal display method in which only the display image can be underscanned or only the display image can be moved left and right without moving the frame, as shown in FIG. An object of the present invention is to provide a video signal display device for executing the method, and a television device including the video signal display device.

[0008]

In order to achieve the above-mentioned object, the video signal display method of the present invention is a method for displaying various broadcasting systems.
Depending on the writing timing pulse of the digital video signal
Write to field memory, then to the field memory
Read the written digital video signal
Read out according to the
Aspect conversion of the read digital video signal
The aspect ratio is converted by means of
In addition to adding a frame signal according to the imming pulse,
The writing timing of the input digital video signal
It is set for each broadcasting system according to the ng pulse.
The position adjustment pulse can be adjusted based on an appropriate value,
The digital video signal on the field memory
If you can adjust the relative writing position of the issue
The read timing pulse and the frame
Fixed the timing of additional timing pulse
As input signal of digital video signal
A video signal is displayed on a display device with an aspect ratio different from the pecto ratio.
The voltage is applied . Furthermore, the video signal display method of the present invention is such that the time width of the frame signal can be adjusted.

Further, the video signal display device of the present invention has various types.
A digital video signal for various broadcasting systems is written in
Field memory and at least the image displayed on the display means.
Frame addition timing of the frame signal of the frame displayed on one side
A frame signal generating means for generating a pulse,
The aspect ratio of the video signal read from the
Aspect converter for conversion and on the field memory
Relative writing position of the digital video signal in
The timing was made adjustable so that the position could be adjusted.
The write timing pulse and the write timing pulse
Appropriate value set for each broadcasting system according to
Position adjustment pulse that can be adjusted based on
Read the digital video signal written in the memory.
Timing that generates a read-out timing pulse
Pulse pulse generating means, and the input digital
Position according to the write timing pulse of the video signal
By adjusting the adjustment pulse, the field
Relative writing of the digital video signal on memory
The read-out position can be
Timing pulse and the frame-added timing pattern
The input data that fixed the timing of the
Aspect ratio different from that of digital video signal
The image signal is applied to the display means of
It

Furthermore, the video signal display apparatus of the present invention, prior to
A horizontal phase synchronizing signal of various broadcasting systems is input to one side, and a first phase comparator to which the first decoder output is applied to the other side, and an error signal by smoothing the comparison output of the first phase comparator. A first low-pass filter, a first voltage-controlled oscillator whose oscillation frequency is controlled according to the error signal from the first low-pass filter, and an output pulse from the first voltage-controlled oscillator. A first counter; and a frequency dividing means for dividing the output pulse from the first voltage controlled oscillator, which is composed of the first decoder to which the count value of the first counter is input. By applying a horizontal position adjustment signal of an image displayed on the display device to the first decoder, the time position of the write pulse output from the first decoder is adjusted. Than it is.

Furthermore, the video signal display device of the present invention includes a second phase comparator to which the horizontal synchronizing signals of the various broadcasting systems are input to one side and the second decoder output is applied to the other side, and the second phase comparator. A second low-pass filter that smoothes the comparison output of the phase comparator into an error signal, a second voltage-controlled oscillator whose oscillation frequency is controlled according to the error signal from the second low-pass filter, and the second voltage. The frequency of the output pulse from the second voltage controlled oscillator, which is composed of a second counter that counts the output pulse from the controlled oscillator and the second decoder to which the count value from the second counter is input, is divided. A frequency dividing means, and by applying a signal for adjusting the frame width of the image displayed on the display device to the second decoder, the time width of the frame signal output from the second decoder It is obtained so as to adjust.
The television device of the present invention includes the above-mentioned video signal display device and display device.

[0012]

In the video signal display method of the present invention, the relative writing of the digital video signal on the field memory is performed.
Timing can be adjusted so that the cutting position can be adjusted
Therefore, to be able to move the position of the left and right display image while fixing the frame, in response to a video signal source of a variety of conditions,
The horizontal display position of the display image can be adjusted. Furthermore, if the time width of the frame signal can be adjusted,
Since the width of the frame to be displayed can be adjusted, the frame width can be reduced and the deflection system can be overscanned so that only the display image can be overscanned or the frame width can be increased. Underscanning makes it possible to underscan only the display image.

Further, since the video signal display device of the present invention is provided with the write pulse generating means for generating the write pulse supplied to the field memory whose timing can be adjusted, the head write position in the field memory can be set. It can be adjusted, and the left and right positions of the display image can be moved while the frame is fixed. Therefore, it is possible to adjust the horizontal display position of the display image corresponding to the video signal sources of various conditions. Furthermore, since the time position of the write pulse output from the first decoder is adjusted by applying the horizontal position adjustment signal of the image displayed to the first decoder, the horizontal display of the display image can be easily performed. The position can be adjusted.

Furthermore, by applying a signal for adjusting the frame width of the image displayed on the display device to the second decoder, the time width of the frame signal output from the decoder is adjusted so that the image is displayed. Since the width of the frame can be adjusted, it is possible to overscan the display image only by decreasing the frame width and overscanning the deflection system, or increasing the frame width and underscanning the deflection system. By canceling, it becomes possible to underscan only the display image. Since the television device of the present invention includes the above-described video signal display device and display device, the left and right positions of the display image can be moved while the frame is fixed, so that the video signal source of various conditions can be obtained. Correspondingly, the horizontal display position of the display image can be easily adjusted, and the display width can be overscanned by reducing the frame width and overscanning the deflection system, or By increasing the frame width to undercance the deflection system, it is possible to underscan only the display image.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a television device according to the present invention. For example, this television device is a CRT having an aspect ratio of 16: 9 as a display device.
There is a device of high definition (HDTV) system having a 9- 1. This television device is Yagi Antenna 7-
1 receives VHF broadcast and UHF broadcast, and parabolic antenna 7-2 receives CS broadcast or BS broadcast, and these received signals are input to various tuners 1. A CATV signal is further input to the various tuners 1 via a cable. Various tuners 1
If the received signal is a video signal having an aspect ratio of 4: 3 such as PAL system or NTSC system, the video signal is switched to the first switch (SW1; current system Input se se).
The signal is applied to the first video signal processing section 2 via the section 8-1.

Further, the received signal has an aspect ratio of 4:
3 is a video signal that has been scrambled, the video signal from each tuner 1 is input to, for example, an external descrambling decoder 7-3 to descramble, and the descrambled video signal. As the first video signal (VIDEO in 1) as the first switch 8-1
It is applied to the first video signal processing unit 2 via. Further, the second video signal (VIDEO in 2) from the VTR or the like is input to the first switch 8-1.
-1 is a desired one of the three input video signals
One of them is selected and supplied to the first video signal processing unit 2.

In the first video signal processing section 2, the supplied video signal is subjected to processing such as Y / C separation, chroma decoding, sync separation, etc. to obtain a luminance signal Y, a color difference signal RY,
BY and the sync signal are separated or extracted. The luminance signal Y, the color difference signals RY, BY, and the synchronizing signal are supplied to the field double speed aspect conversion circuit 3 which is the video signal display device according to the present invention and executes the video signal display method according to the present invention. Has been done. In the field double speed aspect conversion circuit 3, field double speed processing, aspect conversion processing, frame addition processing and the like are performed on a video signal having an aspect ratio of 4: 3, and the processed luminance signal Y and color difference signal RY. , BY and the synchronizing signal are output respectively.

The signals received by the various tuners 1 are H
The video signal of the DTV system, that is, the video signal having the video aspect ratio of 16: 9 and the number of scanning lines of 1125 is the third switch (SW3; HD Decoder Input selecti).
on) 8- 3 through is inputted to the HD decoder 5. The HD decoder 5 is an H encoder encoded by the MUSE method, the ATV method, the HD-MAC method, or the like.
It is a decoder that decodes a DTV signal into an original video signal. An encoded HDTV signal (HD Decorder) input from the outside is input to the third switch 8-3.
in) is also input, and the third switch 8-3 selects one of the input HDTV signals and supplies it to the HD decoder 5. Further, the HDTV signal decoded by the HD decoder 5 has a second switch (SW2;
HDTV Input selection) Input to 8-2,
Decoded HDTV signals (HD VIDEOin 1, HD VIDEO in 2) input from the outside to the second switch 8-2.
Is input, the second switch 8-2 selects any one of the input HDTV signals and outputs the video signal component to the fourth switch (SW4; Video selection) 8-4. A sync signal component is supplied to the 5 switch (SW5; Sync selection).

The fourth switch 8-4 further has the field double speed aspect conversion processing output from the field double speed aspect converter 3 and is subjected to the NTSC / P.
A video signal component of the AL system or a video signal component of the HDTV system is input, and either one is selected by the fourth switch 8-4 and supplied to the second video signal processing unit 4. Further, the fifth switch 8-5 outputs the NTSC / PAL output from the field double speed aspect conversion unit 3.
System or HDTV system sync signal component is also input,
One of the selected synchronization signal components is supplied to the deflection processing circuit 6. It should be noted that the fourth switch 8-4 and the fifth switch 8-5 are synchronized with each other and are connected to the HDTV signal side or NT.
It has been switched to the SC / PAL system side. The second video signal processing section 4 includes a luminance signal Y and color difference signals RY and B.
Color signals of R, G, B are generated from -Y, and the deflection processing circuit 6 generates a vertical deflection waveform and a horizontal deflection waveform from the synchronization signal. The R, G, B color signals output from the second video signal processing unit 4 have an aspect ratio of 1
The deflection processing circuit 6 is supplied to the CRT 9-1 of 6: 9.
The vertical and horizontal deflection waveforms generated by
The image is displayed on the display surface of the CRT by being supplied to the deflection yoke 9-2 of T9-1.

Next, FIG. 2 shows a block diagram of the field double speed aspect conversion section 3, and the description will be given with reference to this figure. Field double speed aspect converter 3
Are the first field memory 12 and the second field memory
22 , a third field memory 32, a timing controller 42, an aspect converter 43, a write timing pulse generation PLL circuit 40, a read timing pulse generation PLL circuit 41, and the like.
/ NTSC system field double speed processing is performed to double the horizontal and vertical scanning frequencies of the video signal to make the horizontal scanning frequency close to the horizontal scanning frequency of the HDTV signal and remove field flicker for display. This is a circuit for improving the image quality of an image.

In the field double speed aspect conversion section 3, the input luminance signal (Yin) is subjected to removal of unnecessary high frequency components with respect to the sampling frequency by a low pass filter (LPF) 10 and an A / D converter. 11 and is converted into a digital video signal. The converted digital video signal is written in the first field memory 12. The input color difference signal (R-Yin) is
Sampling frequency by low pass filter (LPF) 20
On the other hand, unnecessary high frequency components are removed and supplied to the A / D converter 21 and converted into a digital video signal. The converted digital video signal is written in the second field memory 22. Further, the input color difference signal (B-Yi
n) is sampled by a low pass filter (LPF) 30 .
Unnecessary high frequency components with respect to the frequency are removed and supplied to the A / D converter 31 and converted into a digital video signal.
The converted digital video signal is written in the third field memory 32.

The luminance signal 2Y and the color difference signal 2R- read out from the field memories 12, 22, 32 at double speed.
Y and 2B-Y are input to the aspect conversion unit 43 and subjected to processing such as adding a frame signal.
The analog video signals are converted by the conversion circuits 13, 23, and 33, and each of them is further converted into a low-pass filter (L
The unnecessary harmonic components are removed by the PF) 14, 24, and 34, and the luminance signal 2Y, the color difference signal 2R-Y, and the color difference signal 2 are removed.
It is output as BY. In addition, the vertical sync signal (V SYN
C), the high-speed clock WCK0 generated by the first PLL circuit 40, and the high-speed clock RCK0 generated by the second PLL circuit 41.
To the write clock pulse WCK and write reset pulse WVCL.
R, write line reset pulse WHCLR, write line address increment pulse WWHINC, read clock pulse RCK, read reset pulse RVCLR, read line reset pulse RHCLR, read line address increment pulse RHINC, read enable signal RE, frame addition timing pulse FRAME It is generated and supplied to each of the field memories 12, 22, 32 or the aspect conversion unit 43, and the double speed vertical synchronizing signal 2VSYN is generated.
C, double speed horizontal sync signal 2HSYNC is generated and output.

The write clock pulse WCK is also used as a sampling clock for the A / D converters 11, 21, 31 and its frequency is, for example, a horizontal scanning frequency f _H × 910. That is, PA
In the L system, 14. The frequency is 22 MHz, and in the NTSC system, it is 14.32 MHz. Further, the read clock pulse RCK has a horizontal scanning frequency f _H × 910 ×
It is set to 2 x 4/3. That is, 37.92 MHz in the PAL system and 38.92 MHz in the NTSC system.
It is set to 19 MHz. In addition, the aspect conversion unit 43
Includes a frame signal addition circuit (Frame Add) and a blanking signal addition circuit (BLK Add) as a part thereof. The aspect conversion unit 43 includes a frame addition timing pulse FRAME from the timing controller 42.
Is supplied, and the frame signal is added to the video signal read from the field memories 12, 22, 32 according to the timing. When this frame-added timing pulse FRAME is at "H" level, the original digital video signal is replaced with a fixed level for displaying the frame. It is switched in synchronization with the read enable signal RE. Further, the width of the frame can be changed from the outside.

Next, the field memories 12, 22,
A block diagram of 32 is shown in FIG. The field memories 12, 22, 32 have the same configuration, and each has a memory cell array (Memory Cell ArrAy) 50, a write address pointer (WriteAddr Pointer) 51, a read address pointer (Read Addr Pointer) 52, and a write port ( A write port 53 and a read port 54. As shown in FIG. 4, the memory cell array 50 is configured by arranging cells having addresses assigned to pixel addresses in the horizontal direction and line addresses in the vertical direction arranged in a matrix. Address numbers are sequentially assigned from address 0 in the horizontal direction. This memory cell array 50
The digital video signal supplied via the write port 53 is sequentially written to the address address designated by the write address pointer 51, and the digital video signal sequentially read from the address address designated by the read address pointer 52 is , Read port 54
Is output to the outside of the field memory.

A write clock pulse WCK, a write reset pulse WVCLR, a write
A line reset pulse WHCLR and a write line address increment pulse WWHINC are supplied to control to write video signals in the order of address addresses. In this case, every time the write clock pulse WCK is supplied, the pointer is advanced by one in the horizontal direction as indicated by arrow D in FIG.
When the write reset pulse WVCLR is supplied, the pointer is made to return to the start address which is the head address as indicated by arrow A in FIG. 4, and the write line reset pulse
When WHCLR is supplied, the pointer is made to return to the head address of the horizontal line as shown by arrow B in FIG. 4, and when the write line address increment pulse WWHINC is supplied, as shown by arrow C in FIG. Then, the horizontal line address is incremented by one line and the pointer is moved one line down. In this way, digital video signals are sequentially written in the memory cell array 50.

The read address pointer 52 has a read clock pulse RCK, a read reset pulse RVCLR, and a read signal from the timing controller 42.
A line reset pulse RHCLR, a read line address increment pulse RHINC, and a read enable signal RE are supplied, and control is performed so that the addresses can be sequentially read. In this case, every time the read clock pulse RCK is supplied, the pointer is advanced by one in the horizontal direction as indicated by arrow D in FIG. 4, and the read reset pulse RVCLR
4 is supplied, the pointer is made to return to the start address which is the head address as shown by arrow A in FIG. 4, and when the read line reset pulse RHCLR is supplied, it is changed as indicated by arrow B in FIG. When the pointer is made to return to the head address of the horizontal line and the read line address increment pulse RHINC is supplied, the horizontal line address is increased by one line and the pointer is moved down by one line as shown by arrow C in FIG. Be moved. The read operation is performed when the read enable signal RE is "H" level, and the read operation is not performed when the read enable signal RE is "L". By controlling the read enable signal RE, the enable section is switched according to the display mode. In this way, digital video signals are sequentially read from the memory cell array 50.

By the way, the write clock pulse WC
K, the write reset pulse WVCLR, write lines Li <br/> set pulse WHCLR, write line address increment pulse WHINC is being output from the timing controller 42, these signals are as shown in Figure 16, the timing controller 42 It is generated by a part and the first PLL circuit 40. That is, as shown in FIG. 16, the first PLL circuit 40 includes a first phase comparator 81 and a first phase comparator 81 for comparing the phases of the horizontal synchronizing signal HSYNC of the input analog video signal and the write horizontal reference signal HREFW. Bowl 8
1 low-pass filter (L
PF) 82, and a first voltage controlled oscillator (VCO) 83 to which the error signal output from the first low pass filter 82 is supplied as a control signal.
A first counter 84 to which the oscillation output WCKO of
The first decoder 8 to which the count value of the first counter 84 is supplied
5 is a part of the timing controller.

The first counter 84 and the first decoder 85
Then, the frequency is divided by 910 to generate the horizontal reference signal HREFW. Since the loop including the first PLL circuit 40 operates so that the frequencies of the horizontal synchronizing signal HSYNC and the horizontal reference signal HREFW match, the first decoder 85
Write clock pulse WCK, write reset pulse WVCLR, write line reset pulse generated from
WHCLR and write line address increment pulse WWHINC are synchronized with the horizontal sync signal HSYNC. Further, the first decoder 85 has a write reset pulse WVCLR and a write reset pulse WVCLR.
Horizontal position adjustment data (WVCLR, WHCLR, WHINC DECODE Valuese) for adjusting the time position of line reset pulse WHCLR and write line address increment pulse WHINC
t) is supplied with the write reset pulse WVCLR in response to the horizontal position adjustment data, write lines Lise <br/> Ttoparusu WHCLR, write line address increment pulse
The WHINC time position is adjusted on a pixel-by-pixel basis, which
The horizontal display position of the displayed image is determined. That is, the horizontal display position of the image can be adjusted by changing the horizontal position adjustment data.

FIG. 5 shows a timing chart of the write clock pulse WCK, the write reset pulse WVCLR, the write line reset pulse WHCLR, and the write line address increment pulse WHINC. As shown in this figure, the write reset pulse WVCLR is applied to the field memories 12, 2
It is generated in synchronization with the vertical (V) synchronizing signal of the video signals written in Nos. 2 and 32, and as described above, the position of the pointer is reset to the start address by the write reset pulse WVCLR, and writing is started from the start address. Will be done. The write line reset pulse WHCLR and the write line address increment pulse WWHINC are generated at every horizontal cycle.In the case shown in the figure, the write line reset pulse WHCLR and the write line address increment pulse WWHINC.
And have the same pulse. Further, the write clock pulse WCK has the horizontal scanning frequency f _H × 9 as described above.
It is set to 10 . The portion indicated by E in this figure is enlarged and shown in FIG.

As shown in this figure, the period consisting of 910 amino write clock pulses WCK are one horizontal period, the write reset pulse WVCLR, write lines Li <br/> set pulse WHCLR, write line address increment pulse WHINC The time axis of is maximum Δ to the left and right around the standard position
It is possible to move to t. This movement position is variable according to the horizontal position adjustment data. That is, as shown in FIG., The write reset pulse WVCLR from the standard position to the right maximum position, the write line reset <br/> Toparusu WHCLR, write line address increment pulse WH
When INC is advanced, it shifts to the right from the standard position of the digital video signal by Δt and the field memories 12, 22, 32 are moved.
Therefore, the displayed image will be moved to the right.

The manner in which the writing position is shifted will be described with reference to FIG. 7. An area H surrounded by a thick broken line is an area that can be taken into the field memories 12, 22, 32, and an image shown by a solid line. F is a write reset pulse WVCLR, a write line reset pulse WHCLR,
This is an image written in the field memories 12, 22, 32 when the time axis of the write line address increment pulse WWHINC is at the standard position. When the time axis of these write reset pulse WVCLR, write line reset pulse WHCLR, and write line address increment pulse WWHINC is adjusted and delayed to the right by Δt, the images written in the field memories 12, 22, 32 are indicated by broken lines. The image G is shown. In this case, write reset pulse WVCLR,
The time axis of the write line reset pulse WHCLR and the write line address increment pulse WWHINC is delayed to the left maximum position shown in FIG. That is, since the data is written in the field memories 12, 22, 32 with a shift of Δt to the left from the standard position of the digital video signal, the displayed video is moved to the left.

Write reset pulse WVCLR, write
An image displayed when the time axis of the line reset pulse WHCLR and the write line address increment pulse WWHINC is adjusted and delayed by Δt will be described with reference to FIG. 10. FIG. 10A shows a case of normal display. The solid line shows the image I before adjustment and the broken line shows the image J after position adjustment, which is a mode in which frames are displayed on both sides of the image. In the case of the image J after the position adjustment, a part of the left side of the image is masked by the frame as illustrated, but the right side of the image is further added to the right side of the image. That is, it is possible to move only the image to the left in the normal display. Further, if the time axis is advanced by Δt, only the image can be moved to the right, contrary to the above. Further, FIG. 10B shows the case of the light display, the solid line shows the image K before adjustment, the broken line shows the image L after position adjustment, and in the mode in which the frame is displayed on the left side of the image. is there. In the case of the image L after position adjustment, a part of the left side of the image is masked by the frame as shown in the figure, but the right side of the image is further added to the right side of the image. That is, it is possible to move only the image to the left side in the light display. Further, if the time axis is advanced by Δt, only the image can be moved to the right, contrary to the above.

Then, the read clock pulse RCK
, Read reset pulse RVCLR, read line Li <br/> set pulse RHCLR, read line address increment pulse RHINC, read enable signal RE, but the frame addition timing pulse FRAME is outputted from the timing controller 42, these signals Fig As shown in FIG. 17, a part of the timing controller 42 and the second
And the PLL circuit 41 of FIG. That is,
As shown in FIG. 17, the second PLL circuit 41 includes a second phase comparator 8 for comparing the phases of the horizontal synchronizing signal HSYNC of the input analog video signal and the read horizontal reference signal HREFR.
6. Second phase smoothing the phase comparison output of the second phase comparator 86
It comprises a low-pass filter (LPF) 87 and a second voltage-controlled oscillator (VCO) 88 to which the error signal output from the second low-pass filter 87 is supplied as a control signal, and the oscillation output RCKO of this second VCO 88 is supplied. The second counter 89 and the second decoder 70 to which the count value of the second counter 89 is supplied are part of the timing controller 42.

The second counter 89 and the second decoder 70.
And 910.times.2.times.4 / 3 frequency division is performed to generate the read horizontal reference signal HREFR. In addition, this second PL
Since the loop including the L circuit 41 operates so that the frequencies of the horizontal synchronizing signal HSYNC and the read horizontal reference signal HREFW match, the read clock pulse RCK, read reset pulse RVCLR, and read line reset generated from the second decoder 89. Pulse RHCLR, read line address increment pulse RHINC, read enable signal RE, frame addition timing pulse FRAME is horizontal sync signal HSYN
Synchronized to C.

Further, the second decoder 70 is supplied with scan amount adjustment data (RE, FRAME DECODE Value set) for adjusting the time position of the read enable signal RE and the pulse width of the frame addition timing pulse FRAME. The time position of the read enable signal RE and the pulse width of the frame-added timing pulse FRAME are adjusted in pixel units according to the scan amount adjustment data, so that the frame width and the display section of the display image are displayed. Is variable so that overscan or underscan is possible. Incidentally, with respect to the horizontal position adjustment data and the scan amount adjustment data, suitability values are obtained in advance for various input images, and the control register (CONTROLE) shown in FIG.
REGISTER) 90, and the appropriate horizontal position adjustment data and scan amount adjustment data are externally given to the control register 90 via a system bus (SYSTEM Bus). The control register 90 constitutes a part of the timing controller 42. Note that both the adjustment data may be managed by software by passing through a bus.

The read clock pulse RCK, read reset pulse RVCLR, read line reset pulse RHCLR, read line address increment pulse RHINC,
A timing diagram of the read enable signal RE and the frame addition timing pulse FRAME is shown in FIG. As shown in this figure, the video signals read from the field memories 12, 22, and 32 are read twice to be double-speed video signals. Therefore, the read reset pulse RVCL
R is generated in synchronization with a vertical (2V) sync signal having a half cycle of the vertical (V) sync signal of the video signal. As described above, the read reset pulse RVCLR resets the pointer position to the start address. Then, the data is read from the start address. Read line reset pulse
RHCLR, read line address increment pulse RHINC is generated by the read clock pulse RCK × 910 × 4/3 pieces of the horizontal period, the read line Li <br/> set pulse RHCLR the case shown in the figure, the read line address increment pulse Same pulse as RHINC. Further, the read clock pulse RCK has the horizontal scanning frequency f _H × 910 × 2 × 4/3 as described above. The portion indicated by H in this figure is enlarged and shown in FIG.

In this figure, the read clock pulse
The cycle consisting of RCK 910 × 4/3 is one horizontal cycle (cycle of read line reset pulse RHCLR and read line address increment pulse RHINC), and read enable signal RE is read line reset pulse RHCL.
R or read line address increment pulse RHIN
The reading operation from the field memories 12, 22, 32 is interrupted by setting it to the “L” level in synchronization with C. Then, the frame addition timing pulse FRAME is set to "H" level for a predetermined period in synchronization with the read enable signal RE, and the level of the video signal in this period is switched to the level for displaying the frame. In addition,
The "H" level period of the frame addition timing pulse FRAME is the width of the frame of the display image, and this "H" level period is adjustable as shown in the figure so that the frame width can be changed. There is.

An image displayed when the frame width is changed will be described with reference to FIGS. 11 and 12. FIG.
(A) shows a case of normal display, which is a mode in which frames are displayed on both sides of an image. In the case shown, the frame addition timing pulse FRAME is "H".
The frame width is almost fixed because the mask is made by the frame in which the level period is expanded and parts of both sides of the video signal are expanded, and the deflection system is overscanned. Only will be overscanned and displayed. That is, only the video can be overscanned in the normal display. In this case, the timing of the read enable signal RE and the frame addition timing pulse FRAME is RE (normal display), FR
It is shown in FIG. 9 as AME (normal display).

Further, FIG. 11B shows a case of light display, which is a mode in which a frame is displayed on the left side of the image. Further, in the case shown in the drawing, the "H" level period of the frame addition timing pulse FRAME is widened and a part of the left side of the video signal is masked by the widened frame, and the deflection system is overscanned. Therefore, the frame width is almost fixed, but only the video is overscanned and displayed. That is, it is possible to overscan only the image in the light display. In this case, the timing of the read enable signal RE and the frame addition timing pulse FRAME is RE
9 (light display) and FRAME (light display).
Is shown in. As shown in the figure, in this case, since the frame is displayed on the left side, only the time position of the falling edge on the right side of the frame addition timing pulse FRAME can be adjusted.

FIG. 12A shows the case of normal display and the frame addition timing pulse FRAME.
This is the case where the "H" level period of is adjusted to be narrow, and a space is provided between both sides of the video signal and the narrowed frame. Further, since the deflection system is underscanned, the frame width is almost fixed, but only the image is underscanned. That is, it is possible to underscan only the image in the normal display. Further, FIG. 12B shows the case of the light display and the case where the period of the "H" level of the frame addition timing pulse FRAME is adjusted to be narrow, and there is a gap between the narrowed frame and the video signal. It is considered a space. Further, since the deflection system is underscanned, the frame width is almost fixed, but only the image is underscanned. That is, it is possible to underscan only the image in the light display.

As described above, the field memory 1
The video signal write / read operation is performed by using Nos. 2, 22 and 32. FIG. 13 shows the change over time of the write address and the read address. In this figure, the change in the address indicated by the broken line is the change in the write address output from the write address pointer 51, and the change in the address indicated by the solid line is the change in the read address output from the read address pointer 52. As shown in the figure, the change speed of the read address output from the read address pointer 52 is twice the change speed of the write address output from the write address pointer 51. That is, in the video signals written in the field memories 12, 22, 32, each one field is read twice.

The video signal read in this way is supplied to the aspect conversion section 43, and aspect conversion is performed. In this aspect conversion processing, the horizontal direction of the image is compressed to 3/4, frames are added to both the left and right sides of the image, the normal display mode shown in FIG. 14A is added, and the frame is added to the right side (b). Left display mode, shown in
Alternatively, it is a process of adding a frame on the left side and setting the display mode to one of the light display modes shown in (c).
If the aspect conversion process is not performed, the process shown in FIG.
As shown in FIG. 15A, the full display mode is displayed over the front surface of the display surface, and when the vertical direction of the image is expanded to 4/3, the central portion of the image is displayed as shown in FIG. 15B. Is in the zoom display mode in which is displayed over the entire display surface.

In the above description, the case where a video having a 4: 3 aspect ratio is displayed on a television having a CRT having an aspect ratio of 16: 9 has been described, but the present invention is not limited to the television device, It may be a device such as an adapter having only a function of "4: 3 to 16: 9 aspect conversion means", a VTR, a tuner, a descrambling decoder having the function.

[0044]

Since the present invention is configured as described above, in the video signal display method of the present invention, the timing can be adjusted so that the head writing position in the field memory can be adjusted, and the frame can be adjusted. Since the left and right positions of the display image can be moved while being fixed, it is possible to adjust the horizontal display position of the display image corresponding to the video signal sources of various conditions. Furthermore, if the time width of the frame signal can be adjusted, the width of the displayed frame can be adjusted. Therefore, by increasing the frame width and overscanning the deflection system, only the display image is overscanned. Alternatively, it is possible to underscan only the display image by reducing the frame width to undercancel the deflection system.

Further, since the video signal display device of the present invention is provided with the write pulse generating means capable of adjusting the timing of the write pulse supplied to the field memory, the left and right sides of the display image can be maintained with the frame fixed. The position can be moved. Therefore, it is possible to adjust the horizontal display position of the display image corresponding to the video signal sources of various conditions. Furthermore, since the time position of the write pulse output from the first decoder is adjusted by applying the horizontal position adjustment signal of the image displayed to the first decoder, the horizontal display of the display image can be easily performed. The position can be adjusted.

Furthermore, by applying a signal for adjusting the frame width of the image displayed on the display device to the second decoder, the time width of the frame signal output from the decoder is adjusted. Since the width of the frame to be adjusted can be adjusted, the frame width can be increased to overscan the deflection system, so that only the display image can be overscanned, or the frame width can be decreased to reduce the deflection system. By performing the under-can, it becomes possible to under-scan only the display image. Since the television device of the present invention includes the above-described video signal display device and display device, the left and right positions of the display image can be moved while the frame is fixed, so that the video signal source of various conditions can be obtained. Correspondingly, the horizontal display position of the display image can be easily adjusted, and the frame width is increased to overscan the deflection system to perform only the display image overscan. Alternatively, it is possible to underscan only the display image by reducing the frame width to undercancel the deflection system.

Therefore, according to the present invention, the frame width and the display position which meet the respective conditions are set so that the horizontal display position of the input image which is slightly different and the image loss after the aspect conversion for the effective image section do not occur. Can be set accurately. Further, since the amount of overscan can be minimized in accordance with each video signal, the effective video area can be maximized. Furthermore, if the frame width and video display position are all managed by software and partially released to the user as an adjustment means, it is possible to easily deal with input signal conditions that could not be grasped at the manufacturing stage. It can be possible.

[Brief description of drawings]

FIG. 1 is a block diagram of a television device according to the present invention.

FIG. 2 is a block diagram of a field double speed aspect conversion unit.

FIG. 3 is a block diagram of a field memory.

FIG. 4 is a diagram showing operations of a write address pointer and a read address pointer.

FIG. 5 is a diagram showing each timing at the time of writing.

FIG. 6 is a timing diagram showing an enlarged part of the timing at the time of writing.

FIG. 7 is a diagram showing a writing position of a video signal written in a field memory.

FIG. 8 is a diagram showing each timing at the time of reading.

FIG. 9 is a timing diagram showing an enlarged part of the timing at the time of reading.

FIG. 10 is a diagram showing a display image when the horizontal position is adjusted.

FIG. 11 is a diagram showing a display image when an overscan display is performed.

FIG. 12 is a diagram showing a display image when underscan display is performed.

FIG. 13 is a timing chart showing changes in write address and read address.

FIG. 14 is a diagram showing each display mode.

FIG. 15 is a diagram showing another display mode.

FIG. 16 is a diagram showing a configuration for generating a write side timing pulse.

FIG. 17 is a diagram showing a configuration for generating a read side timing pulse.

FIG. 18 is a diagram showing a basic configuration of a control register.

FIG. 19 is a diagram illustrating adjustment in display of a CRT.

FIG. 20 is a diagram illustrating a problem of adjustment in display of a conventional CRT.

FIG. 21 is a diagram showing a display of a CRT for explaining the purpose of the present invention.

[Explanation of symbols]

3 Field double speed aspect conversion circuit 9-1 CRT 11, 21, 31 A / D conversion circuit 12, 22, 32 Field memory 40 First PLL circuit 41 Second PLL circuit 42 Timing controller 43 Aspect conversion unit WCK Write clock pulse WVCLR Write reset pulse WHCLR Write line reset pulse WHINC Write line address increment pulse RCK Read clock pulse RVCLR Read reset pulse RHCLR Read line reset pulse RHINC Read line address increment pulse RE Read enable signal FRAME Frame addition timing pulse

Claims (6)

(57) [Claims] 1. Digital video signals of various broadcasting systems are transmitted.
In the field memory according to the write timing pulse
Writing, the digital image written in the field memory
The image signal is read according to the read timing pulse, and the digital image read from the field memory is read.
The aspect ratio of the image signal is changed by the aspect conversion means.
In other words, the frame signal according to the frame addition timing pulse
And the write time of the input digital video signal.
It is set for each broadcasting system according to the ming pulse.
The position adjustment pulse can be adjusted based on the appropriate value
The digital image on the field memory.
To be able to adjust the relative writing position of the image signal
In addition, the read timing pulse and the frame
To fix the timing of the timing pulse
A video signal display method for applying a video signal to a display means having an aspect ratio different from the aspect ratio of an input digital video signal. 2. The video signal display method according to claim 1, wherein the time width of the frame signal is adjustable. 3. A field memory into which digital video signals of various broadcasting systems are written, and a frame signal of a frame displayed on at least one side of an image displayed on the display means according to a frame addition timing pulse. > a frame signal generating means for generating, the aspect converting unit for converting the aspect ratio of the video signal read from said field memory, so that it can adjust the relative position of writing the digital video signal on the field memory , Write timing pulse with adjustable timing ,
Position adjustment adjustable according to the write timing pulse
The adjustment pulse and before being written to the field memory
Readout timing pattern for reading digital video signals
And a timing pulse generating means for generating a pulse, the write pair of the input digital video signal
It is set for each broadcasting system according to the ming pulse.
Adjusting the position adjustment pulse based on the appropriate value
From the digital on the field memory
Allows you to adjust the relative writing position of the video signal.
And the read timing pulse and the flag.
The timing of the frame-added timing pulse is fixed
Aspect ratio of the input digital video signal
A video signal is applied to a display device with an aspect ratio different from the ratio.
Video signal display apparatus being characterized in that the so that. 4. A first phase comparator to which the horizontal synchronizing signals of the various broadcasting systems are inputted to one side and a first decoder output is applied to the other side, and a comparison output of the first phase comparator. A first low-pass filter that smoothes an error signal; a first voltage-controlled oscillator whose oscillation frequency is controlled according to the error signal from the first low-pass filter;
Frequency dividing means for dividing an output pulse from the voltage controlled oscillator, wherein the dividing means comprises a first counter and the first decoder to which the count value from the first counter is input. The horizontal position adjustment signal of the image displayed on the display means is applied to the first decoder, and the time position of the write timing pulse output from the first decoder is adjusted. The video signal display device according to claim 3, wherein: 5. A second phase comparator to which the horizontal synchronizing signals of the various broadcasting systems are inputted to one side and a second decoder output is applied to the other side, and a comparison output of the second phase comparator is smoothed. A second low-pass filter which is an error signal, and
A second voltage-controlled oscillator whose oscillation frequency is controlled according to the error signal from the low-pass filter; and frequency-dividing means for frequency-dividing the output pulse from the second voltage-controlled oscillator. It is composed of a second counter and the second decoder to which the count value from the second counter is input, and a signal for adjusting the frame width of the image displayed on the display device is applied to the second decoder. 5. The video signal display device according to claim 3, wherein the time width of the frame signal output from the second decoder is adjusted by doing so. 6. A television set comprising the video signal display device according to claim 3 and a display device.