JPH11313269A - Video signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent vertical resolution from being deteriorated in the case that two-screen simultaneous display and double speed conversion are both conducted. SOLUTION: Signals of main and sub screens are respectively fed to a horizontal compression circuit 11 (screens 20A, 20B). The circuit 11 compresses the respective signals horizontally depending on each display size of the main and sub images and the signals are synthesized into signals for one screen (screen 21). The synthesis signal is fed to a double speed conversion section 2, where the horizontal frequency is converted twice and reinforcement processing is applied to the vertical resolution. The signal that is double-speed-converted and whose vertical resolution is reinforced is fed to a screen division/vertical compression circuit 17, where the signal is vertically compressed by applying vertical filter processing to the signal depending on a display size of the main and sub screens (screen 22). Since no vertical filter processing is conducted before double speed conversion, the similar vertical resolution to that for processing for one screen only is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a video signal processing device that achieves high image quality by doubling the number of scanning lines and doubling the number of scanning lines, and that displays two screen images in the same screen.

[0002]

2. Description of the Related Art In recent years, the screen size of television receivers has been increasing, and at the same time, higher image quality has been demanded. For this reason, for example, in the NTSC system, the horizontal frequency is doubled from approximately 15.75 KHz to 31.5 KHz.
In many cases, double speed display is performed. By doubling the horizontal frequency, the number of scanning lines in one screen is doubled.
Higher image quality can be achieved by interpolating the increased scanning lines with the original scanning lines. Further, at this time, a new image information is created from the original image information based on a result learned in advance to obtain a high resolution, and a DRC (Digital Reality Cre
ation) is also in practical use.

On the other hand, a large number of television receivers that simultaneously display two screen images on one CRT screen have appeared. The user can enjoy the main video on the first screen (main screen), and at the same time, can enjoy, for example, a counter program on the second screen (sub-screen). Such a display method is called picture & picture (P & P), and the main screen is displayed in a predetermined area on one side of the screen, and the sub-screen is displayed on the other side. The main screen and the sub-screen can be displayed, for example, at the aspect ratio of the original screen, respectively.

[0004] There is also a television receiver which performs both high-quality display by double-speed display and simultaneous display of two screens. FIG. 4 shows an example of a configuration according to the prior art in which both double-speed display and two-screen display are performed.
Here, the configuration for performing the two-screen display will be mainly described.
Hereinafter, the video signal of the main screen is referred to as A. ch (A channel) signal and the sub-screen video signal This is referred to as a ch (B channel) signal.

A. ch signal and B. The channel signals are supplied to A / D converters 100A and 100B, respectively, and are converted into digital signals. A. In ch
Digitally converted A. The ch signal is supplied to the horizontal / vertical filter 101A and is filtered. By this filter processing, A.I. Reduction processing of the ch signal in the horizontal and vertical directions is performed, and data is formed with the size of the actual display image of the main screen in the two-screen display. This reduction processing is performed by a digital filter by thinning out predetermined pixels, conversion by weighting, or the like. Filtered A. The ch signal is stored in the memory 102A.

B. The ch. The same processing as for the ch signal is performed. That is, the A / D converter 1
00B digitally converted at B.00B. The ch signal is filtered by the horizontal / vertical filter 101B and reduced.
B. reduced The ch signal is stored in the memory 102B.

[0007] The stored signals are read from each of the memories 102A and 102B. The reading of this signal is performed, for example, as described in A. Synchronization of the signals is performed based on the synchronization of the channel signals. Memory 102A, 102
B. The signals read from B are respectively
3A and 103B, the filters 101A and 10A are used.
The image quality degraded by the processing in 1B is compensated and supplied to the synthesis / output processing circuit 104.

In the combining / output processing circuit 104, ch signal and B. The channel signal is synthesized and output as a signal of one screen. The signal output from the synthesizing / outputting circuit 104 is converted into an analog video signal by a D / A converter 105, and a double-speed conversion circuit (scan converter) 106
Supplied to Then, the double frequency conversion circuit 106 doubles the horizontal frequency and performs, for example, scanning line interpolation to reinforce the vertical resolution. The double speed conversion circuit 10
6 is a digital system, the combining / output circuit 104
Is directly supplied to the double speed conversion circuit 106 without passing through the D / A converter 105.

[0009]

As described above, conventionally, in the two-screen synthesis processing, a large amount of filter processing is required in order to reduce the image in the horizontal and vertical directions. Therefore, there is a problem that the resolution is reduced as compared with the processing on one screen, and the image quality is deteriorated.

When two screens of video are simultaneously displayed on one screen by P & P or the like, it is necessary that both screens have the same image quality. As described above, when further performing the double-speed conversion processing, if an attempt is made to perform two-screen synthesis after the double-speed conversion processing,
A. Two screen signals to be synthesized ch signal and B. A double-speed conversion processing circuit is required for each of the channel signals,
The circuit scale becomes enormous and the cost rises significantly.
Therefore, conventionally, double-speed conversion processing has been performed after performing two-screen synthesis.

In the double-speed conversion process, the vertical resolution is enhanced as the number of scanning lines increases. However, in the related art, the vertical filter processing is performed during the reduction processing, and the resolution in the vertical direction is deteriorated. Therefore, conventionally, since the double-speed conversion processing is further performed on the signal whose resolution in the vertical direction has deteriorated, there is a problem that the vertical resolution further deteriorates after the conversion.

As described above, conventionally, when both double-speed display and dual-screen display are performed at the same time, there is a problem that the resolution in the vertical direction is poor and the image quality is significantly deteriorated with respect to the original video. Was.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a video signal processing apparatus in which the vertical resolution is not deteriorated even when performing two-screen simultaneous display and double-speed conversion.

[0014]

According to the present invention, in order to solve the above-mentioned problem, the horizontal frequency at the time of display can be doubled, and two video signals can be simultaneously displayed on one screen. In a simple video signal processing apparatus, a horizontal compression unit for compressing each of two input video signals in the horizontal direction and combining them into one video signal, and a horizontal frequency of one video signal output from the horizontal compression unit, A video signal processing apparatus comprising: a double-speed conversion unit that converts the video signal to a double speed; and a vertical compression unit that vertically compresses a video signal output from the double-speed conversion unit.

As described above, the present invention compresses each of two input video signals in the horizontal direction and synthesizes them into one video signal, and doubles the horizontal frequency of the synthesized video signal. After the conversion, the video signal is compressed in the vertical direction, so that only one double speed conversion means is required and the deterioration of the image quality in the vertical direction is suppressed.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 conceptually shows an example of a configuration and a screen image according to the present invention. The configuration shown in FIG. 1A includes a two-screen combining unit 1 and a double-speed converting unit 2.
Consists of FIG. 1A shows that a signal is input from the uppermost stage and processing is performed in order from top to bottom, and FIG. 1B shows a screen image by processing at a corresponding stage of FIG. 1A. Have been.

A. The main screen video signal A. ch signal is A
The B./D converter 10A supplies the B./D.
The ch signal is supplied to the A / D converter 10B. A. ch signal and B. Each of the ch signals is
For example, a video signal based on the NTSC system is shown in FIG.
As shown in the screens 20A and 20B, one screen having a predetermined aspect ratio is formed. Scanning is interlaced or progressive (non-interlaced)
The number of scanning lines per frame is 525 in any case.

Here, the supplied video signal is
The component signals are Y / C-separated, and are shown as a single signal in FIG. 1A with the path omitted. Also,
In the following description, similar processing is performed on each of the separated Y and C signals.

A / D converters 10A and 10B convert the A.D. ch. The ch signal is
Each is supplied to the horizontal compression circuit 11. In the horizontal compression circuit 11, the A.P.A. ch. c
The h signal is compressed in the horizontal direction. The horizontal compression circuit 11 has, for example, a horizontal filter. ch signal and B. For each of the ch signals, compression in the horizontal direction is performed by thinning out predetermined pixels in accordance with the reduction ratio of the display screen size or converting by weighting.

A. Compressed horizontally. ch.
The ch signal is further synthesized into a signal of one screen. This synthesis is described, for example, in A. channel signal based on the synchronization of the B.ch signal. This is performed by changing the ch signal synchronously. The output of the horizontal compression circuit 11, as shown as screen image 21 in FIG. ch. Each of the ch signals is a signal obtained by performing only horizontal compression while maintaining the original screen size in the vertical direction. A. each compressed horizontally. ch screen images 21A and B.B. A combined screen image 21 is formed with the screen image 21B of the channel.

The signal output from the horizontal compression circuit 11 has 525 scanning lines per frame in either the interlaced or progressive system.

This signal is supplied to a TBC (Time Base Corrector) 13 of the double speed conversion unit 2 via a switch circuit 12 so that the timing is adjusted.
Is supplied to the double speed conversion circuit 15 through

In the double speed conversion circuit 15, the horizontal frequency of the supplied video signal is doubled. Accordingly, the number of scanning lines is doubled. For a video signal whose number of scanning lines has been doubled, image quality improvement processing is performed by a predetermined method such as scanning line interpolation or enhancement of vertical resolution. Double speed conversion circuit 1
By applying the above-mentioned DRC as the number 5, higher image quality can be obtained.

The signal double-speed converted by the double speed conversion circuit 15 is supplied to a screen division / vertical compression circuit 17 via a switch circuit 16. In this circuit 17, one screen compressed and synthesized in the horizontal direction by the above-described horizontal compression circuit 11 is A.D.
ch signal and B. It is divided into two based on the channel signal. Then, according to the initially set display screen sizes of the main screen and the sub screen, each of the two divided signals is compressed in the vertical direction.

The screen image 22 shown in FIG. 1B is formed by the signal output from the screen division / vertical compression circuit 17. Screen image 21 by horizontal compression circuit 11
A. compressed horizontally as in A. ch. ch
Each of the signals is, in this example, the original screen image 20.
Circuit 17 so that the aspect ratios A and 20B are obtained.
Is compressed vertically. These A. ch. c
The screen signals 22A and 22B are obtained by the h signal, and 1
A screen image 22 of the screen is formed.

The output of the screen division / vertical compression circuit 17, which has been compressed in the horizontal and vertical directions, is supplied to a D / A converter 19 via a switch circuit 18 and converted into an analog video signal (component signal). It is converted and output.

As described above, in the present invention, after the input signals for two screens are subjected to horizontal compression,
The horizontal frequency double speed conversion and the vertical resolution reinforcement processing are performed. Then, after that, the signal is divided into each of two screens and compressed in the vertical direction. The signal before the compression processing in the vertical direction is performed is subjected to the double speed conversion of the horizontal frequency and the enhancement processing of the vertical resolution. Therefore, after the double-speed conversion, compression in the vertical direction can be performed with the same vertical resolution as in the case of one-screen display.

In the configuration shown in FIG. 1A, when the switch circuits 12 and 18 perform, for example, display of only one screen, A.D. It is used when performing double-speed conversion by inputting only ch. By selecting the terminal b in the switch circuits 12 and 18, B.B. ch signal path, and Only the double speed conversion processing can be performed on only the ch signal. Switch circuit 1
No. 4 is for canceling the TBC 13.
Further, when the scanning method of the input video signal is the progressive method, the switch circuit 16 selects the terminal f and cancels the double-speed conversion circuit 15.

FIG. 2 shows the structure of FIG. 1A more specifically. In FIG. 2, portions corresponding to those in FIG. 1A are denoted by the same reference numerals, and detailed description thereof will be omitted. A. ch. ch signal is A / D converter 1
The signals are converted into digital signals by 0A and 10B, respectively, and supplied to the horizontal compression circuit 11.

In this example, the horizontal compression circuit 11 controls the A.P. c
For the h signal path, the horizontal filter / interpolator 30
A and a line memory 31 are provided. A horizontal filter / interpolation circuit 30B and a field memory 32 are provided for the channel signal path. In the horizontal filter / interpolation circuits 30A and 30B, filter processing and interpolation processing in the horizontal direction are performed to prevent aliasing of sampling. The output of the horizontal filter / interpolation circuit 30A is written to the line memory 31 for each scanning line. On the other hand, the output of the horizontal filter / interpolation circuit 30B is written to the field memory 32 for each field.

A. ch. Memory 3 for ch signal
Reading from 1 and 32 is performed as follows.
B. The ch signal is A. The clock synchronized with the reading of the line signal 31 from the line memory 31, A. A signal one field before the ch signal is read from the field memory 32. At this time, A. ch signal and B. The ch signal is read out from the line memory 31 and the field memory 32 while being thinned out in the horizontal direction according to the horizontal size of each screen.

The A.D data read from the memories 31 and 32 ch. The ch signal is supplied to the synthesizing / output circuit 33 and is synthesized into one video signal. In addition, synthesis
In the output circuit 33, the A.I. ch signal and B. The horizontal interpolation processing may be performed on each of the ch signals.

Since the processing up to this point does not involve a vertical filter or interpolation processing, the vertical resolution does not deteriorate. That is, substantially the same vertical resolution is maintained as when only one screen is processed.

The output of the synthesizing / output circuit 33 is converted to the double-speed converter 2
Supplied to As described above, in the double speed conversion unit 2, the horizontal frequency is doubled (in the case of NTSC, about 15.
(Conversion from 75 KHz to 31.5 KHz), and a vertical resolution enhancement process is performed. If the vertical resolution enhancement processing is performed by the above-described DRC, higher image quality can be obtained. The output of the double speed conversion circuit 2 is supplied to a screen division / vertical compression circuit 17.

The screen division / vertical compression circuit 17 includes vertical filter / interpolation circuits 40A and 40B and memories 41A and 4B.
1B and a synthesis / output processing circuit 42. The output of the double speed conversion circuit 2 is divided into two paths and supplied to the vertical filter / interpolation circuits 40A and 40B, respectively. If the vertical filter / interpolation circuit 40A channel signal, and the vertical filter / interpolation circuit 40B It corresponds to the ch signal. Vertical filter / interpolators 40A and 40B
, A similar process is performed. ch signal and B. c
Since the size displayed on one screen differs from that of the h signal, the path is divided in this way.

That is, the vertical filter / interpolation circuit 40A
In, thinning processing, filtering processing, and interpolation processing are performed according to the display size of the main screen in the vertical direction. Similarly, in the vertical filter / interpolation circuit 40B, thinning processing, filter processing, and interpolation processing according to the vertical display size of the sub-screen are performed.

The output of the vertical filter / interpolation circuit 40A is
The output of the vertical filter / interpolation circuit 40B is written to the memory 41A, respectively. By the way, in the horizontal compression circuit 11, the horizontal display size of each of the main screen and the sub-screen is already determined. Therefore, data is written into the memories 41A and 41B according to the horizontal display size of the main screen and the sub-screen.

That is, only a range corresponding to the main screen is selected and data is written into the memory 41A. Similarly, in the memory B, only the range corresponding to the sub-screen is selected and data is written. Further, the reading of data from the memories 41A and 41B is performed in accordance with the synchronization determined as the output signal corresponding to the display range of the main screen and the sub-screen in one screen.

Thus, the memories 41A and 41B
The video signals of the main screen and the sub-screen read from the ch. The ch signals are synthesized and
The video signal is supplied to the output processing circuit 42 and synthesized as a video signal of one screen. In a region where the main screen and the sub-screen are not displayed, for example, a blanking signal can be output. The video signal output from the synthesis / output processing circuit 42 is converted into an analog video signal by the D / A converter 19 and output.

In the example shown in FIG. 2, similarly to the example shown in FIG. 1A, a bypass path is provided so that double-speed conversion processing can be performed in one-screen display (dotted line in FIG. 2). Route).

In the above description, data is written in the memories 41A and 41B in accordance with the horizontal display size of each of the main screen and the sub-screen. However, this is not limited to this example. For example, the memories 41A, 41
Data for one screen may be written to B, and a range may be selected at the time of reading in accordance with the display size of the main screen and the sub-screen.

Further, in the above description, the vertical filter / interpolation circuits 40A and 40B are provided for each of the main and sub-screens, but this is not limited to this example. That is, if a sufficient processing speed can be ensured, it is possible to perform processing for two channels by, for example, time division with one vertical filter / interpolation circuit.

FIG. 3 shows an example of a configuration in which the double-speed conversion and the two-screen combining processing shown in FIGS. 1A and 2 are applied to an actual television receiver system. A television broadcast wave is received by the antenna 50,
The video signal and the audio signal are transmitted via the tuner block 51 and the VIF block 52. The audio signal is supplied to an audio signal processing unit (not shown).

The video signal output from the VIF block 52 is supplied to a video switch circuit 54. In this television receiver, a video output from an external device such as a VTR device or a DVD playback device can be connected to the terminal 53. The video signal from the external device supplied from the terminal 53 is supplied to the video switch circuit 54.

The video signal supplied to the video switch circuit 54 is selected and the two channels A.C. ch.
ch. With the signal from the VIF block 52 and the signal from the terminal 53, the main screen and the sub-screen are
Can be assigned freely. These A. ch. The channel video signal is supplied to YC separation circuits 55A and 55B, respectively.

A. supplied to the YC separation circuit 55A. ch
The signal is separated into a luminance signal Y and a chrominance signal C and supplied to a color decoder / synchronization separation circuit 56A. The supplied luminance signal Y and color signal C are decoded by the color decoder / synchronization separation circuit 56A, and are converted into signals suitable for digital processing, such as component signals. Further, the horizontal and vertical synchronization signals are extracted from the luminance signal Y by the circuit 56A.

The video signal output from the video switch circuit 54 The YC separation circuit 55B and the color decoder / synchronization separation circuit 56B also perform A. ch
The same processing as for the signal is performed.

Color decoder / synchronization separation circuits 56A, 5
6A respectively output from A.6. ch. The channel signal is supplied to the double speed conversion / two screen processing block 57. The double-speed conversion / two-screen processing block 57 includes the two-screen synthesis unit 1 and the double-speed conversion unit 2 shown in FIGS. 1 and 2 described above. In this block 57, the above-described processing is used to set A.D. ch. The two-screen combining process and the double-speed conversion process of the channel are performed.

The output of the double-speed conversion / two-screen processing block 57 is supplied to a video processing / RGB conversion circuit 58, where video processing such as image quality adjustment is performed, and a video signal composed of a luminance signal Y and a color signal C is output, for example. Matrix processing is performed, and the signals are converted into RGB three primary color signals. The RGB signals are
It is supplied to the CRT 60 via the RGB output circuit 59.

On the other hand, in the synchronous processing / deflection processing circuit 61,
A deflection signal for driving the CRT 60 is generated based on a synchronization signal used in the video processing / RGB conversion circuit 58, and a process of synchronizing scanning lines when projecting the video signal on the CRT 60 is performed. Synchronous processing / deflection processing circuit 61
, The vertical deflection output circuit 62 and the horizontal deflection output circuit 63 generate sawtooth currents for performing vertical deflection and horizontal deflection of the CRT 60, respectively. These signals are supplied to the vertical and horizontal deflection coils of the CRT 60, respectively, and the CRT 60 is driven.

In the above description, the present invention has been described as being applied to a video signal according to the NTSC system. However, the present invention is not limited to this example, and can be applied to video signals according to other systems.

[0052]

In general, since the double speed conversion is a process for generating a signal between scanning lines of an original signal, the higher the resolution of the input signal, the better the result. However, in the conventional two-screen display, since the double-speed conversion is performed on the signal that has already been subjected to the filter and the interpolation processing in the vertical direction, the signal generated by the interpolation is further interpolated.
As a result of double processing, the image quality was significantly degraded.

As described above, according to the present invention,
The filtering process on the video signal is performed only in the horizontal direction before the double speed conversion of the horizontal frequency, and the filtering process in the vertical direction is performed after the double speed conversion. Therefore, for example, if the scanning line interpolation processing at the time of the double speed conversion processing is performed with high image quality, the filtering processing in the vertical direction is performed from that state, so that the compression in the vertical direction can be performed while suppressing the deterioration of the resolution. effective.

According to the present invention, since the vertical filtering is performed after the double-speed conversion and the two-screen synthesis is performed, the image quality is further improved by improving the performance of the double-speed conversion. There is an effect that can be.

Further, according to the present invention, since double speed conversion is performed after two video signals are combined into one, there is an effect that only one double speed conversion processing circuit is required.

Furthermore, according to the present invention, since the block of the double speed conversion processing is taken into the block of the two-screen synthesis processing, when the device is considered as a device, these blocks are not divided and are divided into one. Since it can be realized with one device, there is an effect that the cost is low.

[Brief description of the drawings]

FIG. 1 is a diagram conceptually showing an example of a configuration and a screen image according to the present invention.

FIG. 2 is a block diagram more specifically showing a configuration according to the present invention.

FIG. 3 is a block diagram showing an example of a configuration in which the double speed conversion and the two-screen combining process according to the present invention are applied to an actual television receiver system.

FIG. 4 is a block diagram showing an example of a configuration for performing both double-speed display and two-screen display according to the related art.

[Explanation of symbols]

1 ... 2 screen synthesis unit, 2 ... double speed conversion unit, 11 ...
.Horizontal compression circuit, 15 double speed conversion circuit, 17
Screen division / vertical compression circuit, 30A, 30B ... horizontal filter / interpolation circuit, 31 ... line memory, 32 ...
・ Field memory, 33 ・ ・ ・ Synthesis / output processing circuit,
40A, 40B ... vertical filter / interpolation processing circuit, 4
1A, 41B: memory, 42: synthesis / output processing circuit

Claims (3)

[Claims] A video signal processing apparatus capable of converting a horizontal frequency at the time of display to twice and displaying two video signals simultaneously on one screen. Horizontal compression means for compressing in the horizontal direction to synthesize one video signal; double speed conversion means for converting the horizontal frequency of the one video signal output from the horizontal compression means to twice; A vertical compression means for compressing the output video signal in the vertical direction. 2. The video signal processing device according to claim 1, wherein said vertical compression means performs said vertical compression in accordance with each of said two input video signals. Processing equipment. 3. The video signal processing apparatus according to claim 1, wherein when only one video signal is displayed, only the process of converting the horizontal frequency to twice is performed. Video signal processing device.