JP3538851B2 - Video signal processing circuit and display device using the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing circuit provided with a double speed conversion circuit.

[0002]

2. Description of the Related Art In a video display device using a liquid crystal panel,
To display high-resolution signals such as HDTV, please refer to JA.
PAN DISPLAY'89 Proceedings p256-25
9 "High Definition Liquid
As described in “Crystal Projection TV”, a digital signal processing circuit is used.

FIG. 11 shows an example of a conventional signal processing circuit.
The input signal 200 is converted into a digital signal by an AD converter 201, expanded by, for example, 6 times by a time axis expansion circuit 202, then converted into interlaced scans by a double speed conversion circuit 203, and converted by a gamma correction circuit 204 into a liquid crystal panel. After correcting the gamma according to the characteristics, the signal is returned to an analog signal by the DA converter 205, and the liquid crystal panel 206
Transmitted to and displayed.

Here, assuming that a high-definition signal such as an HDTV signal is displayed on a liquid crystal panel having 1440 pixels in the horizontal direction, for example, the clock of the video signal is 50 MHz.
Since the frequency becomes very high, ie, z or more, the drive circuit (not shown) of the liquid crystal panel cannot be operated.
The video signal cannot be displayed. Therefore, the liquid crystal panel is divided into, for example, six blocks in the horizontal direction, independent drive circuits are provided for each of the blocks, and signals are simultaneously written in parallel to lower the frequency of each block to operate the drive circuits. A signal is displayed on the panel.

Referring to FIG. 11, a video signal is separated into six blocks by a time base expansion circuit 202. FIG. 12 shows the timing. The input signal 210 is digitized by the AD converter 201, and here indicates an effective scanning period of one scanning line. The time axis expansion circuit 202 divides the input signal 210 into six blocks, expands the input signal six times with respect to the input, and corresponds to each of the divided blocks of the liquid crystal panel 206 as indicated by a to f of the output signal 211. Output as a signal.

An HDTV having 1035 effective scanning lines
When a signal is displayed on a liquid crystal panel having 1035 pixels in the vertical direction, one scanning line can correspond to one pixel in the vertical direction, but only one half of the scanning lines are sent in one field time. Therefore, it takes two fields, that is, one frame, to display the entire screen.
Flicker occurs due to the charge retention characteristics of the liquid crystal panel. Therefore, the double speed conversion circuit 203 doubles the scanning speed to generate a signal corresponding to two fields in one field time by interpolation so that the entire screen can be written in one field time.
FIG. 13 is a timing chart showing the operation of the double speed conversion circuit 203, wherein a1, b1, a2, b2, a3, b3,.
..., when signals are input in the order of an, bn, a1, a
2, a3, ..., an, b1, b2, b3, ..., bn
, And multiplexing and inputting data of two scanning lines, an output signal of double speed conversion can be obtained. However, since the input signal is sent only one scanning line at a time, the other must supply an interpolation signal.

The simplest method is to convert the data of the same scanning line into two scanning lines having the same data as an interpolation signal. As another method, Japanese Patent Application Laid-Open No. H4-1578
86, there are inter-line interpolation using the average value of the previous scanning line and the current scanning line, and inter-field interpolation using the scanning line one field before. As the line, the former requires a line memory, and the latter requires a field memory. In addition, motion adaptive interpolation is used, which detects the motion of each part of the screen, uses high-resolution inter-field interpolation for the stationary part, and switches to inter-line interpolation so that the moving part does not become a double image. is there. These operations are all performed in synchronization with the input video signal.

[0008]

Due to the above configuration, although omitted in FIG. 11, the number of double-speed conversion circuits 203, gamma correction circuits 204, and DA converters 205 is the same as the number of blocks, that is, In the description, six circuits are required, and there is a disadvantage that the scale is increased.

Further, since all parts are configured to operate in accordance with the timing of an input video signal, if, for example, an HDTV is designed to be displayed on a liquid crystal panel, other signals having different scanning frequencies are not displayed. There was a problem that it could not be done. For the purpose of displaying on a CRT, see Nikkei Electronics '92 .8.3.
(No. 560) pp. 154 to 156, which are described in “Scan Converters with Multifunctionalization”. However, when used for display on a liquid crystal panel, the output signal and the pixel of the panel are not considered to match each other. There was a problem that display quality was inferior.

Accordingly, the present invention is to solve such a problem, and an object of the present invention is to provide a video display device using a liquid crystal panel which is small-scale and can display signals of various scanning frequencies without deterioration. That is, to realize a video signal processing circuit.

[0011]

A video signal processing circuit according to the present invention comprises: an AD converter for converting an input video signal into an A / D signal;
A first field memory and a second field memory in which the input and output for storing the output of the converter are asynchronous, a conversion means for converting the output of the first and second field memories at double speed, and the first and second field memories Means for locking the write clock of the input video signal to the synchronization signal of the input video signal, setting means for setting the write enable timing of the first and second field memories, and the read enable timing of the first and second field memories, Setting means for setting the switching between the case of using the output of the AD converter as the input of the second field memory and the case of using the output of the first field memory in accordance with the type of the input video signal. Features.

Further, an image display device using a liquid crystal panel according to the present invention includes an AD converter for AD-converting an input image signal, and an AD converter.
A first field memory and a second field memory in which the input and output for storing the output of the AD converter are asynchronous, conversion means for converting the outputs of the first and second field memories at double speed, and inputting the output of the conversion means Gamma correction means, and a time axis expansion means that receives the output of the correction means as input,
Means for locking the write clock of the first and second field memories to the synchronizing signal of the input video signal, write enable timing setting means for setting the write enable timing of the first and second field memories, A write enable timing setting means for setting a read enable timing of the second field memory; and the AD as an input to the second field memory.
Switching between the case where the output of the converter is used and the case where the output of the first field memory is used is determined by the input video signal.
Switching setting means for performing setting in accordance with the type of signal, setting storage means for storing the setting state of the write enable timing setting means, the setting state of the read enable timing setting means, and the setting state of the switching setting means for each input video signal. It is characterized by having.

[0013]

[0014]

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment according to the present invention. In the figure, those having the same reference numerals as those in FIG. 11 have the same functions. The input signal 200 is converted into a digital signal by the AD converter 201, and is input to the frame memory 1, which is the first storage means, and whose input and output are asynchronous. Also, the input signal 200
Are also input to the sync separation circuit 7, and a sync signal 5 consisting of a horizontal sync signal (hereinafter HD) and a vertical sync signal (hereinafter VD).
1 are separated. Although not shown, depending on the type of video signal, a video signal may be separated from HD and VD in advance and transmitted. It is clear that the connection should be made as VD. HD and VD are input to the write timing circuit 3 and the read timing circuit 4. From the write timing circuit 3, a write timing signal 52 for writing the output of the AD converter 201 to the frame memory 1 is input. Further, through the frequency dividing circuit 9, A
It is also connected to the D converter 201. A read timing signal 53 for reading the frame memory 1 is sent from the read timing circuit 4 to the frame memory 1.
Has been entered. Although not shown, the stages subsequent to the frame memory 1 are also connected so as to operate by the read timing circuit 53. The operation setting circuit 8 sets the operation of the frame memory 1. Further, the I / O bus 54 of the CPU 5 is connected to the write timing circuit 3, the read timing circuit 4, the operation setting circuit 8, and the frequency dividing circuit 9. Further, a data memory 6 as a second storage means is connected to the CPU 5 .

The double speed conversion circuit 2 operates in the same manner as the double speed conversion circuit 203 described in the background art.

The output of the frame memory 1 is subjected to scan line conversion by the double speed conversion circuit 2 and gamma correction by the gamma correction circuit 204 in accordance with the characteristics of the liquid crystal panel. After that, the signal is converted back to an analog signal by the DA converter 205 and transmitted to the liquid crystal panel 206 for display. Although six circuits are required for the DA converter 205, only one circuit is shown in FIG.

As described above, since the time base expansion circuit 202 is located after the gamma correction circuit 204, the liquid crystal panel is divided into, for example, six blocks in the horizontal direction, and independent drive circuits are provided for each of the blocks, and are simultaneously connected in parallel. Even when writing a signal, only the DA converter 205 needs the same number as the number of blocks, and can be configured with a much smaller circuit than the conventional example.

FIG. 3 is a block diagram showing a detailed embodiment of the write timing circuit 3 of FIG.

The phase comparator 101, the VCO 102, and the frequency divider 103 constitute a PLL circuit.
The oscillation frequency of the VCO 102 is controlled such that the output of the output 3 and the HD 511 have the same frequency and phase. VCO102
Is input to the frame memory 1 as a write clock 521 and is also connected to the horizontal counter 104. The output of the frequency dividing circuit 103 is connected to a horizontal counter 104 and a vertical counter 105. The outputs of these counters are connected to a write enable circuit 106, and output a write enable signal 522 that gives the frame memory 1 permission to write a video signal. The output of the vertical counter 105 is also connected to the frame memory 1 as a write reset signal 523. The write clock 521 is also connected to the frequency divider 9 in FIG. Note that the write clock 521, the write enable signal 522, and the write reset signal 523 correspond to the write timing signal 52 in FIG.
Further, the I / O 107 is connected to the I / O bus 54, and the CPU 5 can set the frequency division ratio of the frequency dividing circuit 103 and the count values of the horizontal counter 104 and the vertical counter 105, respectively.

FIG. 4 shows a detailed embodiment of the read timing circuit 4 of FIG.

The phase comparator 111, the VCO 112, and the frequency divider 113 constitute a PLL circuit.
21 is switched to the a side, the output of the frequency divider circuit 113 and the VC 511 are set so that the HD 511 has the same frequency and phase.
The oscillation frequency of O112 is controlled. When the switching circuit 121 is switched to the b side, the reference voltage 120 becomes VC
Since it is connected to O112, it does not operate as a PLL circuit, and the output of VCO 112 is, for example, about 56.7 MHz.
The oscillation frequency is fixed at z (= 33.75 kHz * 1680).

The output of VCO 112 is read clock 5
31 is input to the frame memory 1 and is also connected to the horizontal counter 114. The output of the frequency dividing circuit 113 and the frequency dividing circuit 123 is also switched by the switching circuit 122 and connected to the horizontal counter 114 and the vertical counter 115. The frequency dividing ratio of the frequency dividing circuit 123 is always fixed to a constant value, for example, 1680. The outputs of these counters are connected to a read enable circuit 116, and output a read enable signal 532 that gives the frame memory 1 permission to read a video signal. The output of the vertical counter 115 is the read reset signal 533.
As well as being connected to the frame memory 1 as well.
The output of the horizontal counter 114 is connected to a double speed conversion circuit 203 as a read horizontal reset signal (hereinafter, HR) 124. Note that the read clock 531, the read enable signal 532, and the read reset signal 533 are
Of the read timing signal 53. Further, although not shown, a read timing signal is also connected to the stage after the double speed conversion circuit 2. Also, I / O1
17 is connected to an I / O bus 54,
13, the horizontal counter 114 and the vertical counter 11
The CPU 5 can set the count value of 5 and the switching state of the switching circuits 121 and 122, respectively.

FIG. 2 is a block diagram showing a detailed embodiment of the frame memory 1 of FIG.

Field memory (1) 130, field memory (2) 131, line memory 132, coefficient unit 1
33, 134, adders 135, 136, motion detection circuit 1
37, switches 138, 139, 140, 141, 1 /
It comprises two coefficient units 142 and 143. The write clock 521, write enable signal 522, write reset signal 523 of FIG. 3, the read clock 531, read enable signal 532, and read reset signal 533 of FIG.
Although not shown, the above-mentioned field memory (1) 13
0, field memory (2) 131, line memory 13
2 are connected. The output of the operation setting circuit 8 of FIG. 1 performs an operation of switching the switches 138, 139, 140, and 141. The field memory (1) 130 and the field memory (2) 131 operate in such a manner that input and output are completely asynchronous.

In FIG. 1, the I / O bus 54 of the CPU 5
Is connected to the write timing circuit 3, the read timing circuit 4, the operation setting circuit 8, and the frequency dividing circuit 9 to perform the above-described settings and to store the set values in the data memory 6, Can be read from Further, the contents of the data memory 6 can be added or changed by the keyboard 10. With such a configuration, optimal adjustment according to the type of the input signal 200 can be performed, and a plurality of adjustment states can be stored in the data memory 6 and set as needed.

FIG. 5 shows a data memory 6 by the CPU 5 .
5 is a flowchart showing an example of reading a set value from the sub-system and setting data to each circuit. FIG. 6 is a flowchart showing an example in which the CPU 5 writes data to the data memory 6 in order to save the setting data.

Next, the number of pixels of the liquid crystal panel 206 is set to one horizontal.
The operation corresponding to each type of video signal shown in FIG. 14 will be described as 440 and vertical 1035.

Signal No. 1 is the case of a computer. First, the setting of the write frequency dividing circuit 103 is adjusted to 1400 of the horizontal cycle. In the case of a computer signal, since there is a large amount of character information, it is necessary to match the sampling timing to the dots constituting the character so as not to lose the information.
Should be adjusted to the number of dots in the horizontal cycle. By setting the setting value of the frequency dividing circuit 8 to 1, the clock of the AD converter 201 has the same frequency as the write clock 521. Signal No. 1, since both the horizontal cycle and the vertical cycle are smaller than the number of pixels of the liquid crystal panel, the writing horizontal counter 10
4. The write vertical counter 105 stops operating,
The write enable signal is set to be always active, and the frame memory 1 is continuously written without blanking. The switch 138 switches for each scanning line, and the switch 140 switches with a read clock.
The switch 139 is set to the c-side and the switch 141 is set to the h-side. Data for every other scanning line is written to the field memory (1) 130 and the field memory (2) 131, and multiplexed by the read clock to perform multiplexing. , A1, a2,..., A in FIG.
The display in the order of the scanning lines can be performed so that n is the first scanning line and b1, b2,..., bn are the next scanning lines. In the read timing circuit 3, the switching circuit 121 is set to the b side, and the VCO 112 is set to a fixed oscillation state. Also,
The switching circuit 122 is set on the d side, and the frequency dividing circuit 123 divides the frequency by 1680. The horizontal counter 114 and the vertical counter 115 make the number of dots in the horizontal cycle and the number of lines in the vertical cycle of the signal equal to each other, and during this period, the read enable circuit 116 reads the field memory (1) 130 and the field memory (2) 131. In this case, the reading is stopped during the period of the difference from the number of pixels of the liquid crystal panel.
By doing so, as shown in FIG.
In FIG. 6, a display in which the dots of the input video signal and the pixels of the liquid crystal panel coincide with each other can be performed in a window shape as indicated by oblique lines. The field memory (1) 1
Reading and writing of each of the field memory (30) and the field memory (2) 131 are completely asynchronous. However, in the case of a computer signal, since it can be regarded as a still image, no inconvenience occurs.

Signal No. 2 is the case of another computer. Signal No. Unlike 1, the horizontal cycle exceeds 1680, so that if data is written continuously and read by enabling the read frequency dividing circuit 123 by dividing by 1680 as described above, the data of one scanning line The read operation is not completed in the horizontal cycle of the read operation, and the data of the next scan line enters the head of the scan line. Therefore, the write horizontal counter 104 is set to an arbitrary value between 1400 and 1680, and the write enable circuit 106
Write to the frame memory 1 only during the operation of this counter,
What is necessary is just to set the read counter 114 to the same value and read. Other settings and operations are described in the above-mentioned signal No.
Same as 1

Signal No. The number of horizontal effective pixels and the number of vertical effective scanning lines are less than half of the number of horizontal pixels and the number of vertical pixels of the liquid crystal panel. When treated in the same way as 1, the display is 1 of the area of the liquid crystal panel.
Or less, and waste occurs. Therefore,
In the frame memory 1, the switch 138 is fixed to the a side and the switch 140 is fixed to the e side, and the field memory (1) 13
If only 0 is used and this output is input to the double speed conversion circuit 203, the signal of the same scanning line is output every two lines.
On a liquid crystal panel, it can be displayed in a size twice as large in the vertical direction. Although blanking is not applied to writing to the frame memory 1, if the write frequency dividing circuit 103 is set to twice the input signal, and the read frequency dividing circuit 113 and the read horizontal counter 114 are similarly set to double, Since one dot of the input signal can be sampled and handled as two dots, it can be displayed on the liquid crystal panel at twice the size in the horizontal direction. In this case, the frequency dividing ratio of the frequency dividing circuit 8 is set to 2, and one dot of the input signal is set to A.
If the D converter 201 performs sampling as one point and treats the subsequent processing as two dots, only the optimum point can be sampled and the output signal can be output with a width of two pixels even in the waveform of the rising or falling edge of the input signal. As shown at the lower end, it is possible to obtain image quality with a sharp outline despite being doubled, and there is an image quality improvement effect.

Signal No. 4 is an interlaced computer signal. When the switch 139 is set to the c side and the switch 141 is set to the h side, and the switch 138 is switched for each field of the input signal, a signal for each field is written to the field memory (1) 130 and the field memory (2) 131. When the switch 140 is switched by the read clock 531, the double-speed conversion circuit 2
The output of 03 means that the scanning lines of both fields are output one by one, and a sequentially scanned signal is obtained. For other operations, the signal No. The same as in the case of 1.

Signal No. Reference numeral 5 denotes a so-called IDTV signal obtained by double-converting an NTSC signal externally. in this case,
Signal No. Although it can be treated and displayed in the same way as 3,
Unlike computer signals, video is mainly used. If reading / writing of the frame memory 1 is completely asynchronous, the field memory (1) 130 and the field memory (2) 13
In 1, in some cases, one of the write and read addresses may overtake the other. At this time, signals of different frames are displayed before and after the overtaking point, and an unnatural discontinuous portion occurs in a moving image. Therefore, the switching circuit 121 of the read timing circuit 3 is set to the a side,
Is set to the d side, and the read timing circuit operates as a PLL. Here, assuming that the frequency dividing circuit 113 is set to 1800 and signals to the horizontal counter 114 and the vertical counter 115 are supplied from the frequency dividing circuit 123 by the switch 122, the frequency dividing ratio of the frequency dividing circuit 123 is 1680. Therefore, the dot clock is 1800 * 31.468.
kHz = 1680 * 33.716 kHz. Focusing on the right side, it is almost close to the horizontal frequency of HDTV,
112 need only slightly change the fixed oscillation frequency described above. Therefore, the operation timings of the blocks after the frame memory 1 hardly change, and the blocks can be operated under the optimum conditions. Further, the write timing circuit 2 and the read timing circuit 3
Therefore, if the reset is performed with the same VD 512, the writing and reading of the frame memory 1 coincide with each other in the HD cycle, and the discontinuous portion as described above does not occur.

Signal No. Reference numeral 6 denotes an HDTV signal. The frequency divider 103 of the write timing circuit 2 is set to 1680, and the read timing circuit 3 is set to the switching circuit 121 on the a side and the switching circuit 122 on the d side.
Are operated at the same timing. In the frame memory 1, the switch 138 is on the a side, the switch 139 is on the d side,
The switch 141 is set to the g side. The write timing setting circuit 2 and the read timing setting circuit 3 operate the field memory (1) as a 562-line delay line and the field memory (2) as a 563-line delay line. Therefore, the two inputs of the motion detection circuit 137 are 112
There is a difference of five lines, that is, one frame, and the motion can be detected by calculating the difference. According to this output, for example, as shown in FIG. 9, when the motion is large, the coefficient of the coefficient unit 134 is increased and the coefficient of the coefficient unit 133 is decreased, and when the motion is small, the coefficient is inverted to thereby reduce the 1/2 coefficient An interpolation signal corresponding to the motion is obtained from the output of the unit 143. The switch 140 is switched by a read clock. With such a configuration, a signal having a scanning line structure as shown in FIG. 10 is obtained at the output of the double speed conversion circuit 203. Numerals in the figure indicate scanning line numbers, and a part is a 1/2 coefficient multiplier 14 in FIG.
The output of No. 3 is input as an interpolation scanning line.
The average value of 4 and 565 is entered, and 2 is entered for a still image.
In addition, a mixture of the two is included according to the level of movement. As described above, in the case of the HDTV signal, it operates as a double-speed conversion device completely synchronized with the input signal.

The case where the liquid crystal panel 206 is one and is further divided into six has been described above. However, the case where a plurality of liquid crystal panels are used for colorization or the case where the number of divisions is increased or decreased according to the driver is also considered. Clearly, it can.

[0037]

As described above, according to the present invention,
Progressive scan signal, interlace signal, IDTV signal, H
Since a signal processing method suitable for each DTV signal can be set and a signal with a small number of dots can be enlarged and displayed, a device that displays most video signals used in various media can be configured.

Further, by providing the time axis extending means at the subsequent stage of the gamma correction means, the circuit scale can be reduced, and the first storage means is provided between the output of the AD converter and the double speed conversion circuit. The provision of the second storage means for storing the adjustment state makes it possible to switch the video signals of various scanning frequencies and display them on the liquid crystal panel.

From the above, it is possible to provide the same function as a so-called multi-scan monitor or projector using a CRT despite the use of a liquid crystal panel.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a frame memory of the present invention.

FIG. 3 is a block diagram showing details of a write timing circuit of the present invention.

FIG. 4 is a block diagram showing details of a read timing circuit of the present invention.

FIG. 5 is a flowchart illustrating data setting for each circuit according to the present invention.

FIG. 6 is a flowchart illustrating writing of a set value of each circuit to a data memory according to the present invention.

FIG. 7 is a diagram showing a display example on the liquid crystal panel of the present invention.

FIG. 8 is a diagram illustrating a relationship between a frequency division ratio and an output according to the present invention.

FIG. 9 is a diagram illustrating an example of a relationship between an output of the motion detection circuit of the present invention and a coefficient of a coefficient unit.

FIG. 10 is a diagram showing a scanning line structure for double speed conversion according to the present invention.

FIG. 11 is a block diagram illustrating a conventional example.

FIG. 12 is a block diagram illustrating an operation of a conventional example and a time axis expansion circuit of the present invention.

FIG. 13 is a timing chart illustrating the operation of the conventional example and the double-speed conversion circuit of the present invention.

FIG. 14 is a diagram showing a setting state by various signals according to the present invention.

[Explanation of symbols]

1 frame memory Double speed conversion circuit 3 Write timing circuit 4 Read timing circuit 5 CPU 6 Data memory 7 Sync separation circuit 8 Operation setting circuit 9 divider circuit 10 Keyboard 51 Sync signal 52 Write Timing Circuit 53 Read timing circuit 54 I / O bus 101 Phase comparison circuit 102 VCO 103 divider circuit 104 horizontal counter 105 vertical counter 106 Write enable circuit 107 I / O circuit 111 phase comparison circuit 112 VCO 113 divider circuit 114 horizontal counter 115 vertical counter 116 Read enable circuit 117 I / O circuit 120 Reference voltage 121 Switching circuit 122 Switching circuit 123 divider circuit 130 Field memory (1) 131 Field memory (2) 132 line memory 133 Coefficient unit 134 coefficient unit 135 adder 136 adder 137 Motion detection circuit 138 switch 139 switch 140 switch 141 switch 142 1/2 coefficient unit 143 1/2 coefficient unit 511 horizontal synchronization signal 512 Vertical sync signal 521 Write clock 522 Write enable signal 523 Write reset signal 531 Read clock 532 Read enable signal 533 read reset signal

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N ^7/ 00-7/088

Claims (8)

(57) [Claims] 1. An image signal processing circuit for displaying an image signal, comprising: an AD converter for AD-converting an input image signal; a first field memory for storing an output of the AD converter; Field memory,
Means for converting the outputs of the first and second field memories at double speed; means for locking the write clocks of the first and second field memories to a synchronization signal of the input video signal; Setting means for setting the write enable timing of the second field memory and the read enable timing of the first and second field memories, and using the output of the AD converter as an input of the second field memory. A video signal processing circuit comprising: a setting unit configured to set switching between the case where the output of the first field memory is used and the type of the input video signal . 2. The apparatus according to claim 1, further comprising means for synchronizing read timings of said first and second field memories and timing of said conversion means with a synchronization signal of said input video signal. Video signal processing circuit. And means for setting the frequency of the write clock, the frequency of the read clock of the first and second field memories, and the frequency of the clock of the conversion means in an integer ratio relationship. 3. The video signal processing circuit according to claim 1, wherein: 4. The apparatus according to claim 1, further comprising conversion means for converting output data of said first field memory into two scanning lines having data equal to said data at double speed.
The video signal processing circuit as described in the above. 5. The apparatus according to claim 1, further comprising means for setting a clock of the AD converter to an integer fraction of a write clock of the first and second field memories. Video signal processing circuit. 6. An AD converter for AD-converting an input video signal, a first field memory and a second field memory for asynchronously inputting and outputting an output of the AD converter,
Converting means for converting the outputs of the first and second field memories at double speed, gamma correcting means receiving the output of the converting means as input, time axis extending means receiving the output of the correcting means as input, Means for locking the write clock of the first and second field memories to the synchronization signal of the input video signal; write enable timing setting means for setting the write enable timing of the first and second field memories; And write enable timing setting means for setting a read enable timing of the second field memory, and using the output of the AD converter as the input of the second field memory and using the output of the first field memory. and switching setting means for switching between the case in accordance with the type of the input video signal, the document A liquid crystal panel having a setting storage means for storing a setting state of the read enable timing setting means, a setting state of the read enable timing setting means, and a setting state of the switching setting means for each input video signal. The video display device used. 7. A line memory to which an output of the first field memory is input when an output of the first field memory is used as an input of the second field memory; Motion detection means for comparing the input of the second field memory with the output of the second field memory, and addition means for adding the output of the second field memory and the output of the line memory according to the output of the motion detection means, 6. The video signal processing circuit according to claim 1, further comprising output switching means for switching between the output of said adding means and the output of said first field memory. 8. A line memory to which an output of the first field memory is input when an output of the first field memory is used as an input of the second field memory; Motion detection means for comparing the input of the second field memory with the output of the second field memory, and addition means for adding the output of the second field memory and the output of the line memory according to the output of the motion detection means, 7. An image display apparatus using a liquid crystal panel according to claim 6, further comprising output switching means for switching between the output of said adding means and the output of said first field memory.