JPH06292147A - Video signal processing circuit - Google Patents

Abstract

PURPOSE:To attain setting of the signal processing method suitable for each signal and magnification display of a signal with the less number of dots by providing a means locking a write timing of a 1st storage means to an input video signal and a means setting a read timing in the processing circuit. CONSTITUTION:A write timing signal 52 used to write an output of an A/D converter 201 is inputted from a write timing circuit 3 to a frame memory 1. Moreover, a read timing signal 53 for reading the frame memory 1 is inputted from a read timing circuit 4 to the frame memory 1. Moreover, an operation setting circuit 8 sets the operation of the frame memory 1. Then an I/O bus 54 of a CPU 5 is connected to the write timing circuit 3, the read timing circuit 4, an operation setting circuit 8 and a frequency division circuit 9 and each setting is executed and the set value is stored in a data memory 6 and read from the data memory 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing circuit having a double speed conversion circuit.

[0002]

2. Description of the Related Art In a video display device using a liquid crystal panel,
In order to display high resolution signals such as HDTV, JA
PAN DISPLAY '89 Proceedings p256-25
9 "High Definition Liquid
As described in "Crystal Projection TV", a digital signal processing circuit is used.

FIG. 11 shows an example of a conventional signal processing circuit.
The input signal 200 is converted into a digital signal by the AD converter 201, and after being expanded by, for example, 6 times by the time axis expansion circuit 202, the double speed conversion circuit 203 converts interlace into progressive scanning, and the gamma correction circuit 204 converts the interlace into a liquid crystal panel. After the gamma is corrected according to the characteristics, the DA converter 205 restores the analog signal, and the liquid crystal panel 206
It is transmitted to and displayed.

Assuming that a high-definition signal such as an HDTV signal is displayed on a liquid crystal panel of 1440 pixels in the horizontal direction, the clock of the video signal is 50 MH.
Since the frequency becomes extremely high at z or more, the drive circuit (not shown) of the liquid crystal panel cannot be operated,
The video signal cannot be displayed. Therefore, the liquid crystal panel is divided into, for example, six blocks in the horizontal direction, independent drive circuits are provided in each block, and signals are simultaneously written in parallel to lower the frequency of each block to operate the drive circuits. Signals are displayed on the panel.

Referring to FIG. 11, the video signal is separated into 6 blocks by the time axis expansion circuit 202. The timing is shown in FIG. The input signal 210 is digitized by the AD converter 201, and here shows the effective scanning period of one scanning line. The time axis expansion circuit 202 divides the input signal 210 into 6 blocks, expands the input signal 6 times to the input, and corresponds to each of the divided blocks of the liquid crystal panel 206 as indicated by a to f of the output signal 211. Output as a signal.

An HDTV having 1035 effective scanning lines
When a signal is displayed on a liquid crystal panel having 1035 pixels in the vertical direction, one scanning line can correspond to one pixel in the vertical direction, but only half the number of scanning lines is sent in one field time. Since it doesn't exist, it takes 2 fields, or 1 frame, to display the whole screen.
Flicker occurs due to the charge retention characteristics of the liquid crystal panel. Therefore, the double speed conversion circuit 203 doubles the scanning speed to generate a signal corresponding to two fields in one field time by interpolation, so that the entire screen can be written in one field time.
FIG. 13 is a timing chart showing the operation of the double speed conversion circuit 203, in which a1, b1, a2, b2, a3, b3 ,.
..., if signals are input in the order of an, bn, then a1, a
2, a3, ..., an, b1, b2, b3, ..., bn
The data is output after being rearranged in this order, and the output signal of the double speed conversion can be obtained by multiplexing and inputting the data of the two scanning lines. However, since the input signal is sent only one scanning line at a time, the other must provide an interpolation signal.

The simplest method is to convert the data of the same scanning line into two scanning lines having the same data, using the data as an interpolation signal. As another method, JP-A-4-1578
As described in Publication No. 86, there is inter-line interpolation that uses the average value of the previous scan line and the current scan line and inter-field interpolation that uses the scan line of one field before. As a line, the former requires a line memory and the latter requires a field memory. In addition, motion adaptive interpolation may be used, in which the motion of each part of the screen is detected, inter-field interpolation with high vertical resolution is used for the still part, and inter-line interpolation is switched to prevent double images in the motion part. is there. Note that all of these operations are performed in synchronization with the input video signal.

[0008]

Due to the above configuration, although omitted in FIG. 11, the double speed conversion circuit 203, the gamma correction circuit 204, and the DA converter 205 are as many as the number of blocks, that is, the above. In the description, there is a drawback that 6 circuits are required and the scale becomes large.

Further, since all the parts are configured to operate in synchronization with the timing of the input video signal, if an HDTV is designed to be displayed on a liquid crystal panel, other signals having different scanning frequencies will be displayed. There was a problem that it could not be done. For the purpose of displaying on a CRT, Nikkei Electronics '92 .8.3.
(No. 560) p154-156 "Multifunctional scan converter" is described, but when it is used for display of a liquid crystal panel, the coincidence between output signal and panel pixel is not taken into consideration. There is a problem that the display quality is poor.

Therefore, the present invention solves such a problem, and an object of the present invention is to provide a video display device using a liquid crystal panel, which is small in scale and can display signals of various scanning frequencies without deterioration. It is to realize a video signal processing circuit.

[0011]

A video signal processing circuit according to the present invention comprises means for locking the write timing of the first storage means to the input video signal and means for setting the read timing. .

Further, there is provided means for matching the write and read timings of the first storage means at the time of inputting the HDTV signal, and further for locking to the input video signal, and the first storage means operates as a double speed conversion means. It is characterized by being used as a detection frame memory and a field memory for inter-field interpolation.

Further, when an externally double-speed converted NTSC signal is input, the write timing of the first storage means is locked by the input signal, and the read timing clock of the first storage means is set to the write timing. By setting the relationship between the clock and the integer ratio, it is possible to prevent a discontinuous portion that occurs on the screen during a moving image due to the difference in the writing and reading timings of the first storage means.

Further, when the number of vertical or horizontal dots of the input video signal is 1/2 or less of the number of pixels in the vertical or horizontal direction of the display device, it is possible to enlarge the display. Characterize. Further, in order to reduce the circuit scale, a time axis expansion means is provided after the gamma correction means, and between the output of the AD converter and the double speed conversion means so as to be compatible with video signals of various scanning frequencies. The present invention is characterized in that it is provided with one storage means, and further provided with a second storage means for storing the adjustment state for each of various input video signals.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment according to the present invention. In this figure, the same symbols as those in FIG. 11 have the same functions. The input signal 200 is converted into a digital signal by the AD converter 201, and is input to the frame memory 1 which is the first storage means and whose input / output is asynchronous. In addition, the input signal 200
Is also input to the sync separation circuit 7 and is a sync signal 5 consisting of a horizontal sync signal (hereinafter HD) and a vertical sync signal (hereinafter VD).
1 is separated. Although not shown, depending on the type of the video signal, the video signal and the HD and VD may be separately transmitted in advance. In that case, the HD signal is not directly passed through the sync separation circuit 7, It is clear that the connection should be made as VD. HD and VD are input to the write timing circuit 3 and the read timing circuit 4. A write timing signal 52 for writing the output of the AD converter 201 into the frame memory 1 is input from the write timing circuit 3. Further, through the frequency dividing circuit 9,
It is also connected to the D converter 201. In addition, a read timing signal 53 for reading the frame memory 1 is output from the read timing circuit 4.
Has been entered in. Although not shown, the stages after the frame memory 1 are also connected so that the read timing circuit 53 operates. The operation setting circuit 8 sets the operation of the frame memory 1. Further, the write timing circuit 3, the read timing circuit 4, the operation setting circuit 8, and the frequency dividing circuit 9 are connected to the I / O bus 54 of the CPU 5. A data memory 6, which is a second storage unit, is connected to the CPU 4.

The double speed conversion circuit 2 operates in the same manner as the double speed conversion circuit 203 described in the prior art.

The output of the frame memory 1 is converted into a scanning line by the double speed conversion circuit 2 and gamma is corrected by the gamma correction circuit 204 according to the characteristics of the liquid crystal panel, and then expanded by, for example, 6 times by the time axis expansion circuit 202. After that, the DA converter 205 restores the analog signal and transmits it to the liquid crystal panel 206 for display. Although the DA converter 205 requires six circuits, it is omitted in the figure and only one circuit is shown.

Since the time-axis expansion circuit 202 is positioned after the gamma correction circuit 204 in this way, the liquid crystal panel is horizontally divided into, for example, six blocks, and independent drive circuits are provided for each of them, and they are simultaneously arranged in parallel. Even when writing a signal, it is only the DA converter 205 that needs the same number as the number of blocks, and can be configured by a much smaller circuit than the conventional example.

FIG. 3 is a block diagram showing a detailed embodiment of the write timing circuit 3 of FIG.

The phase comparison circuit 101, the VCO 102, and the frequency dividing circuit 103 constitute a PLL circuit, and the frequency dividing circuit 10
The oscillation frequency of the VCO 102 is controlled so that the output of No. 3 and the HD 511 have the same frequency and phase. VCO102
The output of is input to the frame memory 1 as the write clock 521 and is also connected to the horizontal counter 104. The output of the frequency dividing circuit 103 is connected to the horizontal counter 104 and the vertical counter 105. The outputs of these counters are connected to the write enable circuit 106 and output a write enable signal 522 that gives the frame memory 1 permission to write a video signal. The output of the vertical counter 105 is also connected to the frame memory 1 as a write reset signal 523. The write clock 521 is also connected to the frequency dividing circuit 9 in FIG. The write clock 521, the write enable signal 522, and the write reset signal 523 correspond to the write timing signal 52 of FIG.
Further, the I / O bus 54 is connected to the I / O 107, and the frequency division ratio of the frequency dividing circuit 103 and the count values of the horizontal counter 104 and the vertical counter 105 can be set by the CPU 4, respectively.

FIG. 4 shows a detailed embodiment of the read timing circuit 4 of FIG.

The phase comparison circuit 111, the VCO 112, and the frequency dividing circuit 113 constitute a PLL circuit, and the switching circuit 1
When 21 is switched to the side a, VC is adjusted so that the output of the frequency dividing circuit 113 and the HD 511 have the same frequency and phase.
The oscillation frequency of O112 is controlled. Further, when the switching circuit 121 is switched to the b side, the reference voltage 120 becomes VC
Since it is connected to O112, it does not operate as a PLL circuit, and the output of VCO 112 is, for example, about 56.7 MH.
It is fixed to the oscillation frequency of z (= 33.75 kHz * 1680).

The output of the VCO 112 is the read clock 5
It is input to the frame memory 1 as 31, and is also connected to the horizontal counter 114. Further, it is also connected to the frequency dividing circuit 123, and the outputs of the frequency dividing circuit 113 and the frequency dividing circuit 123 are switched by the switching circuit 122 and connected to the horizontal counter 114 and the vertical counter 115. The frequency dividing circuit 123 has a frequency dividing ratio that is always fixed to a constant value, for example, 1680. The outputs of these counters are connected to the read enable circuit 116, and output a read enable signal 532 which gives the frame memory 1 permission to read the video signal. The output of the vertical counter 115 is the read reset signal 533.
Is also connected to the frame memory 1 as
The output of the horizontal counter 114 is connected to the double speed conversion circuit 203 as a read horizontal reset signal (hereinafter, HR) 124. The read clock 531, the read enable signal 532, and the read reset signal 533 are as shown in FIG.
Of the read timing signal 53. Further, although not shown, the read timing signal is also connected to the stages after the double speed conversion circuit 2. Also, I / O1
An I / O bus 54 is connected to 17 and the frequency divider circuit 1
Dividing ratio of 13, horizontal counter 114 and vertical counter 11
The count value of 5 and the switching states of the switching circuits 121 and 122 can be set by the CPU 4, respectively.

FIG. 2 is a block diagram showing a detailed embodiment of the frame memory 1 of FIG.

Field memory (1) 130, field memory (2) 131, line memory 132, coefficient unit 1
33, 134, adders 135, 136, motion detection circuit 1
37, switches 138, 139, 140, 141, 1 /
It is composed of two coefficient units 142 and 143. The write clock 521, the write enable signal 522, the write reset signal 523 in FIG. 3, the read clock 531, the read enable signal 532, and the read reset signal 533 in FIG.
Is not shown, but the above field memory (1) 13
0, field memory (2) 131, line memory 13
Connected to 2. The output of the operation setting circuit 7 of FIG. 1 serves to switch the above switches 138, 139, 140 and 141. The field memory (1) 130 and the field memory (2) 131 operate so that input and output are completely asynchronous.

In FIG. 1, the I / O bus 54 of the CPU 5
Is connected to the write timing circuit 3, the read timing circuit 4, the operation setting circuit 8, and the frequency dividing circuit 9, and performs the above-mentioned settings and stores the set value in the data memory 6 and the data memory 6 Can be read from. Further, the contents of the data memory 6 can be added or changed by the keyboard 10. With such a configuration, optimum adjustment can be performed according to the type of the input signal 200, and a plurality of adjustment states can be stored in the data memory 6 and set as necessary.

FIG. 5 shows the data memory 5 by the CPU 4.
3 is a flow chart showing an example of reading a set value from and setting data to each circuit. FIG. 6 is a flow chart showing an example of writing to the data memory 5 by the CPU 4 in order to save the setting data.

Next, the number of pixels of the liquid crystal panel 206 is set to 1 horizontal.
An operation corresponding to each type of video signal shown in FIG. 14 will be described with reference to 440 and vertical 1035.

Signal No. 1 is the case of a computer. First, the setting of the write frequency dividing circuit 103 is adjusted to the horizontal cycle of 1400. In the case of a computer signal, since there is a lot of character information, it is necessary to match the sampling timing with the dots forming the character so as not to lose the information, but as described above, the write frequency dividing circuit 103.
Should be adjusted to the number of dots in the horizontal cycle. By setting the setting value of the frequency dividing circuit 8 to 1, the clock of the AD converter 201 has the same frequency as the write clock 521. Signal No. In the case of 1, the horizontal period and the vertical period are smaller than the number of pixels of the liquid crystal panel.
4. The write vertical counter 105 stops its operation,
The write enable signal is set to be always active, and the frame memory 1 is continuously written without blanking. The switch 138 is switched for each scanning line, and the switch 140 is switched by a read clock.
The switch 139 is set to the c side, and the switch 141 is set to the h side. Data for every other scanning line is written in the field memory (1) 130 and the field memory (2) 131, and multiplexed by the read clock to perform the double speed conversion circuit 2. , A1, a2, ..., A in FIG.
It is possible to display the scanning lines in order such that n is the first scanning line and b1, b2, ..., Bn are the next scanning lines. Further, in the read timing circuit 3, the switching circuit 121 is set to the b side to bring the VCO 112 into a fixed oscillation state. Also,
The switching circuit 122 is set to the d side, and the frequency dividing circuit 123 divides the frequency by 1680. The horizontal counter 114 and the vertical counter 115 are made equal to the number of dots in the horizontal cycle and the number of lines in the vertical cycle of the signal, respectively, and only during this time, the read enable circuit 116 reads the field memory (1) 130 and the field memory (2) 131. The reading is stopped during the period of the difference from the number of pixels of the liquid crystal panel.
By doing so, as shown in FIG.
In 6, a display can be performed in which the dots of the input video signal and the pixels of the liquid crystal panel coincide with each other in a window shape as shown by the diagonal lines. The field memory (1) 1
Reading and writing of data from 30 and the field memory (2) 131 are completely asynchronous, but in the case of a computer signal, since it can be regarded as a still image, no inconvenience occurs.

Signal No. 2 is for another computer. Signal No. Unlike 1, the horizontal period exceeds 1680. Therefore, when data is written continuously, and data is read from one scanning line by enabling it by the 1680 frequency division of the frequency division circuit 123 for reading as described above. The data cannot be displayed normally because the data of the next scanning line has entered the beginning of the data of the next scanning line without completing the reading in the horizontal cycle of reading. Therefore, the horizontal counter 104 for writing is set to an arbitrary value between 1400 and 1680, and the write enable circuit 106
Write to frame memory 1 only while this counter is operating,
The read counter 114 may be set to the same value and read. For other settings and operations, refer to the signal No. described above.
It is the same as the case of 1.

Signal No. Also in the case of a computer, the number of horizontal effective pixels and vertical effective scanning lines is less than half of the number of horizontal pixels and vertical pixels of the liquid crystal panel. When handled in the same way as 1, the display is 1
Only less than / 4 and waste occurs. Therefore,
In the frame memory 1, the switch 138 is fixed to the a side and the switch 140 is fixed to the e side, and the field memory (1) 13 is fixed.
If only 0 is used and this output is input to the double speed conversion circuit 203, the signal of the same scanning line is output every two lines.
On the liquid crystal panel, the display can be doubled in the vertical direction. Although blanking is not applied to the writing in the frame memory 1, if the write frequency dividing circuit 103 is set to double the input signal and the read frequency dividing circuit 113 and the read horizontal counter 114 are also set to double the same. Since one dot of the input signal can be sampled and handled as two dots, it can be displayed on the liquid crystal panel in double size in the horizontal direction. In this case, the frequency division ratio of the frequency divider circuit 8 is further set to 2, and 1 dot of the input signal is set to A
If the D converter 201 samples at 1 point by using 1 dot and treats the subsequent processing as 2 dots, only the optimum point can be sampled and output with a 2 pixel width even if the waveform of the rising and falling edges of the input signal is sampled. As shown in the lower end of the figure, the image quality with a sharp contour can be obtained even though the image quality is doubled, and there is an image quality improving effect.

Signal No. 4 is an interlaced computer signal. When the switch 139 is set to the c side and the switch 141 is set to the h side, and the switch 138 is switched for each field of the input signal, the signal for each field is written in the field memory (1) 130 and the field memory (2) 131. If the switch 140 is switched by the read clock 531, the double speed conversion circuit 2
The output of 03 means that the scanning lines of both fields are output one by one, and the signals sequentially scanned are obtained. For other operations, the signal No. It is similar to the case of 1.

Signal No. Reference numeral 5 is a so-called IDTV signal obtained by externally converting the NTSC signal at a double speed. in this case,
Signal No. Although it can be handled and displayed in the same way as in item 3,
Unlike computer signals, movies are the main type. If the reading and writing of the frame memory 1 is completely asynchronous, the field memory (1) 130 and the field memory (2) 13
In No. 1, one of the write and read addresses may overtake the other, and at this time, different frame signals are displayed before and after the overtaking point, resulting in an unnatural discontinuous portion in the moving image. Therefore, the switching circuit 121 of the read timing circuit 3 is set to the a side, and the switching circuit 122.
Is set to the d side to operate the read timing circuit as a PLL. Here, assuming that the frequency dividing circuit 113 is set to 1800 and the signals to the horizontal counter 114 and the vertical counter 115 are supplied from the frequency dividing circuit 123 by the switch 122, the frequency dividing ratio of the frequency dividing circuit 123 is 1680. Therefore, the dot clock is 1800 * 31.468
kHz = 1680 * 33.716 kHz. Focusing on the right side, it is close to the horizontal frequency of HDTV,
112 need only slightly change the above-mentioned fixed oscillation frequency. Therefore, the blocks subsequent to the frame memory 1 can be operated under optimum conditions with almost no change in operation timing. The write timing circuit 2 and the read timing circuit 3 are the same HD 51.
Since it is locked by 1, if the same VD 512 is reset, the writing and reading of the frame memory 1 coincide with each other in the HD cycle, and the above discontinuity does not occur.

Signal No. Reference numeral 6 is an HDTV signal. The frequency divider 103 of the write timing circuit 2 is set to 1680, and the read timing circuit 3 is set to the switching circuit 121 on the a side and the switching circuit 122 on the d side, and both PLLs are set.
Operate at the same timing. In the frame memory 1, the switch 138 is on the a side, the switch 139 is on the d side,
The switch 141 is set to the g side. The write timing setting circuit 2 and the read timing setting circuit 3 cause the field memory (1) to operate as a 562 line delay line and the field memory (2) to operate as a 563 line delay line. Therefore, the two inputs of the motion detection circuit 137 are 112
The difference is 5 lines, that is, 1 frame, and the motion can be detected by obtaining the difference. With this output, as shown in FIG. 9, for example, when the motion is large, the coefficient of the coefficient unit 134 is increased and the coefficient of the coefficient unit 133 is decreased. At the output of the device 143, an interpolation signal corresponding to the motion is obtained. Further, the switch 140 is switched by the read clock. With such a configuration, a signal having a scanning line structure as shown in FIG. 10 is obtained at the output of the double speed conversion circuit 203. The numbers in the figure indicate the scanning line numbers, and the ½ coefficient unit 14 of FIG.
The output of 3 enters as an interpolation scanning line, but in the case of a moving image, it is 56
The average value of 4 and 565 is entered, and 2 is entered for a still image.
Also, depending on the level of movement, a mixture of both will be included. As described above, in the case of the HDTV signal, it operates as a double speed conversion device which is completely synchronized with the input signal.

The case where the liquid crystal panel 206 is one and is further divided into six has been described above. However, even when a plurality of liquid crystal panels are used for colorization or when the number of divisions is increased or decreased according to the driver. It is clear that we can handle this.

[0037]

As described above, according to the present invention,
Progressive scan signal, interlace signal, IDTV signal, H
Since a signal processing method suitable for each DTV signal can be set and a signal with a small number of dots can be enlarged and displayed, an apparatus for displaying most video signals used in various media can be configured.

Further, the circuit scale can be reduced by providing the time axis expansion means at the subsequent stage of the gamma correction means, and the first storage means is provided between the output of the AD converter and the double speed conversion circuit. By providing the second storage means for storing the adjustment state, it becomes possible to switch the video signals of various scanning frequencies and display them on the liquid crystal panel.

For these reasons, it is possible to provide the same function as that of a so-called multi-scan type monitor or projector using a CRT, even though a liquid crystal panel is used.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a frame memory of the present invention.

FIG. 3 is a block diagram showing details of a write timing circuit of the present invention.

FIG. 4 is a block diagram showing details of a read timing circuit of the present invention.

FIG. 5 is a flowchart illustrating data setting in each circuit according to the present invention.

FIG. 6 is a flowchart illustrating writing of set values for each circuit to a data memory according to the present invention.

FIG. 7 is a diagram showing a display example on a liquid crystal panel of the present invention.

FIG. 8 is a diagram illustrating a relationship between a frequency division ratio and an output according to the present invention.

FIG. 9 is a diagram showing an example of the relationship between the output of the motion detection circuit of the present invention and the coefficient of the coefficient unit.

FIG. 10 is a diagram showing a scanning line structure for double speed conversion according to the present invention.

FIG. 11 is a block diagram illustrating a conventional example.

FIG. 12 is a block diagram illustrating an operation of a conventional example and a time axis expansion circuit of the present invention.

FIG. 13 is a timing chart for explaining the operation of the conventional example and the double speed conversion circuit of the present invention.

FIG. 14 is a diagram showing a setting state by various signals according to the present invention.

[Explanation of symbols]

 1 frame memory 2 double speed conversion circuit 3 write timing circuit 4 read timing circuit 5 CPU 6 data memory 7 sync separation circuit 8 operation setting circuit 9 frequency divider circuit 10 keyboard 51 sync signal 52 write timing circuit 53 read timing circuit 54 I / O bus 101 phase comparator circuit 102 VCO 103 frequency divider circuit 104 horizontal counter 105 vertical counter 106 write enable circuit 107 I / O circuit 111 phase comparator circuit 112 VCO 113 frequency divider circuit 114 horizontal counter 115 vertical counter 116 read enable circuit 117 I / O circuit 120 Reference Voltage 121 Switching Circuit 122 Switching Circuit 123 Frequency Division Circuit 130 Field Memory (1) 131 Field Memory (2) 132 Line Memory 133 Coefficient Unit 134 Coefficient unit 135 Adder 136 Adder 137 Motion detection circuit 138 Switch 139 Switch 140 switch 141 switch 142 1/2 Coefficient unit 143 1/2 Coefficient unit 511 Horizontal sync signal 512 Vertical sync signal 521 Write clock 522 Write enable signal 523 Write reset Signal 531 Read clock 532 Read enable signal 533 Read reset signal

Claims (6)

[Claims] 1. A video signal processing circuit for displaying a video signal, wherein an AD converter and a first storage means for storing an output of the AD converter and having asynchronous input and output and a double speed output of the storage means. Setting conversion means for converting, means for locking the write clock of the first storage means to the input video signal, write enable timing of the first storage means, and read enable timing of the first storage means And a setting means for setting switching of the memory forming the first storage means. 2. A video signal processing circuit for displaying a video signal, wherein an AD converter and a first storage means for storing an output of the AD converter and having asynchronous input and output and an output of the storage means are double speed. A video signal processing circuit comprising: a conversion means for converting, a means for locking a write timing and a read timing of the first storage means, and a timing of the conversion means to an input video signal. 3. A video signal processing circuit for displaying a video signal, wherein an AD converter and a first storage means for storing the output of the AD converter and having asynchronous input and output and an output of the storage means are double speed. Conversion means for converting, means for locking the write clock of the first storage means to the input video signal, the write clock, the read clock of the first storage means and the clock of the conversion means in integer ratio A video signal processing circuit comprising: means for setting a relationship. 4. A video signal processing circuit for displaying a video signal, comprising: an AD converter, a first storage means for storing an output of the AD converter and asynchronous input / output, and output data of the storage means. A video signal processing circuit, comprising: a conversion unit that performs double speed conversion into two scanning lines having the same data as the data. 5. A video signal processing circuit for displaying a video signal, wherein an AD converter and a first storage means for storing an output of the AD converter and having asynchronous input and output and an output of the storage means are double speed. A video signal processing circuit comprising: a conversion unit for converting and a unit for setting the clock of the AD converter to an integral fraction of the write clock of the first storage unit. 6. An image display device using a liquid crystal panel, an AD converter, a first storage means for storing an output of the AD converter and asynchronous input / output, and a conversion for double-speed conversion of the output of the storage means. Means, gamma correction means having the output of the converting means as an input, time axis expansion means having the output of the correcting means as an input, setting means for setting the write enable timing of the first storage means, and Setting means for setting the read enable timing of the first storage means, setting means for setting switching of the memory forming the first storage means, parameters of the write enable timing setting means, and the read enable timing setting A video signal, characterized in that it comprises a second storage means for storing the parameter of the means and the setting state of the switching setting means. Processing circuit.