JPH07255026A - Television signal display device - Google Patents

Abstract

PURPOSE:To freely adjust an image display position on a liquid crystal display part by an inexpensive means. CONSTITUTION:Liquid crystal cells 111-113 are driven by X drivers 105-107 and Y drivers 108-110 and a video signal is supplied to the X drivers 105-107, line by line. A clock for each driver is generated by a synchronous control circuit 101. The clock is switched in frequency in respective periods so as to set a display period (area) and a nondisplay period (area), the switching timing can optionally be set, and an image display area on the display can easily be changed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION This invention is based on the existing method (for example, N
The present invention relates to a television signal processing device for processing a high definition television signal compatible with the TSC system), and particularly to a display device thereof.

[0002]

2. Description of the Related Art Systems have been developed for transmitting and receiving high definition television signals that are compatible with current systems.
Signals handled by this transmission / reception system include a side panel system and a lator box system.

The side panel system has an aspect ratio of 16:
High-definition television signal of 9: 4: 3 only in the center part
It is cut at the aspect ratio and is used as the main signal according to the standard of the current system signal, and the signals of the left and right side parts are transmitted by being multiplexed with the main signal. Therefore, when it is received by the television receiver of the current system, the main signal of 4: 3 is displayed on the full screen. When received by a receiver with a high definition television signal decoder,
The signal in the side portion is demodulated and connected to the left and right of the main signal to reproduce an image signal with a wide aspect ratio of 16: 9.

On the other hand, in the letterbox system, a television signal having an aspect ratio of 16: 9 is vertically compressed,
It is processed so as to fit on a screen with an aspect ratio of 4: 3 and transmitted as a main signal. In addition, an extra high resolution signal generated due to compression is multiplexed and transmitted to upper and lower mask portions generated above and below the main signal, for example. Therefore, when a television signal of this system is received and reproduced by a receiver of the current system, a mask (black) part (non-image part) is generated above and below the screen, and the screen becomes a horizontally long video screen. When the signal is received by a receiver with a high-definition television signal decoder, the high-resolution signals of the upper and lower mask parts are reproduced, and the main signal is vertically expanded, and the reproduced high-resolution signals are reproduced. Are added, and an image signal with a wide aspect ratio of 16: 9 is obtained.

[0005]

As a receiver for receiving the letterbox type or side panel type video signal as described above, it is desired that the current NTSC type video signal can be received and displayed. It is also desired that various types of video signals from devices such as VTRs can be processed and displayed. In such a system, the screen of the display device is, of course, produced as a wide screen, but when the image of the video signal sent by the current method is displayed as it is or when it is enlarged, it is displayed on the wide screen. Has a margin or no display. In such a case, there is a demand to effectively utilize the screen, and a system capable of freely changing the image display position is desired. In particular, in the case of a liquid crystal display, conventionally, the image display position is adjusted by adjusting the mechanical means of the optical system.
Such means are extremely expensive and complicated to adjust.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a television signal display device in which an image display position can be freely adjusted with respect to a liquid crystal display portion by an inexpensive means. Still another object of the present invention is to provide a television signal display device in which the response speed of the liquid crystal display section is improved by a simple means.

[0007]

According to the present invention, when a video signal is displayed on a liquid crystal display, a clock controller is provided so that the image position can be adjusted with a simple structure. Further, according to the present invention, when a video signal is displayed on a liquid crystal display, the liquid crystal display is regarded as a frame memory, a calculation process of an input signal and an output of the display is performed, a new input signal is created, and a response speed is increased. It is a thing.

Specifically, a liquid crystal cell in which liquid crystal display elements are arranged in a matrix, a horizontal driver for driving the elements of the liquid crystal cell in a horizontal arrangement direction by sampling an input video signal in the horizontal direction, A vertical driver for driving the elements of the liquid crystal cell in the vertical direction by driving the elements of the liquid crystal cells so that the input video signal is sampled in horizontal lines, a horizontal drive start timing signal of the horizontal driver, and the sampling in element units. A horizontal drive clock for obtaining a speed, a means for obtaining a horizontal enable timing signal that determines a horizontal period for supplying a sampled signal to the element, a vertical drive start timing signal for the vertical driver, and a speed specified by the row unit. Specifies the vertical drive clock to obtain and the previous matrix unit A means for obtaining a vertical enable timing signal that defines a direct period and a horizontal enable timing signal that defines the horizontal period are high-speed clocks obtained by increasing the frequency of the horizontal drive clock when the period is other than the designated period, and indicate the designated period. Means for switching to a low-speed clock with a lower frequency, and a vertical enable timing signal that defines the vertical period is a high-speed clock with a higher frequency of the vertical drive clock when a period other than the designated period is indicated, indicating the designated period. In this case, there are provided means for switching to a low-speed clock having a lower frequency, and means for arbitrarily changing the designated period of the horizontal enable timing signal and the vertical enable timing signal.

The present invention further comprises a liquid crystal cell in which liquid crystal display elements are arranged in a matrix, a horizontal driver for driving the elements of the liquid crystal cell in the horizontal arrangement direction by sampling an input video signal in the horizontal direction, and A vertical driver that drives the elements of the liquid crystal cell in the vertical direction by designating the elements of the liquid crystal cell in the vertical direction so that the input video signal is sampled in the horizontal line unit, and a signal that is opposed to the horizontal driver and is output from the liquid crystal cell. A horizontal receiver for latching, a horizontal drive start timing signal for the horizontal driver, a means for obtaining a horizontal drive clock for obtaining the sampling speed in element units and supplying the horizontal driver to the horizontal driver, and a vertical drive start timing for the vertical driver. Vertical to get the signal and speed specified in the row units A means for obtaining a dynamic clock and supplying it to the vertical driver, and a path for supplying the input video signal to the horizontal driver, which is provided in the path, compares the level of the input video signal with the output signal from the horizontal receiver, and inputs When the difference between the video signal levels is equal to or more than a predetermined value, a means for adding or subtracting a voltage of the difference to the input signal in order to speed up the response of the liquid crystal cell and supplying it to the horizontal driver bar is provided. And

[0010]

By the above means, the image display position can be moved to any position on the liquid crystal display screen. Also, a new input signal can be created by performing arithmetic processing of the input signal and the output of the display and supplied to the liquid crystal display to speed up the response.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

(Image Display Position Correction System (1)) Conventionally, the correction of the image display position of a liquid crystal projector or the like has been optically performed by mechanically moving the projection lens.

If the correction is performed by this method, it is necessary to mechanically move the projection lens, and a considerably complicated mechanism is required. Furthermore, in order to perform the correction by this method, it is necessary to make the lens considerably large, which leads to an increase in cost.

Therefore, in this embodiment, by utilizing the characteristics of the liquid crystal display device and devising its driving method,
The image display position is inexpensive and easily obtained.

FIG. 1 is a block diagram showing in detail the display correction unit in the video decoder to which the display 8000 in this embodiment is connected.

The video signal is input to the two input terminals as a digital luminance signal (Y signal) and a color signal (I, Q signal), respectively, and the digital luminance signal is converted into a digital analog converter (hereinafter referred to as D / A conversion). It is converted into an analog signal by a device 102). Similarly, the color signal is also converted into an analog signal by the D / A converter 103. The luminance signal and chrominance signal converted into analog signals are input to a matrix circuit (MTX) 104, converted into R, G, and B signals, and corresponding X drivers (105 to 10).
Sent to 7).

The sync control circuit 101 receives a system clock (8 fsc), a horizontal sync signal H synchronized with an input video signal, and a vertical sync signal V, and a display 8000.
Driver (105-107) and Y driver (108-
110) horizontal start pulse STH for controlling
Horizontal clock pulse CPH, horizontal output enable signal OEH, vertical start pulse STV, vertical clock pulse CPV, vertical output enable signal OE
V is output.

FIG. 2 is a diagram for explaining the synchronization control circuit 101 in more detail, and the circuit operation will be described below.

First, in order to stably output CPH,
Phase comparator 500, low pass filter (LPF) 50
1, voltage controlled oscillator (VCO) 502, frequency divider 5
03, the comparator 504, and the fixed value output circuit 505 form a phase locked loop (PLL).

The phase comparator 500 receives an H signal (shown in FIG. 3A) having a cycle of about 32 μsec from the outside and one horizontal period from the comparator 504 shown in FIGS. 3B and 3E. A single phase comparison pulse is input and the phases of both are compared. Then, if the phase of the phase comparison pulse is delayed from the down edge of the H signal, a positive control voltage is output as shown in FIG. If the phase of the phase comparison pulse from the comparator 504 is advanced as shown in e), a negative control voltage is output as shown in FIG.

The signal obtained from the phase comparator 500 (see FIG. 3)
(C) and (f)) are input to the LPF 501, and as shown in FIG.
The signals are shown in (d) and (g). The voltage controlled oscillator (hereinafter referred to as VCO) 502 operates so as to increase the output pulse frequency when the control voltage from the LPF 501 is on the positive side and decrease the output pulse frequency when the control voltage is negative.

The frequency division counter 503 performs an up-counting operation using the pulse from the VCO 502 as a clock, and sends the counter output to the comparator 504.

In the comparator 504, the fixed value from the fixed value output circuit 505 and the counter output from the frequency dividing counter 503 are compared.
The coincidence pulse (HIGH signal) shown in (b) and (e) is output.

The coincidence pulse is used as a reset pulse for the frequency division counter 503, and at the same time, the phase comparator 500
Is used as a phase comparison pulse as shown in FIGS. 3 (b) and 3 (e). Therefore, the matching pulse is 1
It is output once in the horizontal scanning period.

The value of the output of the fixed value output circuit 505 is shown in FIG.
Is set to a value smaller than the number of liquid crystal cells (111 to 113) in the horizontal direction shown in FIG.
By changing the value of 5, the frequency of the CPH output from the VCO 502 changes. The fixed value output circuit shown in this system can change its value from the user control unit.

The output of the frequency dividing counter 503 is also supplied to the comparator 506 and the gate forming circuit 508.

In the comparator 506, the frequency division counter 5
03 and the value obtained from the fixed value output circuit 507 are compared, and the X driver (105-1
07) STH is output.

The gate creation circuit 508 compares the counter value obtained from the frequency division counter 503 with the values (A) and (B) obtained from the fixed value output circuit 509 shown in FIG.
The OEH of the X driver (105 to 107) shown in FIG. 1 is output.

FIG. 4 is a time chart for explaining a specific circuit operation. FIG. 4A shows a reset signal of the frequency division counter 503, and this reset signal is synchronized with the horizontal blanking portion of the video signals Y, I, and Q signals shown in FIG. FIG. 4B shows a signal obtained by comparing the counter value obtained by the frequency division counter 503 and the signal (A) from the fixed value output circuit 509, which is a signal output only once in one horizontal scanning period. is there. Figure 4 (c) shows
A signal obtained by comparing the counter value obtained by the frequency division counter 503 and the signal (B) from the fixed value output circuit 509, which is a signal output only once in one horizontal scanning period.
FIG. 4 (d) sets the signals of FIG. 4 (c), and FIG. 4 (b).
2 is obtained by an RS flip-flop circuit (not shown) that uses the signal as the reset signal, and this signal becomes the OEH shown in FIG. Further, this OEH is also supplied to the selector 510. As shown in FIG. 4F, this selector 510 selects the output of VCO 502 while OEH is LOW, and externally applied VCO 5 during HIGH.
A signal higher than the frequency of the output signal of 02 is selected, derived, and output as CPH. However, the number of CPH pulses is the same as the liquid crystal cells (111 to 113) shown in FIG.
Is equal to the horizontal number of. FIG. 4E shows a signal obtained by comparing the counter value obtained from the frequency division counter 503 and the signal obtained from the fixed value output circuit 507 with 1
This signal is output only once in the horizontal scanning period, and this signal becomes STH.

CPH and ST obtained as described above
X driver (105-105 shown in FIG.
The control of 107) is performed.

Next, generation of a screen control signal in the vertical direction will be described.

In the differentiating circuit 511 shown in FIG.
The vertical sync signal V from the outside shown in (a) is given, and the signal of V is differentiated by the output of the comparator 504 as shown in (b) and (e) of FIG.
HI only in one horizontal scanning period in one vertical scanning period shown in (b)
A signal that becomes GH is obtained. The counter 512 counts up by the output of the comparator 504,
Reset is applied by the signal from the differentiating circuit 511. The signal in FIG. 5C is a signal obtained as a result of comparing the counter value from the counter 512 and the signal (D) from the fixed value output circuit 516, and is a signal output only once in one vertical scanning period. . The signal in FIG. 5D is a signal obtained by comparing the counter value from the counter 512 and the signal (E) from the fixed value output circuit 516, and is a signal output only once in one vertical scanning period. . FIG. 5E is the same as FIG.
It is obtained by an RS flip-flop circuit (not shown) in which the signal of (d) is set and the signal of FIG. 5 (c) is used as a reset signal, and this signal becomes OEV. Furthermore, OEV is
The vertical clock pulse CPV supplied to the selector 517.
Used to control. The selector 517 outputs the output of the comparator 504 as CPV while the signal shown in FIG. 5 (e) is LOW, and the signal shown in FIG. 5 (e) is HIGH.
In this case, a signal having a frequency higher than the output of the comparator 504, such as the 2nd MSB of the frequency division counter 503, is output. However, CPV output in one vertical scanning period
The number of pulses of the liquid crystal cell (111
Up to 113) in the vertical direction. Figure 5 (g)
Shows the signal form of CPV. FIG. 5F shows the counter 5
The signal obtained by comparing the counter value obtained from 12 and the signal obtained from the fixed value output circuit 513 by the comparator 514 is a signal output only once in one vertical scanning period, and this signal becomes STV.

CPV and ST obtained as described above
V driver and YEV driver shown in FIG.
110) is controlled.

The control of the X driver (105 to 107) and the Y driver (108 to 110) will be described more specifically with reference to FIG.

The circuit shown in FIG. 6A shows the liquid crystal cell for the R signal in the R, G and B panels shown in FIG. 1, and the same applies to the G signal and the B signal. Since it has the processing of 1, it is omitted here. First, as a horizontal control signal for the driver, the shift register 17
CPH and STH are input to 0, the R video signal is input to the sample hold circuit 172 (details are shown in FIG. 7B), and OEH is input to the buffer driver 173. On the other hand, CPV and STV are input to the shift register 174 and OEV is input to the buffer driver 176 as control signals of the driver in the vertical direction. The level converters 171 and 175 are for converting a TTL level signal to a liquid crystal cell control level. The sample hold circuit 172 includes a gate element 180 and a hold element 181 corresponding to a unit cell as shown in FIG.
Is composed of a buffer element 182 corresponding to each unit cell.

FIG. 7 shows the function of each control signal for correcting the image display position.

First, in the liquid crystal cell 8000, a cell area larger than the cell area to be actually driven is prepared in order to correct the image display position (the liquid crystal cell 15 in FIG. 6).
0, the same applies to the liquid crystal cells (111 to 113) shown in FIG. 1.

As described above, the CPH is controlled so as to have the same number of pulses as the liquid crystal cells arranged in the horizontal direction, and the CPH is used to display an image by sampling the image. The image signal is temporally compressed in the horizontal direction.

Next, the left and right display positions of the video signal are determined by the phase of STH, and OEH shown in FIG.
The liquid crystal cell is driven during the OW period, and the liquid crystal cell is not driven during the HIGH period. By such an operation, the liquid crystal cell is not driven during a period other than the necessary video signal period, and light is not transmitted through this portion. However, the liquid crystal cell of this example is a normally black one.

In the vertical direction as well, the same processing as in the horizontal direction is performed by CPV, STV and OEV, and the liquid crystal cell to be driven is selected.

By the above processing, the driven liquid crystal cell area is selectively selected, and the vertical and horizontal positions and the enlargement / reduction of the driven liquid crystal cell area shown in FIG. 7 can be freely changed. . When the periods (ta) and (tb) in the figure are equal and the periods (tc) and (td) are the same, the image display position on the screen is relative to the projection lens 520 as shown in FIG. Up and down, left and right even position,
When the period of (ta) in FIG. 7 is longer than that of (tb),
As shown in FIG. 8B, the image display position on the screen is shifted to the right with respect to the projection lens 520, and when the period of (ta) in FIG. 7 is shorter than (tb), it is shown in FIG. 8C. Thus, the image display position on the screen is shifted to the left with respect to the projection lens 520. The arrow in FIG. 8 indicates the scanning direction of the scanning line, and FIG. 7 is a view of the liquid crystal cell viewed from the projection lens 520 side in FIG.

Similarly in the vertical direction, when the period of (tc) in FIG. 7 is longer than (td), the image display position on the screen is shifted upward with respect to the projection lens 520, and (t) of FIG.
When the period of c) is shorter than (td), the image display position on the screen is shifted downward with respect to the projection lens 520.

As described above, according to this embodiment, the image display position is corrected by the above-described signal processing, and the image display position is corrected by moving the projection lens to shift the optical axis. The same effect can be obtained. As a result, it is possible to eliminate the mechanical portion related to the projection lens, which has been costly in the past, and to realize a significant cost reduction. If the LCD projector is tilted or misaligned, you can freely correct the image position by adjusting the holding value of the fixed value output circuit,
Can be adjusted to the normal position.

(Image Display Position Correction System (2)) Conventionally, the image display position of a liquid crystal projector or the like has been optically corrected by mechanically moving the projection lens.

If the correction is performed by this method, it is necessary to mechanically move the projection lens, and a considerably complicated mechanism is required. Furthermore, in order to perform the correction by this method, it is necessary to make the lens considerably large, which leads to an increase in cost.

Therefore, in this embodiment, by utilizing the characteristics of the liquid crystal display device and devising its driving method,
The image display position is inexpensive and easily obtained.

FIG. 9 shows the display 8 in this embodiment.
3 is a block diagram showing in detail a display correction unit in the video decoder connected to the H.000.

The video signal is input to two input terminals as a digital luminance signal (Y signal) and a color signal (I, Q signal), respectively, and the digital luminance signal is converted to a digital-analog converter (hereinafter referred to as D / A). It is converted into an analog signal by a converter 102). Similarly, the color signal is also converted into an analog signal by the D / A converter 103. The luminance signal and chrominance signal converted into analog signals are input to the matrix circuit (MTX) 104, converted into R, G, B signals, and sent to the image control circuit 100.
X driver corresponding to each from 00 (105-1
07).

The sync control circuit 101 receives the system clock 8fsc, the horizontal sync signal H, and the vertical sync signal V, and receives the liquid crystal cells (111 to 111) as the display 8000.
A horizontal start pulse STH and a horizontal clock pulse CPH for controlling the X driver (105 to 107) and the Y driver (108 to 110) that drive 113).
Vertical start pulse STV, vertical clock pulse CPV
In order to control the image control circuit 100, a horizontal output enable signal OEH and a vertical output enable signal OEV are output.
Details of the synchronization control circuit 101 are as described in FIG. Therefore, the timing charts shown in FIGS. 3 to 5 also apply to this synchronization control circuit 101 as they are. The same applies to the X driver and the Y driver described with reference to FIG. However, in this embodiment, OEH and OEV are not input to the buffer drivers 173 and 176.

In this embodiment, the CPH and STH obtained from the synchronous control circuit 101 control the X driver (105 to 107) shown in FIG. 9, and the OEH controls the image control circuit 100. Different from the embodiment.

C obtained from the synchronization control circuit 101
The Y driver (108 shown in FIG. 9 is selected by PV or STV.
.About.110) and the image control circuit 100 is controlled by the OEV.

In the image control circuit 100, OEH, OEV
Send out the signal sent from the MTX 104 only during the period when both are LOW, and one of OEH and OEV is HIG.
During the H period, the signal path is configured to send the black level image signal.

FIG. 10 shows the functions of the respective control signals for correcting the image display position. As the liquid crystal cell, a cell larger than an actual image signal (a period other than a period in which the black level is sent by the image control circuit 100) is prepared in order to correct the image display position.

As described above, the CPH is controlled to have the same number of pulses as the number of liquid crystal cells arranged in the horizontal direction, and the CPH is used to display an image by sampling. The image signal is temporally compressed in the horizontal direction. In the vertical direction as well, similar processing is performed by the CPV and STV in the horizontal direction, and the display area of the image signal is selected. The black level signal is output by the image control circuit 8100 during the period other than the image signal period that is actually displayed.

By the above processing, the vertical and horizontal positions and the enlargement / reduction of the image signal period can be freely changed, and the periods (ta) and (tb) of FIG.
When the periods (tc) and (td) are the same, FIG.
As shown in FIG. 8, the image display position on the screen is even with respect to the projection lens 520 in the vertical and horizontal directions. When the period of (ta) in FIG. 10 is longer than (tb), FIG.
As shown in FIG. 8, the image display position on the screen is shifted to the right with respect to the projection lens 520, and when the period of (ta) in FIG. 10 is shorter than (tb), the screen is displayed as shown in FIG. The image display position for is shifted to the left with respect to the projection lens 520.

Similarly in the vertical direction, when the period (tc) in FIG. 10 is longer than (td), the image display position on the screen is shifted upward with respect to the projection lens 520, and the position (tc) in FIG. When the period is shorter than (td), the image display position on the screen is shifted downward with respect to the projection lens 520.

As described above, according to this embodiment, the image display position can be corrected by the above-mentioned signal processing, and the image display position which is conventionally obtained by moving the projection lens to shift the optical axis is used. The same effect as the correction can be obtained. As a result, it is possible to eliminate the mechanical portion related to the projection lens, which has been costly in the past, and to realize a significant cost reduction.

(Time Compression / Expansion System by Variable Drive Frequency) The conventional image signal time compression / expansion circuit is performed by using the following two methods.

The first method is Bosch's Japanese Patent Laid-Open No. 59-59.
No. 61371, an interpolation filter and a line memory are combined to perform time compression / expansion. The second method is Siemens's Tokuhei 2-16067 or Sony's Tokuhei 2
No. 17867, only the line memory is used, and the time compression and expansion are performed by changing the frequencies of the write clock and the read clock to the memory. Each of the above two methods requires a line memory and a circuit for controlling the line memory is complicated, so that the cost is considerably high.

Therefore, in this embodiment, the characteristics of the liquid crystal display device are utilized to devise the driving method so that the time compression / expansion of the image signal can be easily obtained.

FIG. 11 shows in detail the display correction unit in the video decoder to which the display 8000 in this embodiment is connected.

First, the video signal is input as a digital luminance signal (Y signal) and a color signal (I, Q signal) from the two input terminals, and the digital luminance signal is converted into a digital-analog converter (hereinafter D / A). It is converted into an analog signal by an A converter 102). Similarly for color signals D /
It is converted into an analog signal by the A converter 103. The luminance signal and the chrominance signal converted into analog signals are input to the matrix circuit (MTX) 104, converted into R, G, and B signals, sent out to the image control circuit 100, and respectively corresponded from the image control circuit 100. X driver (10
5-107).

In the sync control circuit 101, the system clock (8 fsc), the horizontal sync signal H, and the vertical sync signal V are input, and the X driver (105 to 107) and the Y driver for driving the liquid crystal cells (111 to 113). (1
08-110) for controlling the horizontal start pulse S
TH, a horizontal clock pulse CPH, a vertical start pulse STV, and a vertical clock pulse CPV are generated, and a horizontal output enable signal OEH is generated to control the image control circuit 100.

FIG. 12 shows the details of the synchronization control circuit 101.

First, in order to stably output the CPH pulse, the phase comparator 500, LPF 501, VCO 50
2, the frequency division counter 503, the comparator 504, and the fixed value output circuit 505, the phase locked loop (P
LL) is formed. In the phase comparator 500, an H signal (FIG. 13 (a)) having a cycle of about 32 μsec is supplied from the outside.
3 (b) and 3 (e), the phase comparison pulse is input once in one horizontal period from the comparator 504, the down edge of the H signal and the phase of the comparison pulse are compared, and the down edge of the H signal is input. If the phase of the comparison pulse lags behind, a positive control voltage is output as shown in FIG. 13C, and conversely, a positive control voltage is output rather than the down edge of the H signal.
If the phase of the comparison pulse is advanced as shown in (e), a negative control voltage is output as shown in FIG. 13 (f). Signal from the phase comparator 500 (Fig. 13 (c)
And (f) are input to the LPF 501, and (d) in FIG.
And (g), which are supplied to the control terminal of the VCO 502.

In the VCO 502, the circuit operates so as to increase the output pulse frequency when the control voltage from the LPF 501 is on the plus side and decrease the output pulse frequency when the control voltage is minus. In the frequency division counter 503,
An up-count operation is performed by using a pulse obtained from O502 as a clock, and a counter output is supplied to the comparator 504. The comparator 504 compares the fixed value from the fixed value output circuit 505 with the counter output from the frequency dividing counter 503, and when the values match,
The coincidence pulse (HIGH signal) shown in FIGS. 13B and 13E is output. The coincidence pulse is used as a reset pulse for the frequency division counter 503, and at the same time, the phase comparator 5
In 00, it is used as a phase comparison pulse. Therefore,
The coincidence pulse is output once in one horizontal scanning period.

The fixed value output circuit 505 is set to a value smaller than the number of the liquid crystal cells (111 to 113) shown in FIG. 11 in the horizontal direction when the image is compressed, and the liquid crystal cell (111) when the image is expanded. To 113), the frequency of the CPH output from the VCO 502 is changed by changing the value of the fixed value output circuit 505.

The count value of the frequency division counter 503 is supplied to the comparator 506 and the gate forming circuit 5
08 is being supplied. In the comparator 506, the counter value from the frequency division counter 503 and the fixed value output circuit 50
The values obtained from No. 7 are compared, and the STH of the X driver (105 to 107) shown in FIG. 11 is output. In the gate creation circuit 508, the counter value from the frequency division counter 503 and the fixed value output circuit 509 (A),
The values of (B) are compared, and the image control circuit 10 shown in FIG.
OEH for 0 is output.

FIG. 14 is a time chart for explaining a specific circuit operation of the synchronization control circuit 101. Figure 1
4A shows a reset signal of the frequency dividing counter 503, which is synchronized with the horizontal blanking portion of the video signals Y, I, and Q signals shown in FIG.
FIG. 14B shows a counter value obtained from the frequency division counter 503 and a signal (A) obtained from the fixed value output circuit 509.
Is a signal that is output only once in one horizontal scanning period. FIG. 14C shows a counter value obtained from the frequency division counter 503 and the fixed value output circuit 5.
The signal obtained by comparing the signal (B) obtained from 09,
This signal is output only once in one horizontal scanning period. The signals (A) and (B) obtained from the fixed value output circuit 509 have the values (A)-(B) in the horizontal direction of the liquid crystal cells (111 to 113) shown in FIG. 11 when the image is compressed. When the value is set to a value smaller than the number and the image is expanded,
Is set to a value larger than the number of liquid crystal cells (111 to 113) in the horizontal direction. FIG. 14 (d) is obtained by an RS flip-flop circuit (not shown) in which the signal in FIG. 14 (c) is set and the signal in FIG. 14 (b) is used as a reset signal. The OEH shown in FIG. 12 is obtained, and when the image is expanded, the OEH is always L.
It's set to be OW. Further, the OEH is also supplied to the selector 510, and when compressing an image, the OEH shown in FIG.
As shown in FIG. 4 (f), VCO5 is applied while OEH is LOW.
02 output is selected, and during the HIGH period, a signal having a frequency higher than the frequency of the output signal of the VCO 502 provided from the outside is selected, and the CPH shown in FIG.
Is output as. However, when compressing the image, C
The number of PH pulses is equal to the number of the liquid crystal cells (111 to 113) shown in FIG. 11 in the horizontal direction. OEH is always LOW when expanding the image, so C
The signal output as PH is always the signal given from the VCO 502. Therefore, when compressing an image, C
The number of PH pulses is the liquid crystal cell (1
11 to 113) in the horizontal direction. 14
(E) is a signal obtained by comparing the counter value obtained from the frequency dividing counter 503 and the signal obtained from the fixed value output circuit 507, which is a signal output only once in one horizontal scanning period. The STH shown in FIGS. 11 and 12 is obtained.

CPH and STH obtained as described above
X driver (105-107) shown in FIG. 11 by
The image control circuit 8100 shown in FIG. 11 is controlled by the OEH.

Next, generation of a screen control signal in the vertical direction will be described.

The differentiating circuit 511 shown in FIG.
The external vertical synchronizing signal V shown in (g) is applied, and the signal of V is differentiated by the output of the comparator 504 shown in FIGS. 14 (b) and 14 (e).
As shown in (h), the differential signal becomes HIGH only in one horizontal scanning period in one vertical scanning period. This differentiating circuit 511
Is output to the unter 512. The counter 512 counts up by the output of the comparator 504 and is reset by the signal obtained from the differentiating circuit 511. FIG. 14I shows the counter 512.
The signal obtained by comparing the obtained counter value with the signal obtained from the fixed value output circuit 513 is a signal output only once in one vertical scanning period.
The STV shown in FIG.

CPV and STV obtained as described above
By the Y driver (108-110) shown in FIG.
Is controlled.

FIG. 15 shows the X driver (105 to 10
7) shows a specific configuration of the Y driver (108 to 110). This structure is the same as that described in FIG. 6, but OEH and OEV are not supplied to the buffer drivers 173 and 176, respectively.

The circuit shown in FIG. 15 shows the liquid crystal cell for the R signal of the R, G, B panels shown in FIG. 11, and the same processing is performed for the G signal and the B signal. Since it has, it is omitted here. First, the shift register 170 is used as a horizontal control signal for the driver.
12, CPH and STH shown in FIG. 12 are input, and the R video signal is input to the sample hold circuit 172. on the other hand,
The vertical driver control signals include the shift register 174 shown in FIG. 15 and the CPV and STV shown in FIG.
Is entered. The level converters 171 and 175 have T
It is for converting a TL level signal into a level for liquid crystal cell control.

In the image control circuit 100 shown in FIG. 11, the signal sent from the MTX 104 is sent only while the OEH is LOW, and the black level image signal is sent while the OEH is HIGH.

FIG. 16 is a diagram for explaining the function of each control signal when compressing an image. First, the liquid crystal cells are arranged so that a screen having a ratio of (α) to (β) of 16: 9 can be formed when the image is not time-compressed and expanded (the liquid crystal cells (111 to 113 in FIG. 11). ) Is also the same). When compressing an image, the CPH is controlled so as to have the same number of pulses as the liquid crystal cells arranged in the horizontal direction, and the CPH signal is used to sample and display an image. In the vertical direction, the display position of the image signal is determined by STV, and cells for one horizontal line are simultaneously driven by CPV. Next, when the image is expanded, the image signal drives the entire liquid crystal cell, as shown in FIG.
As described above, the number of CPH pulses in one horizontal period is larger than the number of liquid crystal cells in the horizontal direction. Therefore, STH determines which period in one horizontal image signal period is displayed on the screen. ing.

Further, when performing image compression / expansion in the vertical direction, a frame memory (not shown) is arranged in front of the D / A converters 102 and 103 in FIG. 11, and the image signal is read out in the vertical direction. In contrast to the case of performing the image compression / expansion in the horizontal direction, it can be realized by rotating the liquid crystal cell by 90 degrees.

As described above, according to this embodiment, by performing the above-mentioned signal processing, it becomes possible to perform time compression / expansion of an image signal without using a line memory, and a great cost reduction is realized.

(LCD Response Speed Improvement Driver System) As a method for improving the response speed of the conventional LCD, the signal one frame before the image signal is compared with the current signal, and when the level difference is larger than a certain value, the A value greater than the level difference was given to the LCD to improve the response speed. However, in order to use this method,
A memory circuit for holding the frame is required, which leads to an increase in cost.

Therefore, in this embodiment, by utilizing the characteristics of the liquid crystal display device, the liquid crystal cell itself is regarded as a frame memory (delay means), and the response speed can be easily adjusted by obtaining the time adjustment for one frame of the image signal. I am trying to improve.

FIG. 18 shows an embodiment thereof.

First, an image signal is input as a digital luminance signal (Y signal) and a color signal (I, Q signal) from two input terminals, and the digital luminance signal is converted into a digital analog converter (hereinafter referred to as D / A). It is converted into an analog signal by a converter 102). D / A for color signals as well
It is converted into an analog signal by the converter 103. The luminance signal and chrominance signal converted into analog signals are input to the matrix circuit (MTX) 104, converted into R, G, and B signals, and sent to the voltage control circuits (300 to 8302), and the voltage control circuit (300 ~ 8302) to the corresponding X driver (105-107).

A system clock 8fsc, a horizontal synchronizing signal H, and a vertical synchronizing signal V are input to the synchronization control circuit 200, and a liquid crystal cell (111 to 111) as a display 8000 is input.
113) to drive the X driver (105 to 10)
7) and horizontal start pulses STH1 and STH2 for controlling the Y drivers (108 to 110), a horizontal clock pulse CPH, a vertical start pulse STV, and a vertical clock pulse CPV.

FIG. 19 shows the details of the synchronization control circuit 200. A horizontal synchronizing signal H from the outside shown in FIG. 20 (a) is applied to the differentiating circuit 600, and the signal of H is differentiated by the signal of 8fsc, and as shown in FIG. 20 (b), in one horizontal scanning period. A signal that becomes HIGH only once is obtained. This signal is supplied to the counter 601. The counter 601 counts up with a signal of 8 fsc and is reset with a signal from the differentiating circuit 600. FIG. 20C is a signal obtained by comparing the counter value from the counter 601 and the signal from the fixed value output circuit 602, which is a signal output only once in one horizontal scanning period. It becomes STH2 shown in FIG.
The signal obtained from the comparator 603 is further input to the latch circuit 608, and the latch circuit 608 outputs 8f.
Latched by sc, about 35nsec than STH2
The delayed STH1 is output. 8fs shown in FIG.
The c signal is output as CPH shown in FIG.

CPH and STH obtained as described above
1 by the X driver (105-10
Control of 7) is performed, and control of the X receivers (8204 to 8206) is performed by CPH and STH2. The X receivers (8204 to 8206) are liquid crystal cells (111).
To 113) are input.

Next, the creation of the screen control signal in the vertical direction will be described.

The differentiating circuit 604 of FIG.
The vertical synchronization signal V is given from the outside as shown in (e),
HI once per horizontal scanning period obtained from the differentiating circuit 600
The signal of V is differentiated by the signal of GH, and FIG.
HI only in one horizontal scanning period in one vertical scanning period shown in (f)
The signal becomes GH. The counter 605 counts up with a signal that becomes HIGH once in one horizontal scanning period obtained from the differentiating circuit 600.
It is reset by the signal obtained from 4. FIG. 20G shows a signal obtained by comparing the counter value obtained from the counter 605 and the signal from the fixed value output circuit 606, which is output only once in one vertical scanning period. This signal becomes the STV shown in FIG.

CPV and STV obtained as described above
By the Y driver (108-110) shown in FIG.
Is controlled.

FIG. 21 shows the X driver (105 to 10).
FIG. 7 is a diagram for more specifically explaining control of 7), X receivers (8204 to 8206), and Y drivers (108 to 110). This circuit shows the liquid crystal cell for the R signal of the R, G, B panels shown in FIG. 18, and has the same processing for the G signal and the B signal. Will be omitted. First, as the control signals of the horizontal X driver (105 to 107), the shift register 170 includes the CPH shown in FIG.
STH1 is input and R is input to the sample hold circuit 172.
The video signal of is input. Horizontal X receiver (8
204 to 8206), CPH and STH2 shown in FIG. 19 are input to the shift register 622,
The sample-hold circuit 620 holds the voltage value of one frame-one clock before. Sample hold circuit 620
The voltage value held in the delay circuit 623 is delayed by the delay circuit 623 and output as the voltage value one frame before, and the voltage correction circuit 624
Then, the potential leaked in the liquid crystal cell is corrected and sent to the voltage control circuit (300-8302) shown in FIG. In the example of FIG. 21, it is the voltage control circuit 300.

On the other hand, as the vertical control signal for the driver, the CP shown in FIG.
V and STV are input. Level converters 171, 1
Reference numerals 75 and 621 are for converting a TTL level signal to a liquid crystal cell control level.

FIG. 22 is a diagram for explaining the operation of improving the response speed of the LCD by the above circuit. Normally, when the liquid crystal cell is normally black, the voltage applied to the liquid crystal cell is −5 V for the black level (the lowest level of the image signal), 5 V for the white level (the highest level of the image signal), and the gray level (the middle level of the image signal) 22 is defined as 0 V,
Voltages corresponding to the image signal changing from the black level as shown in (a) to the white level in the next frame are black level -5V and white level 5V as shown in FIG. However, the response of the LCD corresponding thereto is slow enough to complete a complete response in a few frames as shown in FIG. When the image is projected on the screen at such a response speed, the moving image becomes visually blurred with a trailing tail. Therefore, the voltage control circuit (300 to 8302) determines the levels of the current signal and the signal one frame before held in the liquid crystal cell.
22. If the level difference is equal to or larger than the specified value, the level difference is multiplied by a coefficient to be added to the input signal to perform voltage control as shown in FIG. By controlling the voltage in this way, the response speed of the LCD can be improved as shown in (e) of the figure, and it is possible to eliminate the blurring feeling that was present in the moving image as before the countermeasure.

The voltage control calculation formula (15) is shown below.

Ov = Iv + (Iv-Iv ′) * k (15) Ov: Output of voltage control circuit (300 to 302) Iv: Output signal of MTX 104 Iv ′: X receiver (204 to 206) Output k: Coefficient (0 ≦ k ≦ 1) As described above, according to this embodiment, by performing the above-mentioned signal processing, the response speed of the conventional LCD is improved, and no failure occurs even in a moving image. The image can be projected on the screen.

(Multi-panel LCD drive system)
When converting a conventional LCD television into a multi-panel,
A plurality of identical LCD televisions are arranged and a complicated and fast drive circuit is required. This embodiment realizes a system which has a simple structure and can realize a multi-panel structure without requiring a high-speed drive circuit as in the prior art.

FIG. 23 shows the embodiment.

The image signals are digital luminance signals (Y signals) and color signals (I, Q signals) from two input terminals respectively.
As line memories 400 and 401, respectively.
Entered in. In the line memories 400 and 401, the input digital image signal is controlled by the write clock (WC) and the read clock (RC) output from the synchronization control circuit 8402, and the brightness signals Y1 to Y4, as described later in detail. The color signals I1 to I4 and Q1 to Q4 are output.

The image signal obtained from the line memory 400 is converted into an analog signal by a digital-analog converter (hereinafter referred to as D / A converter) 102. The color signal obtained from the line memory 401 is similarly converted into an analog signal by the D / A converter 103. The luminance signal and chrominance signal converted into analog signals are input to a matrix circuit (MTX) 104, converted into R, G, and B signals, and corresponding X drivers (105 to 10).
Sent to 7).

In the synchronization control circuit 402, the system clock 8fsc, the horizontal synchronization signal H, and the vertical synchronization signal V are input, and the liquid crystal cells (111 to 111) as the display 8000 are input.
113) to drive the X driver (105 to 10)
7) and a horizontal start pulse (STH), a horizontal clock pulse (CPH), a vertical start pulse (STV), and a vertical clock pulse (CPV) for controlling the Y drivers (108 to 110) are created.

FIG. 24 shows the details of the synchronization control circuit 402.

A horizontal synchronizing signal H from the outside shown in FIG. 25 (a) is applied to the differentiating circuit 600, and the H signal is differentiated by a signal of 8 fsc, so that one horizontal scanning period shown in FIG. 25 (b). A signal that becomes HIGH is output only once. This signal is supplied to the counter 601. The counter 601 counts up with a signal of 8 fsc and is reset with a signal from the differentiating circuit 600. FIG. 25C shows a signal obtained by comparing the counter value from the counter 601 and the signal from the fixed value output circuit 602 in the comparator 603, which is a signal output only once in one horizontal scanning period. Signal is Figure 23
STH shown in FIG.

The 8 fsc signal shown in FIG. 23 is used as CPH and is also used as a write clock (WC) for the line memories 400 and 401.

CPH and STH obtained as described above
By X driver (105-107) shown in FIG.
Is controlled. The line memory 400 shown in FIG.
The read reset signal (RC) of 401 is selected by the selector circuit 609 of FIG. 24 according to the configuration of the multi-screen, 8 fsc is selected in the case of the one-screen configuration, and the LSB output of the counter 601 is selected in the case of the four-screen configuration. Is 1
In the case of a 6-screen configuration, the 2nd LSB output of the counter 601 is selected.

Next, generation of a screen control signal in the vertical direction will be described.

The differentiating circuit 604 of FIG.
The vertical synchronizing signal V from the outside shown in (d) is given and obtained from the differentiating circuit 600 as shown in FIG.
The V signal is differentiated by a signal that becomes HIGH once in the horizontal scanning period, and H is generated only in one horizontal scanning period in one vertical scanning period.
The signal becomes IGH. This signal is input to the counter 605. The counter 605 counts up with a signal that becomes HIGH once in one horizontal scanning period from the differentiating circuit 600, and is reset with a signal obtained from the differentiating circuit 604. FIG. 25F shows a counter value from the counter 605 and a fixed value output circuit 606.
Is a signal obtained by comparing the signals from the above with the comparator 607 and is output only once in one vertical scanning period. This signal becomes the STV shown in FIG. In the CPV, the output of the differentiating circuit 600 is selected by the selector circuit 610 when the multi-screen configuration is composed of one screen, and the output of the OR circuit 617 is selected when the multi-screen configuration is four screens.
In the case of the screen configuration, the output of the OR circuit 618 is selected.
The OR circuit 617 takes the logical sum of 8 fsc and the output obtained by passing the output of the differentiating circuit 600 to the latch circuits 611 and 612. The OR circuit 618 takes the logical OR of the output of the differentiating circuit 600 passed through the latch circuits 611 to 614, the output of the differentiating circuit 600 passing through the latch circuits 611 to 616, and the OR circuit 617. There is. Each latch circuit is driven by 8fsc.

The output signal from the OR circuit 617 is output as two pulses in the H blanking period of one horizontal scanning period, and the X driver (105 to 1 shown in FIG.
The signal held in 07) is the Y driver (108-
110) to drive two lines simultaneously. The output signal from the OR circuit 618 is output as four pulses in the H blanking period of one horizontal scanning period.
The signals held by the X driver (105 to 107) shown in (4) are simultaneously driven by the Y driver (108 to 110) for four lines.

In the OE control circuit 619, the OEV
The signal levels of 1 to OEV4 are controlled, and it is always LOW when the multi-screen configuration is the one-screen configuration, and OEV1 and OEV2 are shown in FIG.
Controlled as shown in (a) and (b), in the case of a 16-screen configuration, OEV1 to OEV4 are shown in FIGS.
(E) It is controlled as shown in (f).

CPV and ST obtained as described above
Control of the Y driver (108 to 110) shown in FIG. 23 is performed by V and OEV1 to OEV4.

FIG. 27 shows the X driver (105-10
7) is a diagram showing control of Y drivers (108 to 110). This circuit is shown for the liquid crystal cell for the R signal in the R, G, B panel shown in FIG. 23, and has the same processing for the G signal and the B signal. Omit it. First, the horizontal driver (1
05 to 107), the shift register 1
The CPH and STH shown in FIG. 24 are input to 70, and the R video signal is input to the sample hold circuit 172.

On the other hand, as the control signal for the driver in the vertical direction, the shift register 174 has the CPV shown in FIG.
STV is input and OE is sent to the buffer driver 176.
V1 is input. Level converters 171, 175
Is for converting a TTL level signal to a liquid crystal cell control level.

Next, the control of the line memories 400 and 401 will be described in detail.

As shown in FIG. 28, the line memory 400,
The 401 has four output ports. If the multi-screen configuration is 4 screens, 1 is set according to the read clock.
Data can be output by dividing the horizontal scanning period into two parts. If the multi-screen configuration is 16 screens,
It is possible to output data by dividing one horizontal scanning period into four parts according to the read clock.
As described above, by controlling each signal according to the number of multi-screens, it is possible to make all LCDTVs forming the multi-screen the same.

As described above, according to this embodiment, by performing the above-described signal processing, the X driver is not complicatedly driven at high speed as in the conventional case, and the configuration of the X driver is greatly simplified. , It becomes possible to move at low speed.

The present invention is not limited to the embodiments shown in the above drawings, but may have a composite structure in which the means for driving the liquid crystal cell shown in each drawing are combined.

[0115]

As described above, according to the present invention,
The image display position can be freely adjusted with respect to the liquid crystal display unit by an inexpensive means. Further, in order to speed up the response speed of the liquid crystal display, the liquid crystal display can be regarded as a frame memory, and a new input signal can be created by performing arithmetic processing on the input signal and the output of the display.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a specific configuration example of the synchronization control circuit of FIG.

FIG. 3 is a timing diagram shown to explain the operation of the circuit of FIG.

FIG. 4 is a timing diagram shown for explaining the operation of the circuit of FIG.

5 is a timing diagram shown to explain the operation of the circuit of FIG.

FIG. 6 is a diagram showing an X and Y driver of a display correction unit.

FIG. 7 is an explanatory diagram of an operation of a display correction unit and a display screen.

FIG. 8 is an explanatory diagram shown for explaining the effect of the display correction unit.

FIG. 9 is a diagram showing another embodiment of the display correction unit according to the present invention.

FIG. 10 is an explanatory diagram shown for explaining the display correction unit in FIG. 9.

FIG. 11 is a diagram showing still another embodiment of the display correction unit.

12 is a diagram showing a specific configuration example of the synchronization control circuit of FIG.

FIG. 13 is a timing diagram shown for explaining the operation of the circuit of FIG. 11.

FIG. 14 is a timing chart shown for explaining the operation of the circuit of FIG. 11.

15 is a diagram showing the X and Y drivers of FIG. 11. FIG.

16 is an explanatory diagram of the operation and display screen of the display correction unit in FIG.

17 is an explanatory diagram of the operation and display screen of the display correction unit in FIG. 11.

FIG. 18 is a diagram showing still another embodiment of the display correction unit.

19 is a diagram showing a specific configuration example of the synchronization control circuit of FIG.

20 is a timing chart shown for explaining the operation of the circuit of FIG.

21 is a diagram showing an X driver and a Y driver of the display correction unit in FIG.

22 is an explanatory diagram shown for explaining the effect of the display correction unit in FIG. 18. FIG.

FIG. 23 is a diagram showing still another embodiment of the display correction unit.

FIG. 24 is a diagram showing a specific configuration example of the synchronization control circuit of FIG. 23.

FIG. 25 is a timing chart shown for explaining the operation of the circuit of FIG. 23.

FIG. 26 is a timing chart shown for explaining the operation of the circuit of FIG. 23.

FIG. 27 is a diagram showing an X, Y driver of the display correction unit in FIG. 23.

FIG. 28 is an explanatory diagram shown for explaining the operation of the display correction unit in FIG. 23.

[Explanation of symbols]

101 ... Synchronous control circuit, 102, 103 ... Digital-analog (D / A) converter, 104 ... Matrix circuit, 1
05-107 ... X driver, 108-110 ... Y driver, 111-113 ... Liquid crystal cell, 500 ... Phase comparator, 501 ... LPF, 502 ... Voltage controlled oscillator (VC)
O), 503 ... Frequency division counter, 504, 506, 514
... Comparator, 505, 507, 509, 513, 5
16 ... Fixed value output circuit, 508, 515 ... Gate creation circuit, 511 ... Differentiation circuit, 512 ... Counter, 510, 5
17 ... Selector, 170 ... Shift register, 171 ... Level converter, 172 ... Sample and hold circuit, 17
3 ... buffer driver, 174 ... shift register, 1
75 ... Level converter, 176 ... Buffer driver, 180 ... Gate element, 181 ... Hold element, 18
2 ... Buffer element, 520 ... Projection lens, 100 ... Image control circuit, 300, 301, 302 ... Voltage control circuit, 2
00 ... Synchronous control circuit, 204-205 ... X receiver,
600, 604 ... Differentiation circuit, 601, 605 ... Counter, 602, 606 ... Fixed value output circuit, 603, 607
... Comparator, 608 ... Latch circuit, 620 ... Sample and hold circuit, 621 ... Level converter, 622 ...
Shift register, 400, 401 ... Line memory, 40
2 ... Synchronous control circuit, 611-616 ... Latch circuit, 61
8 ... OR circuit, 610 ... Selector.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Satoshi Ishii 8 Shinsita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture Home Appliances Technology Laboratory, Toshiba Corporation Yokohama Works (72) Inventor Seijiro Yasugi Isogo-ku, Yokohama-shi, Kanagawa Shin-Sugita-cho 8 Home Appliance Technology Laboratory, Toshiba Corporation Yokohama Works (72) Inventor Noriya Sakamoto 8-Shin-Sugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Home Appliance Technology Laboratory, Toshiba Yokohama Office (72) Inventor Yoshihiko Ogawa 8th Shinsugita-cho, Isogo-ku, Yokohama, Kanagawa Prefecture Home Appliances Technology Research Laboratory, Toshiba Yokohama Works (72) Inventor Atsushi Hirota 8th, Shinsugita-cho, Isogo-ku, Yokohama City, Kanagawa Prefecture 72) Inventor Koichi Noguchi 8 Yokohama Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Stock company Toshiba Yokohama Tokoro consumer electronics intra-technology Research Institute (72) inventor Koichi Sato, Minato-ku, Tokyo Shimbashi 3-chome, No. 3, No. 9 Toshiba error over buoy Yee within Co., Ltd.

Claims (11)

[Claims] 1. A liquid crystal cell in which liquid crystal display elements are arranged in a matrix, a horizontal driver for driving the elements of the liquid crystal cell in the horizontal arrangement direction by sampling the input video signal in the horizontal direction, and the input video signal. So as to sample every horizontal line, a vertical driver that drives the liquid crystal cell elements in a row unit in the vertical direction, obtains a horizontal drive start timing signal of the horizontal driver, and obtains the sampling speed in each element. A horizontal drive clock for obtaining a horizontal enable timing signal for determining a horizontal period for supplying the sampled signal to the element, a vertical drive start timing signal for the vertical driver, and a speed specified by the row unit. The vertical drive clock and the vertical period specified by the row unit A means for obtaining a vertical enable timing signal that defines the horizontal period, and a horizontal enable timing signal that defines the horizontal period is a high-speed clock that is a higher frequency of the horizontal drive clock when the period indicates other than the designated period, and a frequency when the period indicates the designated period. And a means for switching to a low-speed clock that lowers the vertical period, when the vertical enable timing signal that defines the vertical period indicates a period other than the designated period, a high-speed clock in which the frequency of the vertical drive clock is increased, and a frequency when the designated period is indicated A television signal display device comprising: means for switching to a low-speed clock with a lower frequency, and means for arbitrarily changing a designated period of the horizontal enable timing signal and the vertical enable timing signal. 2. The liquid crystal cell is arranged between a light source of a projector and a lens system, and is displayed on a screen on which an image of the liquid crystal cell is projected for a designated period of the horizontal enable timing signal and the vertical enable timing signal. The television signal display device according to claim 1, wherein the television signal display device is adjusted for image display position correction. 3. The horizontal drive start timing signal is a phase locked loop circuit that is phase-locked with a horizontal sync signal of an input video signal, a counter that counts output pulses of the phase locked loop circuit, an output of this counter and a fixed value. The horizontal enable timing signal is generated by a gate circuit that compares the counter and the output of the counter with a plurality of fixed values to obtain a gate pulse, and outputs the gate pulse as the horizontal enable timing signal. The television signal display device according to claim 1, wherein the television signal display device is produced. 4. The horizontal drive clock is supplied with an output pulse of the phase-locked loop circuit and a high-speed pulse given from the outside, and is output from a selector which selectively switches the pulse with the horizontal enable timing signal. The television signal display device according to claim 1, wherein: 5. The vertical drive start timing signal includes a phase locked loop circuit that is phase-locked with a horizontal synchronous signal of an input video signal, a first counter that counts output pulses of the phase locked loop circuit, and a first counter. A first comparator that compares a counter output with a fixed value to obtain a coincidence pulse in a horizontal cycle, a differentiating circuit that takes out the vertical synchronizing signal of the input video signal in synchronization with the first comparator output, and a differentiating circuit Of the second counter which is reset by the output of the counter and counts the output of the comparator, and the second comparator which compares the output of the second counter with a fixed value and obtains the start timing pulse when they match each other. The vertical enable timing signal compares the output of the second counter with a plurality of fixed values to obtain a gate pulse. 2. The television signal display device according to claim 1, wherein the television signal display device is created by a gate circuit that outputs the vertical enable timing signal. 6. The vertical drive clock is input from the first counter output and the first comparator output, and is output from a selector that selectively switches the output by the vertical enable timing signal. The television signal display device according to claim 5. 7. A liquid crystal cell in which liquid crystal display elements are arranged in a matrix, a horizontal driver for driving the elements of the liquid crystal cell in the horizontal arrangement direction by sampling the input video signal in the horizontal direction, and the input video signal. So as to sample every horizontal line, a vertical driver that drives the liquid crystal cell elements in a row unit in the vertical direction, obtains a horizontal drive start timing signal of the horizontal driver, and obtains the sampling speed in each element. Means for obtaining a horizontal drive clock for supplying the horizontal driver to the horizontal driver, a vertical drive start timing signal for the vertical driver, and a vertical drive clock for obtaining a speed designated by the row unit and supplying the vertical drive clock to the vertical driver. Means and a horizontal period for supplying an input video signal to the horizontal driver A horizontal enable timing signal specifying means for obtaining a vertical enable timing signal that specifies the vertical period, provided in a path of said input video signal supplied to the horizontal Doraba, and the horizontal enable timing signal,
Image control means for supplying the input video signal to the horizontal driver only during a period specified by the vertical enable timing signal and for supplying a black level signal during the other period, and when the horizontal enable timing signal indicates a period other than the specified period Is a high-speed clock in which the frequency of the horizontal drive clock is increased, and means for switching to a low-speed clock in which the frequency is lowered when the time is within a designated period, and the vertical drive clock is used when the vertical enable timing signal indicates a period other than the designated period. And a means for switching to a low-speed clock having a lower frequency when the designated period is indicated, and a means for arbitrarily changing the designated period of the horizontal enable timing signal and the vertical enable timing signal. A television signal display device characterized by the above. 8. A liquid crystal cell in which liquid crystal display elements are arranged in a matrix, a horizontal driver for driving the elements of the liquid crystal cell in the horizontal arrangement direction by sampling the input video signal in the horizontal direction, and the input video signal. So as to sample every horizontal line, a vertical driver that drives the liquid crystal cell elements in a row unit in the vertical direction, obtains a horizontal drive start timing signal of the horizontal driver, and obtains the sampling speed in each element. Means for obtaining a horizontal drive clock for supplying to the horizontal driver, a vertical drive start timing signal for the vertical driver, a vertical drive clock for obtaining a speed specified in the row unit, and a vertical specified in the row unit A vertical enable timing signal that determines the period is obtained to the vertical driver. Supplying means, means for obtaining a horizontal enable timing signal that specifies a horizontal period for supplying an input video signal to the horizontal driver, and a horizontal enable timing provided in a path of the input video signal supplied to the horizontal driver. An image control unit that supplies an input video signal to the horizontal driver only during a period specified by a signal and supplies a black level signal during other periods, and the horizontal enable timing signal when the horizontal enable timing signal indicates a period other than the specified period. A high-speed clock with an increased drive clock frequency, and means for switching to a low-speed clock with a low frequency when indicating a designated period, and the vertical drive clock frequency when the vertical enable timing signal indicates a period other than the designated period. A high-speed clock with a high frequency, and a low frequency with a low A television signal display device comprising: means for switching to a high-speed clock; and means for arbitrarily changing the frequency of the low-speed clock and enabling image compression / expansion of the liquid crystal cell. 9. The television signal display device according to claim 8, wherein the input video signal is introduced through a frame memory in which a writing direction and a reading direction can be switched from horizontal to vertical. . 10. A liquid crystal cell in which liquid crystal display elements are arranged in a matrix, a horizontal driver for driving the elements of the liquid crystal cell in the horizontal arrangement direction by sampling the input video signal in the horizontal direction, and the input video signal. So as to sample every horizontal line, a vertical driver that drives the elements of the liquid crystal cell in the vertical direction by designating the elements of the liquid crystal cell, and a signal that is opposed to the horizontal driver and that is output from the liquid crystal cell is latched. A horizontal receiver, a horizontal drive start timing signal of the horizontal driver, a means for obtaining a horizontal drive clock for obtaining the sampling speed in element units and supplying the horizontal driver to the horizontal driver, a vertical drive start timing signal of the vertical driver, Vertical drive clock to obtain the speed specified in the row unit And a means for supplying to the vertical driver, and a path provided to supply the input video signal to the horizontal driver, the output signal from the horizontal receiver and the level of the input video signal are compared, and the input video signal is compared. When the level difference is equal to or more than a predetermined value, a means for adding or subtracting the voltage of the difference to the input signal to supply it to the horizontal driver bar is provided in order to speed up the response of the liquid crystal cell. Television signal display device. 11. A plurality of liquid crystal cells in which liquid crystal display elements are arranged in a matrix, and a plurality of horizontal drivers for driving the elements of the respective liquid crystal cells in a horizontal arrangement direction by sampling an input video signal in the horizontal direction. A plurality of vertical drivers for driving the elements of the plurality of liquid crystal cells in a row direction so as to sample the input video signal in a horizontal line unit; and a plurality of horizontal drivers of the plurality of horizontal drivers. A means for obtaining a horizontal drive clock for each liquid crystal cell for sequentially obtaining a start timing signal and for obtaining the sampling speed in an element unit, and sequentially obtaining a vertical drive start timing signal for each of the plurality of vertical drivers, and for each row unit. Vertical drive clock for each driver to get the specified speed And a means provided in a path for supplying the input video signal to the horizontal driver, dividing the horizontal period of the input video signal and supplying the divided horizontal drivers to different horizontal drivers in the order of division. Television signal display device.