JP2000047623A - Crt display image horizontal distortion correcting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a horizontal distortion correcting device, which corrects the horizontal distortion of an image by controlling the phase of a horizontal deflecting current by applying a residual phase, for a CRT display device. SOLUTION: The horizontal distortion correcting device HDCp which corrects the horizontal distortion of an image due to the assembly precision of the CRT display device displaying the image by scanning a video signal Si according to the horizontal synchronizing signal included in the video signal Si includes a PLL 14 which supplies the horizontal deflecting current Ihd to a video signal controller 12 displaying the image on the CRT 24 by deflecting an electron beam. A distortion correcting waveform generator 100 applies the PLL 14 with a waveform signal Sw which is scanned by a user and has a desired waveform to give a residual phase to the horizontal deflecting current Ihd, thereby controlling its phase. Consequently, the CRT display device displays a distortion-free image.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for correcting horizontal distortion of an image displayed on a CRT display device.
More specifically, the present invention relates to a PLL circuit using a residual phase and a drive circuit of a CRT display device using the same.

[0002]

2. Description of the Related Art In recent years, CRT display devices for computers have generally become compatible with various scanning frequencies. However, an image displayed on a CRT display device is inevitably distorted due to an assembly accuracy error at the time of manufacturing the CRT display device. Among these distortions, there is a horizontal distortion in which an image is deformed in the horizontal direction. The horizontal distortion includes a center deviation distortion, a parallelogram distortion, an arc distortion, and the like. These horizontal distortions shift the phase of the image in the horizontal direction, and require horizontal phase correction to correctly display the image. Hereinafter, each of these horizontal distortions will be briefly described with reference to FIGS. 31, 32, 33, and 34.

First, FIG. 31 shows a screen including no distortion,
The relationship with various signals constituting a video signal for generating the screen is shown. In the figure, Hysnc is a horizontal synchronizing signal that generates a pulse at a predetermined cycle. Ihd indicates a horizontal deflection current. Sv indicates an image signal for one frame. The horizontal deflection current Ihd is synchronized with the horizontal synchronization signal Hsync, and the horizontal synchronization signal Hsync and the image signal Sv have a fixed time relationship.

[0004] In the example shown in FIG.
The process after 7 is a repetition of the process from time t1 to time t7. Therefore, from time t1 to time t
The relationship between the video signal and the screen between 7 will be briefly described. The H pulse Hp is a pulse signal that rises at time t1, falls at time t3, and rises at time t7, as shown in FIG. The horizontal deflection current Ihd becomes maximum at time t2 in the pulse of the H pulse Hp and becomes minimum at time t4. Between time t4 and time t8, the horizontal deflection current Ihd increases linearly and reaches a maximum value at time t8.

The image signal Sv is a horizontal synchronizing signal Hsync.
A predetermined period (R) from the fall of the pulse (time t3)
At time t4 after iL), drawing of a raster image for one line is started in response to the falling edge of the horizontal deflection current Ihd. Then, the raster drawing ends at time t6, which is a predetermined period (RiR) before time t8.
The interval between the raster screen Fr and the image screen Fv corresponding to the period RiL from time t4 to time t5 is referred to as a left retrace period RiL. Similarly, an interval between the raster screen Fr and the image screen Fv corresponding to the period RiR from the time t6 to the time t8 is referred to as a right retrace period RiR.

[0006] The screen configuration of the image displayed by the CRT display device upon receiving these video signals is as follows. The image is displayed concentrically on the display frame Fc of the cabinet of the CRT display device, so that the user can recognize the image without a sense of incongruity. Therefore, the image displayed on the CRT display device includes two types of a raster screen Fr and an image screen Fv. The raster screen Fr is a screen displayed as a set of scanning lines called a raster, and is scanned in a range larger than the cabinet display frame Fc.

That is, the image screen Fv is the raster screen Fr
Can be viewed as projected on the cabinet display frame Fc. The image screen Fv represents an actual video. Assuming that the scanning line is scanned from left to right on the drawing, the left retrace interval RiL from the left end of the raster screen Fr to the left end of the image screen Fv is usually constant. The fact that the left retrace interval RiL is constant means that the horizontal deflection current Ihd and the horizontal synchronization signal Hs
are synchronized, and as a result, the horizontal synchronization signal Hsync is output.
This is because the temporal relationship between the video signal Sv and the video signal Sv is constant.
Similarly, the right flyback period RiR is also constant.

FIG. 32 shows a state in which the image is centered and distorted. Raster screen Fr for cabinet display frame Fc
And the image screen Fv is shifted in the horizontal direction, and as a result, the image screen Fv is shifted from the center of the cabinet display frame Fc.

FIG. 33 shows a parallelogram distortion state of an image. The raster screen Fr is distorted into a parallelogram with respect to the cabinet display frame Fc, and as a result, the image screen Fv is also distorted on the parallelogram.

FIG. 34 shows what is called bow distortion. Since the scanning start position (the left end in the figure) of the raster screen Fr is bowed, the image screen Fv also appears to be bowed. These horizontal distortions shown in FIG. 32, FIG. 33, and FIG. 34 are not always generated independently but may be generated in combination.

Such distortion in the horizontal direction does not cause the relationship between the horizontal deflection current Ihd, the image signal Sv, and the horizontal synchronizing signal Hsync which is a start signal of the image signal Sv to be shifted. This is caused by the mechanical mounting accuracy of the deflection control unit including the coil, the unevenness of the generated magnetic field, and the like. Therefore, today, a CRT display device is equipped with a distortion correction circuit capable of adjusting a correction amount for image distortion in accordance with a scanning frequency in order to reduce distortion of a displayed image and maintain image quality. .

With reference to FIGS. 35 and 36, an example of image distortion caused by the mechanical mounting accuracy of the deflection control unit will be described. First, FIG. 35 shows a state in which an electron beam is scanned in a vertical direction by a deflection control device normally attached to a CRT display device. Note that, for the sake of visibility, parts unnecessary for description such as a glass tube of a CRT are not shown in FIG. In this example, the deflection control unit includes the deflection magnetic pole 6 and a drive circuit (not shown).

The electron beam Eb emitted from the electron gun 5 collides with the phosphor screen of the CRT forming the screen, is deflected and scanned in the vertical direction by the deflecting magnetic pole 6, and is observed as a bright line Lb on the screen. This bright line Lb is transmitted by the deflection controller to the CRT.
If it is accurately attached to the CRT display device, it becomes perpendicular to the horizontal line Lh on the display screen of the CRT.

On the other hand, FIG. 36 shows a case where the deflection control unit is attached to a CRT display device with a slight inclination with respect to the CRT. In this example, as compared with the case where the deflection magnetic pole 6 is shown in FIG.
(Not shown). As a result, even if the electron beam Eb is deflected and scanned in the vertical direction by the deflection magnetic pole 6, CR
The bright line Lb on the display screen of T is not vertical but oblique to the horizontal line Lh. This is the main cause of the parallelogram distortion.

That is, the parallelogram distortion of the screen displayed on the CRT is caused by various video signals Hsync and Hsync shown in FIG.
It does not occur due to distortion of the electric signals Ihd and Sv, but occurs due to an assembly error or the like at the time of assembling the CRT. Similarly, the center deviation distortion is caused by an assembly error of the deflection control unit. The bow distortion is mainly caused by the distortion of the deflection magnetic field or the deflection electric field. However, the bow distortion is caused not by the electric signal controlling the deflection magnetic field or the deflection electric field but by the assembly accuracy of the deflection control unit. The point is similar to the parallelogram distortion.

Conventionally, to correct these horizontal distortions,
A method using a centering circuit is exclusively used. FIG. 37 shows a conventional CRT display device incorporating a horizontal distortion correction device using a centering circuit. The CRT display device Ccrt is roughly divided into a signal separation controller 11, a CRT 24, a horizontal distortion correction device HD.
C, centering adjuster 180, and controller 22.

The signal separation controller 11 converts an input signal Si from a signal source (not shown) such as an external computer into a video signal Svi, a V pulse Vp for vertical deflection, and an H pulse Hp for horizontal deflection. Is output separately. The H pulse Hp is a signal synchronized with a horizontal synchronization signal Hsync which is a start signal of the video signal Svi.

The CRT 24 includes a video signal controller 12 and a vertical deflection controller 13 which are connected to the signal separation controller 11 and receive the video signal Svi and the V pulse Vp, respectively. The video signal controller 12 converts the video signal Svi into the electron beam E
is converted to b and emitted on the CRT 24. The vertical deflection controller 13 controls the electron beam Eb based on the V pulse Vp.
Of the vertical deflection of. Note that any method of magnetic field deflection and electric field deflection may be used for vertical deflection.

The horizontal distortion corrector HDC is connected to the signal separation controller 11, and controls the horizontal deflection of the electron beam Eb based on the H pulse Hp input from the signal separation controller 11. As with the vertical deflection controller 13, any control method of the magnetic field and the electric field can be adopted. As will be described later in detail, the present invention relates to a horizontal distortion correction device that corrects horizontal distortion of an image caused by assembly accuracy of a CRT display device by correcting a video signal to correct horizontal distortion. Therefore, also in the prior art, the detailed description of the video signal controller 12 and the vertical deflection controller 13 is omitted, and only the horizontal distortion correction device HDC will be described in detail.

The horizontal distortion correction device HDC has a PLL circuit 1
4, a horizontal deflection power supply 15, coupling coils 16 and 17, a centering circuit 18, a horizontal drive coil 19, a linearity coil 20, and an S-shaped capacitor 21. The PLL circuit 14 will be described later in detail with reference to FIG.

The PLL circuit 14 receives the H pulse Hp as an input and outputs a sawtooth-shaped horizontal deflection current Ihd in synchronization with the input. The horizontal deflection power supply 15 is connected via a coupling coil 16 to
A high DC voltage is supplied to the drive coil 19 arranged downstream therefrom. The horizontal drive coil 19 is connected to the electron gun 5
A magnetic field is applied to the electron beam Eb emitted from the substrate to deflect it in the horizontal direction. Both the linearity coil 20 and the S-shaped capacitor 21 are used for correcting the deflection of the electron beam Eb.

The centering circuit 18 includes a coupling coil 17
, A DC current Ic is superimposed on the horizontal deflection current Ihd output from the PLL circuit 14. As a result, a bias is applied to the horizontal deflection current Ihd, the raster screen Fr moves in the horizontal direction, and the center deviation distortion can be corrected. In this sense, the current Ic is called a horizontal distortion correction current. The horizontal distortion correction current Ic is adjusted by the user operating the centering circuit 18 by the centering adjuster 180. In other words, the user
While looking at the screen displayed on 24, the centering adjuster 180 is operated to adjust the deviation of the image screen Fv.

Next, FIG. 38 shows the relationship between the horizontal deflection current Ihd and the horizontal distortion correction current Ic at the time of the above-described image screen Fv displacement adjustment. The horizontal deflection current Ihd is 0 A (ampere)
And a sawtooth having the same amount of amplitudes h1 and h2 on both the positive and negative sides. The 0A level in the horizontal deflection current Ihd defines the scanning center O (o) of each scanning line constituting the raster screen Fr. The raster screen Fr defined by such normal horizontal deflection current Ihd
Shows a state displayed on a CRT having horizontal distortion as a horizontal distortion raster screen Frh.

As described above, the center Op of the parallelogram distortion raster screen Frh is shifted with respect to the center Oc of the cabinet display frame Fc due to factors at the time of assembling the CRT. In the example shown in the figure, the image screen Fv viewed through the cabinet display frame Fc has a larger portion on the left side than the center Oc of the parallelogram distortion raster screen Frp. That is, the image screen F
“v” appears to be biased in an image shifted rightward with respect to the center Oc of the cabinet frame. That is, as if the horizontal deflection current I
hd transitions to the positive side, or it appears that the positive side amplitude h1 is larger than the negative side amplitude h2. Such an image screen Fv shifted in the horizontal direction is called a horizontal distortion image screen Fvh.
(Not shown).

Therefore, in order to cancel the apparent transition of the horizontal deflection current Ihd, the centering circuit 18 is operated to superimpose the DC current horizontal distortion correction current Ic corresponding to the above-mentioned horizontal deviation amount in the negative direction. I do. This horizontal distortion correction current Ic has a negative amplitude hi in the horizontal deflection current Ihd.
c. Thus, the positive amplitude h1 is reduced by hic to h1 ', and the negative amplitude h2 is similarly reduced by hic to h2'. As a result, both amplitudes h1 'and h
2 ′ becomes | h1 ′ | <| h2 ′ |.

That is, the phase of the horizontal deflection current Ihd is shifted by the amount corresponding to the horizontal distortion correction current Ic in the negative direction, that is, delayed. Such a horizontal deflection current Ih
The amplitude of d becomes asymmetric h1 ′ and h2 ′ around 0A, but the raster screen Frc shifts to the left with respect to the cabinet display frame Fc, and the parallelogram distortion image viewed from the cabinet display frame Fc. The center screen distortion of the screen Fvp is corrected, and the image screen Fv is displayed.

FIG. 39 shows the configuration of the PLL circuit 14.
The PLL circuit 14 includes a phase comparator 29, a low-pass filter (hereinafter, referred to as “LPF”) 30, a voltage-controlled oscillator (hereinafter, referred to as “VCO”) 31, a 1 / N frequency divider 32, a pulse generator 33, and a horizontal output. Circuit 34 is included. Phase comparator 29
Is connected to the signal separation controller 11 of the CRT display device Ccrt, and receives an H pulse Hp. The phase comparator 29 is further connected to a horizontal output circuit 34,
A flyback pulse FBP, which is a signal indicating the start of horizontal deflection scanning every 1H (horizontal synchronization period), is input.

The phase comparator 29 receives the input H pulse H
A phase difference signal Sdp corresponding to the phase difference between p and the flyback pulse FBP is generated. The LPF 30 includes a phase comparator 29
Is converted into a phase difference voltage Vdp, which is a DC voltage, by performing an integration process on the phase difference signal Sdp input from. VCO31
Generates an oscillation signal So having a frequency corresponding to the phase difference signal Sdp input from the LPF 30.

The VCO 31 changes the oscillation frequency FO depending on the input voltage. Generally, as shown in FIG. 40, the VCO 31 has an oscillation maximum input voltage VOmax corresponding to the oscillation maximum frequency FOmax and an oscillation minimum input voltage corresponding to the oscillation minimum frequency. VCO control reference voltage in between (hereinafter “VCSV”)
). Note that the oscillation frequency FO and the oscillation input voltage VO are determined by the design of the VCO 31, the characteristics of the components, and the like.

The oscillation signal So oscillated by the VCO 31 is
Since it has a higher frequency than the desired horizontal deflection current Ihd, the frequency is divided by the 1 / N divider 32 to a desired frequency to generate a divided signal Sd. Note that N is the reciprocal of the ratio between the desired frequency and the frequency of the input oscillation signal So. Based on the frequency-divided signal Sd having the desired frequency, the pulse generator 33 generates a pulse Pd having a desired duty ratio. Based on this pulse Pd,
The horizontal output circuit 34 generates a horizontal deflection current Ihd and supplies it to the horizontal drive coil 19 and the like.

The horizontal output circuit 34 generates a flyback pulse FBP corresponding to the horizontal deflection current Ihd simultaneously with the generation of the horizontal deflection current Ihd. The flyback pulse FBP is fed back to the phase comparator 29, and the processing until the flyback pulse FBP is further generated based on the H pulse Hp input from the signal separation controller 11 is one cycle of horizontal synchronization processing. Call. Then, the next horizontal synchronization processing cycle is performed based on the flyback pulse FBP generated in the horizontal synchronization processing of the current cycle.

FIG. 41 shows that the PLL circuit 14 outputs the H pulse Hp
2 schematically shows a process of generating a horizontal deflection current Ihd synchronized with the horizontal deflection current Ihd. In the figure, Dp indicates the phase difference between the H pulse Hp input to the phase comparator 29 and the flyback pulse FBP corresponding to each of the H pulses Hp. The phase comparator 29 outputs a phase difference signal Sdp corresponding to the phase difference Dp between the H pulse Hp and the flyback pulse FBP.
Is output. The LPF 30 outputs the phase difference signal Sd
p is converted to a phase difference voltage Vdp.

The VCO 31 is controlled by the phase difference voltage Vdp.
Is required to increase the oscillation frequency, and oscillates a higher frequency (short pulse interval) to generate an oscillation signal So. The oscillation signal So is frequency-divided by the 1 / N frequency divider 32 to have a frequency of 1 / N to generate a frequency-divided signal Sd. Based on the frequency-divided signal Sd, the pulse generator 33 generates a horizontal deflection current Ihd having an appropriate duty ratio, and outputs it to the horizontal output circuit 34.

Thus, in the next horizontal synchronization processing cycle, the flyback pulse FBP input to the phase comparator 29 has a slightly shorter wavelength than the flyback pulse FBP input one cycle before. . That is, the phase difference between the flyback pulse FBP and the H pulse Hp is smaller than the phase difference Dp in the previous cycle.

As a result, the phase difference voltage Vdp input to the VCO 31 becomes smaller than in the previous cycle. Therefore, the oscillation frequency FO at which the phase difference voltage Vdp melts so as to increase the VCO 31 is smaller than that in the previous cycle. Thus, finally, the flyback pulse FBP synchronized with the H pulse Hp is output, and the horizontal deflection current Ih synchronized with the H pulse Hp is finally output.
d is obtained.

Next, a method for correcting the parallelogram distortion using the centering circuit 18 will be described. In other words, the horizontal shift amount in the horizontal direction for each horizontal scanning line is increased or decreased by superimposing the horizontal distortion correction current Ic, which is a large DC current, on the centering circuit 18 for each horizontal scan. As a result, the raster screen Fr has a parallelogram shape.

FIG. 42, FIG. 43, FIG. 44, FIG. 45, and FIG. 46 show the relationship between the horizontal deflection current Ihd and the horizontal distortion correction current Ic to make the raster screen Fr a parallelogram.
As described with reference to FIG. 38, the horizontal deflection current Ihd
When the horizontal distortion correction current Ic is superimposed on the raster frame Fr, the position of the raster screen Fr with respect to the cabinet display frame Fc shifts as shown in FIG. The raster screen Fr originally includes a plurality of horizontal scanning lines Lhs1 to LhsN (N
Is a bunch of arbitrary integers determined for each broadcast system.

Therefore, as shown in FIG. 42, horizontal distortion superimposed as Ic1, Ic2, Ic3,... On the horizontal deflection current Ihd output from the PLL circuit 14 shown in FIG. By changing the amount of the correction current Ic, C
When observed on RT, the horizontal scanning line LhsN gradually shifts to the right in the drawing as N increases, and the raster screen Fr is distorted into a parallelogram.

As shown in FIG. 44, the raster image Fr originally distorted into a parallelogram shape due to a factor at the time of assembly is shown in FIG.
When applied to b, a raster screen Fr without distortion can be obtained as shown in FIG. At this time, the output current of the centering circuit 18 becomes a sawtooth wave along the cycle of the V pulse Vp as shown in FIG.

The correction of the bow-shaped distortion is similar in principle to the correction of the parallelogram distortion, and can be corrected by using a parabolic wave instead of the sawtooth used in the correction of the parallelogram distortion.

[0041]

However, the centering circuit is a high voltage and large current circuit for supplying a control current to the horizontal deflection control unit. Since components having high withstand voltage must be used, the circuit becomes large. As a result, the overall size and weight of the device are increased, which leads to an increase in cost. Next, when a plurality of horizontal distortions are occurring at the same time, or when it is desired to combine and use a plurality of correction waves, a circuit is increased in size to control or generate a high-voltage large-current correction signal, Again, this is a factor in increasing the size of the entire device. The present invention has been made to solve the above problems, and has as its object to provide a small horizontal distortion correction device that controls a low-current correction signal.

[0042]

Means for Solving the Problems and Effects of the Invention The first invention is based on a horizontal synchronization signal included in a video signal.
A horizontal distortion correction device that corrects horizontal distortion of an image caused by assembly accuracy of a CRT display device that scans a video signal and displays an image, and deflects an electron beam to display an image on a CRT. The deflector and the deflector
A deflection controller that controls the display position of an image by applying a horizontal pulse synchronized with a horizontal synchronization signal, and a residual phase that gives the residual phase to the deflection controller and shifts the phase of the horizontal pulse in the direction to eliminate horizontal distortion An image is scanned in the horizontal direction without distortion in the horizontal direction.

As described above, in the first aspect of the invention, the horizontal distortion caused by the assembly accuracy of the CRT display device can be corrected with higher accuracy by utilizing the unavoidable residual phase which cannot be removed.

In a second aspect based on the first aspect, the deflection controller is constituted by a PLL, and the residual phase adder is a waveform generator capable of generating a modulation signal having a waveform having a predetermined waveform. The phase of the horizontal pulse is controlled by inputting the modulation signal to the PLL.

As described above, in the second invention, P
By performing distortion correction by the LL circuit, distortion correction in the horizontal direction of an image is realized, and the size of the device can be reduced.

According to a third aspect, in the second aspect, the waveform of the modulation signal is a sawtooth wave, and parallelogram distortion of the image can be corrected.

According to a fourth aspect of the present invention, there is provided a horizontal display which corrects horizontal distortion of an image caused by assembly accuracy of a CRT display device which scans a video signal and displays an image based on a horizontal synchronization signal included in the video signal. A distortion correction method, comprising: a deflection step of deflecting an electron beam to display an image on a CRT; a deflection control step of applying a horizontal pulse synchronized with a horizontal synchronization signal to control a display position of the image; A residual phase adding step of giving a phase and shifting the phase of the horizontal pulse in a direction to cancel the horizontal distortion, wherein an image scanned in the horizontal direction is displayed without distortion in the horizontal direction. Correction method.

[0048]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A horizontal deflection control device according to a first embodiment of the present invention will be described below with reference to FIGS. 1, 2, 3, 4 and 5. FIG. Will be described. FIG. 1 shows a horizontal distortion correction device HDC according to the present embodiment.
2 shows a CRT display device Pcrt incorporating p. The CRT display device Pcrt is roughly divided, like the conventional CRT display device Ccrt shown in FIG. 37, into a signal separation controller 11, a CRT 24, a horizontal distortion correction device HDCp, a controller 22, and a waveform adjuster 100f.
including.

The CRT 24 includes a video signal controller 12 and a vertical deflection controller 13 which are connected to the signal separation controller 11 and obtain the video signal Svi and the V pulse Vp, respectively. The video signal controller 12 converts the video signal Svi into the electron beam E
b and emit it on a CRT. Vertical deflection controller 1
3 controls the vertical deflection of the electron beam Eb based on the V pulse Vp. The vertical deflection may use either magnetic field deflection or electric field deflection.

The horizontal distortion corrector HDCp is connected to the signal separation controller 11, and controls the horizontal deflection of the electron beam Eb based on the H pulse Hp input from the signal separation controller 11. As with the vertical deflection controller 13, any control method of the magnetic field and the electric field can be adopted.

The horizontal distortion correction device HDCp is a PLL circuit 1
4, including a horizontal deflection power supply 15, a coupling coil 16, a horizontal drive coil 19, a linearity coil 20, an S-shaped capacitor 21, a distortion correction waveform generator 100, and a resistor 101. That is, the horizontal distortion corrector HDCp removes the centering circuit 18 and the centering adjuster 180 from the conventional horizontal distortion corrector HDC, while the distortion correction waveform generator 1
00 and a resistor 101 are newly added. The distortion correction waveform generator 100 is connected to a waveform adjuster 100f provided outside.

The PLL circuit 14 receives the H pulse Hp as an input, and outputs a sawtooth-shaped horizontal deflection current Ihd in synchronization with the H pulse Hp. The horizontal deflection power supply 15 is connected via a coupling coil 16 to
A high DC voltage is supplied to the drive coil 19 arranged downstream therefrom. The horizontal drive coil 19 is connected to the electron gun 5
A magnetic field is applied to the electron beam Eb emitted from the substrate to deflect it in the horizontal direction. Both the linearity coil 20 and the S-shaped capacitor 21 are used for correcting the deflection of the electron beam Eb.

As shown in FIG. 39, the PLL circuit 14 includes a phase comparator 29, a low-pass filter 30, a VCO
31, a 1 / N frequency divider 32, a pulse generator 33, and a horizontal output circuit 34. The phase comparator 29 is connected to the signal separation controller 11 of the CRT display device Pcrt,
The pulse Hp is input. The phase comparator 29 is further connected to a horizontal output circuit 34, and receives a flyback pulse FBP, which is a signal indicating the start of horizontal deflection scanning for each horizontal synchronization period.

The phase comparator 29 receives the input H pulse H
A phase difference signal Sdp corresponding to the phase difference between p and the flyback pulse FBP is generated. On the other hand, as shown in FIG. 4, a distortion correction waveform generator 1
00 and the waveform adjuster 100f are connected, a bias voltage is applied, and a residual phase is intentionally given. That is, in the conventional horizontal distortion correction device HDC, the correction of the center deviation distortion performed by the centering circuit 18 is performed at the stage of the oscillation signal So of the PLL circuit 14.

That is, the horizontal deflection current Ihd of a large current is corrected by the oscillation signal So of a small current. As a result, the size of the components can be reduced, and the size and weight of the entire device can be reduced. The correction of the oscillation signal So performed using the resistor 101, the distortion correction waveform generator 100, and the waveform adjuster 100f will be described later. L
The PF 30 performs an integration process on the phase difference signal Sdp input from the phase comparator 29, and performs a phase difference voltage V which is a DC voltage.
Convert to dp. The VCO 31 generates an oscillation signal So having a frequency according to the phase difference signal Sdp input from the LPF 30.

The VCO 31 changes the oscillation frequency FO according to the input voltage. As described with reference to FIG. 36, the oscillation maximum input voltage VOmax corresponding to the oscillation maximum frequency FOmax and the oscillation frequency FOmax corresponding to the oscillation minimum frequency It is designed to operate with a VCO control reference voltage VCSV that is between the minimum input voltage. Note that the oscillation frequency and the oscillation input voltage are determined by the design of the VCO 31, the material of the components, and the like.

The oscillation signal So oscillated by the VCO 31 is
Since it has a higher frequency than the desired horizontal deflection current Ihd, the frequency is divided by the 1 / N divider 32 to a desired frequency to generate a divided signal Sd. Note that N is the reciprocal of the ratio between the desired frequency and the frequency of the input oscillation signal So.

Based on the frequency-divided signal Sd having the desired frequency, the pulse generator 33 generates a pulse Pd having a desired duty ratio. Based on the pulse Pd, the horizontal output circuit 34 generates a horizontal deflection current Ihd and supplies it to the horizontal drive coil 19 and the like. The horizontal output circuit 34 generates the horizontal deflection current Ihd and simultaneously generates the flyback pulse F corresponding to the horizontal deflection current Ihd.
Generate BP.

The flyback pulse FBP is applied to the phase comparator 2
The process until the flyback pulse FBP is generated based on the H pulse Hp fed back from the signal separation controller 11 and fed back to the signal separation controller 11 is referred to as one cycle of horizontal synchronization process. Then, the next horizontal synchronization processing cycle is performed based on the flyback pulse FBP generated in the horizontal synchronization processing of the current cycle.

As described above, the horizontal distortion correction device HDCp according to the present embodiment performs the correction of the center deviation distortion performed by the centering circuit 18 in the conventional horizontal distortion correction device HDC by using the output of the PLL circuit 14. Done in stages,
Rather than applying a correction to a large current called the horizontal deflection current Ihd, a large current is driven by a correction signal, so that the components can be reduced in size, and the entire device can be reduced in size and weight.

The PLL circuit 14 receives the input H pulse Hp
And a phase comparator 29, an LPF 30, a VCO 31, a 1 / N frequency divider 32, a pulse generator 33, and a horizontal output circuit 34, which are the same as the PLL circuit 14 described with reference to FIG. In the present invention, the distortion correction waveform generator 100 is connected to the LPF 30 of the PLL circuit 14 via the resistor 101, and the waveform adjuster 10 adjusts the output of the distortion correction waveform generator 100.
0f is provided. Thereby, the PLL circuit 14
Then, by generating a residual phase and shifting the phase of the video signal, it is possible to correct the center shift distortion of the image screen Fv and the raster screen Fr with respect to the cabinet display frame Fc. The function will be described below.

First, with reference to the timing chart shown in FIG. 2, a description will be given of the phase correction operation of the video signal for realizing the correction of the center shift distortion according to the present invention. Also in the present invention, as in the case of the conventional example, the PLL circuit 1
4 is used to obtain a flyback pulse FBP synchronized with the H pulse Hp (that is, the horizontal deflection current Ihd). However, in the present invention, VC
The phase difference voltage Vdp, which is the input voltage of O31, is biased in advance by the constant voltage Vc.

The PLL circuit 14 tries to synchronize the flyback pulse FBP having a different phase from the H pulse Hp by the synchronization function described above. However, LPF30
, The flyback pulse FBP is stabilized in a state where the phase is shifted from the H pulse Hp. The PLL circuit receives a normally input signal (H pulse H
p) and its own output signal (flyback pulse FBP)
Operates to make the phase difference zero, but in the present embodiment, the bias voltage Vc is
, A phase difference is intentionally generated. This phase difference is called a residual phase because it is a phase difference generated between the input signal and the output signal even though the PLL circuit 14 is in the locked state.

The horizontal deflection current Ihd corresponding to this is LP
The phase of the H pulse Hp and the horizontal deflection current Ihd are shifted by a phase difference ΔP corresponding to the bias voltage Vc set by the constant voltage generation means in F30. As described above, the horizontal synchronization signal Hsync, which is the video signal projection timing, is used.
Are synchronized with the H pulse Hp, so that the horizontal deflection current Ih
The phase between d and the image signal Sv is also shifted.

FIG. 3 shows the relationship between the raster screen Fr and the cabinet display frame Fc during the above-described processing. The raster screen Frc and the image screen Fvc when the center shift distortion occurs are shifted with respect to the cabinet display frame Fc as illustrated. By performing the above-described processing on the video signal in such a state, the image screen Fvc is shifted in the reverse direction by an amount corresponding to the phase difference ΔP generated by the bias voltage Vc. As a result, the raster screen Fr and the image screen Fv can be displayed at appropriate positions with respect to the cabinet display frame Fc.

In this embodiment, the bias voltage Vc from the distortion correction waveform generator 100 to the LPF 30 is used.
The user operates the waveform adjuster 100f while checking the positional relationship between the image screen Fv displayed on the CRT 24 and the cabinet display frame Fc. The configuration of the distortion correction waveform generator 100 will be described later in detail with reference to FIG.

This means that an effect similar to that of the conventional example described with reference to FIG. 37 is obtained. However, in the conventional method of correcting center shift distortion using the centering circuit 18 shown in FIG.
The center shift distortion is corrected by moving r with respect to the cabinet display frame Fc. On the other hand, in the present invention, the relationship between the raster screen Fr and the cabinet display frame Fc is not changed, and the phase difference between the raster screen Fr and the image screen Fv is changed using the PLL circuit 14 that drives the horizontal deflection current Ihd.

That is, by moving the image screen Fv with respect to the fixed raster screen Fr and the cabinet display frame Fc, the center shift distortion is corrected.
This is one of the major features of the horizontal distortion correction according to the present invention.
In addition, the centering circuit 18, which is conventionally required, becomes unnecessary, and cost reduction and downsizing of the entire device can be achieved.

Further, the relationship between the above-mentioned bias voltage Vc and V pulse Vp will be described with reference to FIGS. First, as shown in FIG. 4, the LPF 30 includes a resistor R1 connected in series between the phase comparator 29 and the VCO 31. A point A between the VCO 31 and the resistor R1
Is an output point of the V pulse Vp to the VCO 31. The resistor R2 and the capacitor Cpll are connected in series to the output point A. Note that the capacitor Cpll is grounded. Further, the output point A is connected to the resistor 10 as described above.
1, a distortion correction waveform generator 100 is connected.

Although the input waveform of the VCO 31 has been described to have a constant voltage during the period of the H pulse Hp, an accurate waveform will be described with reference to FIG. In the H cycle period L shown in the figure, the H pulse Hp and the flyback pulse FBP are synchronized. Therefore, the phase difference signal Sdp, which is the output of the phase comparator 29, is a constant value because it is the VCO control reference voltage VCSV. In this state, the distortion correction waveform generator 1
Assume that 00 is lower than the VCO control reference voltage VCSV.

The electric charge accumulated in the capacitor Cpll of the LPF 30 moves toward the low-voltage distortion correction waveform generator 100, and the potential at the output point A of the phase difference voltage Vdp gradually decreases as shown by. . As a result, VCO31
Oscillating frequency decreases, and the flyback pulse F generated by the horizontal output circuit 34 via the 1 / N frequency divider 32
The phase of the BP lags behind the H pulse Hp when viewed at the input point of the phase comparator 29 as shown by. As a result, the phase comparator 29 generates the phase difference signal Sdp having a constant voltage corresponding to the phase difference between the H pulse Hp and the flyback pulse FBP as shown by the arrow, and supplies it to the LPF 30. During this time, the phase difference voltage Vdp, which is the input voltage of the VCO 31, increases as shown by.

By repeating this, the distortion correction waveform generator 100 is connected to the LPF 30, and the VCO control reference voltage V
When driving the LPF 30 at a voltage lower than the CSV, the phase difference voltage Vdp becomes the VCO as shown in the period Lr.
A sawtooth wave is formed around the control reference voltage VCSV.

The bias voltage Vc shown in FIG. 2 is actually a sawtooth wave as shown in FIG. 5, but in this specification, it is assumed that the bias voltage Vc is a constant potential for convenience. It is apparent from the above that the relationship between the H pulse Hp and the residual phase, which is a feature of the present invention, does not contradict.

As described above, in the present embodiment, the bias is applied by the constant voltage source and the residual phase is left to correct the center deviation distortion. For that, PLL
Is intentionally added to the residual phase to adjust the phase of the raster screen Fr and the phase of the video signal.

(Second Embodiment) Hereinafter, FIGS.
A second embodiment according to the present invention will be described with reference to FIGS. In the present embodiment, a method for correcting parallelogram distortion using the horizontal distortion correction device HDCp according to the above-described first embodiment will be described. In the present embodiment, only the waveform of the output signal Sw from the distortion correction waveform generator 100 applied to the LPF 30 is different from the case of the center shift distortion correction according to the above-described first embodiment.

The timing chart shown in FIG.
The correction of the parallelogram distortion according to the present embodiment will be described with reference to the raster screens shown in FIGS.
The distortion correction waveform generator 100 outputs V
The phase difference voltage Vdp, which is a sawtooth wave that increases stepwise with respect to the VCO control reference voltage VCSV of the CO 31, is generated.
The phase difference voltage Vdp has a period between pulses of the V pulse Vp as one cycle.

This is because the H pulse Hp and the sawtooth wave generated by the distortion correction waveform generator 100 are superimposed on the LPF 30,
This corresponds to an enlarged version of the phase difference voltage Vdp (VCSV) in FIG. The waveform signal Sw, which is a sawtooth wave, is represented as a step wave in the flyback pulse FBP.

The phase of the horizontal deflection current Ihd and the phase of the H pulse Hp are shifted when the input voltage of the VCO 31 is changed, as described in the first embodiment. That is, when the input voltage (phase difference voltage Vdp) of the VCO 31 changes like the phase difference voltage Vdp (VCSV), the flyback pulse FBP is shifted in phase from the H pulse Hp. That is, it means that a phase shift occurs in the relationship between the horizontal deflection current Ihd and the H pulse Hp. The H pulse Hp and the horizontal deflection current Ihd at the bottom of FIG. 3 are simultaneously displayed to clarify the relationship therebetween.

Next, referring to FIGS. 7, 8, and 9, horizontal scanning lines Lhs1 to LhsN in the above-described processing will be described.
The relationship between the horizontal deflection current Ihd and the horizontal deflection current Ihd will be described. Looking at the relationship between the horizontal scanning lines Lhs1 to LhsN and the horizontal synchronization signal Hsync defining the start point of the video, as shown in FIG. 7, the point of the horizontal synchronization signal Hsync is shifted with respect to the horizontal scanning lines Lhs1 to LhsN. Go. When such a video signal is projected on a CRT display device having a parallelogram distortion as shown in FIG. 8, the result is as shown in FIG.
In other words, the horizontal synchronization signal Hsync for each scanning line is vertical from the top to the bottom of the raster screen Frpc, and the parallelogram distortion is corrected for the cabinet display frame Fc (not shown).

As described above, in the present embodiment, the waveform signal Sw which is a sawtooth wave is generated by the distortion correction waveform generator 100, and the waveform signal Sw is input to the PLL circuit 14,
The phase difference voltage Vdp output from F30 is modulated to correct parallelogram distortion. Note that the distortion correction waveform generator 100
The magnitude of the amplitude of the sawtooth wave (Sw) generated by
While checking the displacement of the screen on the RT display device,
The adjustment is performed by operating the waveform adjuster 100f. In the present embodiment, the parallelogram distortion is corrected based on the upper end of the screen. In this case, the base point of the correction can be set to a desired position by distributing the bias to each of the positive side and the negative side of the VCO control reference voltage VCSV.
In this case, the “reference” refers to a point where the H pulse Hp and the flyback pulse FBP do not shift when the horizontal distortion is corrected according to the present embodiment.

(Third Embodiment) FIGS. 10 and 1
1, FIG. 12, FIG. 13, FIG. 14, FIG. 15, FIG. 16, FIG.
A third embodiment according to the present invention will be described with reference to FIG. 7, FIG. 18 and FIG. In the second embodiment described above, the parallelogram distortion is corrected by superimposing the sawtooth waveform signal Sw on the LPF 30 of the PLL circuit 14. Incidentally, the relationship of the residual phase with respect to the VCO 31 input of the PLL circuit 14 is often in the state shown in FIG.

In FIG. 10, there is a portion (RC) where the manner of occurrence of the residual distortion is not linear near the VCO control reference voltage VCSV of the VCO 31. This is because the output characteristic with respect to the input phase difference of the phase comparator 29 in the PLL circuit is:
This is because the characteristics are as shown in FIG. That is, as described with reference to FIG.
Although the phase of the input H pulse Hp and the phase of the flyback pulse FBP do not match, the phase comparator 29
Output is zero. This means that the PLL circuit 14 is in a locked state even though the output signal FBP is not completely synchronized with the input signal H pulse Hp.

Such a nonlinear characteristic section is provided by the PLL circuit 14.
It depends on the difference between the manufacturers and the design frequency of the used frequency, the used parts, and the like, and may be small enough to be ignored or large enough not to be ignored. In particular, when a cheap component or IC is used to reduce the cost, the size may become so large that it cannot be ignored. In the second embodiment as well, the correction of the uniform parallelogram from the top to the bottom of the raster is lost. There are cases.

The operation of each signal at this time will be described with reference to the timing chart shown in FIG. As shown in the figure, a distortion correction waveform generator 10
0 gives a correction wave (waveform signal Sw). Then H
Although the phase of the pulse Hp and the phase of FBP are shifted, in a portion corresponding to FBP2 from FBP1, the phase comparator 29 cannot determine that the phase of the input H pulse Hp and the phase of FBP are shifted, and is the output of the phase comparator. The phase difference signal Sdp remains at zero. However, when the phase difference exceeds a certain value, the phase comparator 29 determines that there is a phase difference and outputs a signal Sc1 for correction. As a result, the input voltage to the VCO 31 changes to VCV1, and as a result, the phase of the FBP does not change smoothly with respect to the H pulse Hp.

As shown in FIG. 13, the horizontal scanning line Lhs1
Looking at the relationship between LhsN and the horizontal synchronizing signal Hsync which is the start position of the image signal Sv, the start position of the image signal Sv should originally be from the upper part of the raster screen Fr to the lower part of the raster screen Fr as shown in FIG. Toward the raster screen F
The portion that should be inclined and linearly inclined with respect to the horizontal of r changes in a non-smooth step shape.

The present embodiment can effectively correct horizontal distortion even in such a case. The configuration of the CRT display device in the present embodiment is exactly the same as in the above-described second embodiment. However, the distortion correction waveform generator 100
Are different from each other in the waveform of the waveform signal Sw.

Referring to FIG. 14, the waveform of waveform signal Sw in the present embodiment will be described. In the present embodiment, a correction waveform (waveform signal S) in which the constant voltage according to the first embodiment and the sawtooth waveform according to the second embodiment are superimposed.
w) is generated by the distortion correction waveform generator 100. The effect of the constant voltage is the same as that in the first embodiment, and a constant phase shift occurs between the H pulse Hp and the horizontal deflection current Ihd.

FIG. 15 shows the horizontal scanning lines Lhs1 to Lhs1 at this time.
The relationship between LhsN and the horizontal synchronization signal Hsync is shown. The effect of the sawtooth wave (waveform signal Sw) is the same as in the second embodiment, and the image screen Fv has a phase shift for each horizontal scanning line with respect to the raster screen Fr. By combining these, the parallelogram distortion can be corrected as shown in FIG.

That is, when a sawtooth wave (waveform signal Sw) superimposed on a constant bias component (Vc) as shown in FIG. 14 is input to the VCO 31 as a correction wave, the H pulse Hp is always changed by the bias voltage Vc. FBPs have different phases. Therefore, the phase comparator 29 always outputs according to the phase difference. It should be noted that at the bottom of FIG.
The horizontal deflection current Ihd output with respect to p and the FBP generated by the horizontal deflection current Ihd are superimposed.

Referring to FIG. 10 showing the relationship between the VCO 31 and the residual phase, the presence of a constant voltage serving as a bias causes the PLL circuit 14 to deviate from the vicinity of the VCSV in the region RA or RB. To work. This is the region R without linearity near the VCSV.
Without using C, the parallelogram distortion is corrected using a portion where the relationship between the input voltage (Vdp) of the VCO 31 and the residual phase is linear, that is, the region RA or the region RB. By doing so, uniform parallelogram distortion can be corrected even in a non-linear region where the phase difference between the H pulse Hp and the FBP cannot be detected as described with reference to FIG.

Although the sawtooth wave according to the present embodiment is shown in the area RA shown in FIG. 10 below the VCSV, the same effect can be obtained in the area RB above the VCSV. . Further, also in the second embodiment and the present embodiment, bowing distortion can be corrected by using a correction wave (waveform signal Sw) as a parabolic wave.

Hereinafter, a method of correcting bow distortion in the present embodiment will be described with reference to FIGS. 17, 18 and 19. FIG. Below the VCO control reference voltage VCSV, a parabolic wave correction wave Scp is shown. Such a correction wave Scp is V
The pulse Vp has a cycle. At this time, the scanning lines Lhs1 to LhsN and the horizontal synchronizing signal Hs
FIG. 18 shows the relationship of the sync. Such a video signal is displayed on a raster screen Fr distorted as shown in FIG.
By applying to a, an image is obtained on a screen without distortion.

As described above, in this embodiment, L
A bias is applied to the PF 30 and the linear portions of the regions RA and RB of the phase comparator 29 are used. In addition,
In this case, a horizontal shift occurs at the same time. The phase of the H pulse Hp can be adjusted independently.

(Fourth Embodiment) FIGS. 20 and 2
A fourth embodiment of the present invention will be described with reference to FIGS. 1, 22, 23, 24, and 25. In the present invention, the horizontal distortion correction device HDCp can correct horizontal distortion, as described in the second and third embodiments. However, as the correction amount is increased, as shown in FIG.
May be distorted at the upper end.

That is, when a signal corrected for parallelogram distortion is displayed on a CRT having no parallelogram distortion, the screen is distorted into a parallelogram in the direction opposite to the distortion. Note that in the case described in the present embodiment, the synchronization of the PLL circuit 14 cannot follow the timing of the horizontal scanning, and the image screen F
This is the case where the upper end of v is distorted. This is mainly because the VCO 31 has a time delay to output a predetermined frequency with respect to the input voltage Vdp.
The time delay depends on the control sensitivity of the VCO 31, the loop gain of the PLL circuit 14, the quality of components and the like, and the input voltage.

This state will be described with reference to FIGS. 21, 22, 23, and 24. In FIG. 21, VC
This shows that the correction waveform (waveform signal Sw) of the sawtooth wave is superimposed on the bias voltage Vc with respect to the O control reference voltage VCSV. 22 and 23 show the H pulse Hp and the flyback pulse FBP, respectively. As shown in FIG. 22, on the upper side of the image screen Fv, the flyback pulse FBP is offset from the H pulse Hp by the amount of the correction signal Sc1 corresponding to the bias with respect to the VCSV. on the other hand,
On the lower side of the image screen Fv, as shown in FIG. 23, the flyback pulse FBP includes the bias voltage Vc and the correction signal Sc.
H pulse Hp deviates from H pulse Hp by 2.

FIG. 24 shows the relationship between the raster screen Fr and the horizontal synchronization signal Hsync in the above case. The deviation of the flyback pulse FBP from the H pulse Hp must return to the phase of the bias voltage Vc during a short period of the sawtooth period (corresponding to the vertical blanking period in the raster screen Fr). At this time, the PLL circuit 14 tries to reduce the phase difference between the H pulse Hp and the FBP every time the H pulse Hp. Therefore, when the sawtooth feedback period ends due to the phase that has to return and the response speed of the PLL circuit 14 with respect to the number of H pulses Hp input so far, the phase difference between the flyback pulse FBP and the H pulse Hp Is determined.

The state shown in FIG. 20 is a sawtooth wave (waveform signal S
This occurs because the flyback pulse FBP does not return even after the feedback period of w) ends. Therefore, in this case, if the correction wave (waveform signal Sw) is a simple sawtooth wave, the distortion cannot be corrected. Therefore, another new means is required as a correction wave. The present embodiment provides a correction wave in such a case.

Referring to FIG. 25, the shape of the correction wave (waveform signal Sw) used in this embodiment will be described.
In the present embodiment, the sawtooth wave (waveform signal Sw) used in the above-described second and third embodiments includes:
An additional waveform for correcting the upper end of the raster screen Fr is further superimposed. This additional waveform is intended to compensate for the delay by changing the phase transiently when the FBP does not return as described above.

As shown in FIG. 25, the correction waveform of the sawtooth wave (waveform signal Sw) to which the additional waveform is added is V
It is added to the vertical deflection period defined by the pulse Vp. A raster screen Fr when this correction wave is used for an ideal PLL circuit 14 that can follow any correction wave
FIG. 26 shows the state of the image screen Fv. Although the phase shift at the upper end of the screen is large, the phase shift is input to a horizontal deflection control circuit HDCp having a PLL circuit 14 having characteristics as shown in FIG. As described with reference to FIG. 9, uniform parallelogram distortion can be corrected.

The present embodiment can be applied only to the case of the parallelogram distortion among the horizontal distortions, and is not used for the center shift distortion and the bow distortion. This is because these distortions do not need to converge during the vertical blanking period because the phases of the scanning line and the horizontal synchronization signal Hsync at the upper and lower parts of the screen are the same.

(Fifth Embodiment) FIGS. 27 and 2
A fifth embodiment of the present invention will be described with reference to FIG. As described above with respect to the fourth embodiment, in order to correct the parallelogram distortion, the PLL circuit 1
When a sawtooth wave (waveform signal Sw) is superimposed on the VCO 31 of No. 4
The phase must be returned during the vertical retrace period from the lower part of the raster screen Fr surface to the upper part of the raster screen Fr. At this time, since the PLL circuit 14 corrects the phase difference for each H pulse Hp, the number of H pulses Hp during the vertical flyback period is one factor for phase convergence.

Accordingly, the magnitude of the angle SE superimposed on the correction wave (waveform signal Sw) changes depending on the number of lines of the input image signal. That is, the phase difference between the H pulse Hp and the flyback pulse FBP at the upper and lower portions of the screen described above is more likely to converge during the vertical blanking period as the number of lines of the input image increases. That is, when the number of lines of the input image is large, the amplitude of the additional waveform may be small.
In view of this point, in the present embodiment, the amplitude of the corner added to the correction wave is changed according to the number of lines of the input image.

Referring to FIG. 27, a CRT display device incorporating the horizontal deflection controller according to the present embodiment will be described. CRT display device PcrtR
Corresponds to the CRT display device Pcrt shown in FIG.
A vertical / horizontal frequency detector 113 is newly provided, and the horizontal distortion corrector HDCp is provided with a horizontal distortion corrector HDCp.
r has been replaced. The vertical / horizontal frequency detector 113 is connected to an external video signal source, detects the horizontal frequency fH and the vertical frequency fV from the input signal Si, and outputs them to the waveform generator 100 of the horizontal distortion corrector HDCpR.

As shown in FIG. 28, the waveform generator 100 includes a controller 110, a storage unit 111, and a waveform generator 112. The controller 110 is connected to the vertical / horizontal frequency detector 113, and based on the input horizontal frequency fH and vertical frequency fV, the number of lines (fH / f).
V) is calculated. Then, the waveform generator 112 generates a correction wave based on the relationship between the number of horizontal lines and the amplitude of the additional waveform previously recorded in the storage unit 111 and the correction amount input by the waveform adjuster 100f by the user. Let PL
Output to the L circuit 14.

FIG. 29 shows an example of the relationship between the number of horizontal lines to be recorded in the storage device 111 and the amplitude of the additional signal added to the sawtooth wave (waveform signal Sw). The actual numerical value is appropriately determined in consideration of the characteristics of the PLL circuit 14 used and the response of other circuits. Note that, in the example of FIG.
For two points, 525 lines, 850 lines, 1480 lines, and 2,000 lines, specifically, the amplitude of the additional signal that does not distort the upper part of the screen is obtained.
These relationships are decided by linear interpolation.

(Sixth Embodiment) Hereinafter, a sixth embodiment of the present invention will be described with reference to FIG. First, the configuration of the waveform generator 100 will be described in detail with reference to FIG. Distortion correction waveform generator 100
Is a controller 110, a storage unit 111, and a waveform generator 1
It consists of 12. The waveform generator 112 includes the constant voltage generator 11
5, a sawtooth wave generator 116, a parabolic wave generator 117, and an additional waveform generator 118. The controller 110 receives an input about the type and magnitude of the correction wave (waveform signal Sw) from the waveform adjuster 100f.

The horizontal frequency fH and the vertical frequency fV are received from the vertical / horizontal frequency detector 113 as inputs. The number of lines of the input video signal is determined based on the horizontal frequency fH and the vertical frequency fV, and the constant voltage generator 115, the sawtooth generator 116, the parabolic generator 117, and the additional waveform are obtained from the input correction amount. The amplitude information and the period information are sent to the generator 118.

The constant voltage generator 115 receives a signal from the controller 110 and generates a DC voltage. The constant voltage generator 115 does not receive the periodic signal from the controller 110. This is because it is unnecessary because it is a direct current. The sawtooth generator 116 generates a sawtooth according to the amplitude and the periodic signal. The parabolic wave generator 117 generates a parabolic wave according to the same amplitude and periodic signal. The additional waveform generator 118 generates an additional waveform according to the same amplitude and periodic signal. Here, the amplitude of the additional waveform generator 118 is not obtained from the input correction amount, but based on the number of lines obtained from the horizontal frequency fH and the vertical frequency fV and the information stored in the storage unit 111. For example, FIG.
This is the amplitude obtained from the relationship shown in FIG.

The constant voltage generator 115, the sawtooth wave generator 116,
The parabolic wave generator 117 and the additional waveform generator 118 are respectively connected in series, and the final output is the sum of the outputs of the respective generators.

Referring to the flowchart shown in FIG.
The operation of the distortion correction waveform generator 100 will be described.

First, in step S1, after receiving an external input instruction, the process proceeds to the next step S2.

In step S2, the number of lines is obtained based on the horizontal frequency fH and the vertical frequency fV.
Then, the process proceeds to the next step S3.

In step S3, it is determined whether or not the external input received in step S1 includes an instruction for correcting center shift distortion. If there is correction of the center deviation distortion, it is determined as Yes, and the process proceeds to step S4.

In step S4, the DC voltage is generated by the constant voltage generator 115 for the external input.
Then, the process proceeds to step S5.

On the other hand, if No is determined in step S3, the process proceeds to the next step S5.

In step S5, it is determined whether or not there is an instruction for correcting parallelogram distortion as an external instruction. Yes if there is an instruction including correction of parallelogram distortion
Is determined, and the process proceeds to step S6.

In step S6, sawtooth wave generator 116
Thereby, a sawtooth wave is generated with an amplitude and a period corresponding to the input. Then, the process proceeds to the next step S7.

On the other hand, if No is determined in step S5, the process proceeds to step S7.

In step S7, it is determined whether or not an external instruction includes an instruction for correcting bow distortion. If there is an instruction to correct bow distortion, it is determined as Yes, and the process proceeds to step S8.

In step S8, the parabolic wave generator 117 generates a parabolic wave with an amplitude corresponding to the input. Then, the process proceeds to the next step S9.

In step S9, it is determined whether or not the output has a parallelogram distortion correction. If there is an instruction to correct the parallelogram distortion, the determination is Yes, and the process proceeds to step S10.

In step S10, an additional waveform is generated by the additional waveform generator 118 corresponding to the number of input lines. Then, the process proceeds to step S11.

On the other hand, if No is determined in the step S9, the process proceeds to the next step S11.

In step S11, if the distortion is other than the parallelogram distortion, H is applied from the upper part to the lower part of the screen.
Since the pulse Hp and the FBP are always at the same phase difference, there is no need to consider the problem of convergence of the phase correction in the PLL circuit 14, and it is not necessary to generate an additional waveform.

In the case where the correction of the parallelogram distortion is included, it is necessary to superimpose an additional waveform for converging the phase correction on the upper part of the screen, and fH and fV input to the control unit are required.
The number of lines is obtained from the signal of the above, and an additional waveform corresponding to the number is calculated by interpolating the data stored in advance in the storage unit 111,
Generate additional waveforms. Such a distortion correction waveform generator 1
As a result, the horizontal deflection control devices according to the first to fifth embodiments can be realized.

As described in the above description of the configuration, these waveforms can be generated independently of each other. Further, the respective waveforms may be simultaneously multiplexed. Although the first embodiment to the fifth embodiment have been described assuming that the H pulse Hp is synchronized with the horizontal synchronization signal Hsync, the phases of the horizontal synchronization signal Hsync and the H pulse Hp are determined in advance by another method. In other words, the image can be adjusted so that the image is at the center of the raster when a constant voltage is generated by the waveform generator of the present invention. For example, such a case is performed when the H pulse Hp is created from the video signal input by the signal separation controller 11 shown in FIG. At this time, the constant voltage generator always outputs a constant voltage corresponding to the bias.

[0128]

[Brief description of the drawings]

FIG. 1 is a block diagram showing a CRT display device incorporating a horizontal distortion correction device according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing an operation of the horizontal distortion control device shown in FIG.

FIG. 3 is an explanatory diagram illustrating a screen in which a center shift occurs.

FIG. 4 is a block diagram showing a detailed structure of an LPF 30 of the horizontal distortion correction device shown in FIG.

FIG. 5 is an explanatory diagram of an input waveform of a VCO.

FIG. 6 is a timing chart illustrating a parallelogram distortion correction operation performed by the horizontal distortion correction device according to the second embodiment of the present invention.

FIG. 7 is an explanatory diagram of an operation of correcting a parallelogram distortion by the horizontal distortion correction device shown in FIG. 6;

FIG. 8 is an explanatory diagram of an operation of correcting a parallelogram distortion by the horizontal distortion correction device shown in FIG. 6;

FIG. 9 is an explanatory diagram of an operation of correcting a parallelogram distortion by the horizontal distortion correction device shown in FIG. 6;

FIG. 10 shows a residual phase and a phase difference voltage Vdp in a VCO.
FIG. 4 is an explanatory diagram of the relationship with.

FIG. 11 is a diagram illustrating output characteristics with respect to a phase difference of a signal input to a phase comparator in a PLL circuit.

FIG. 12 is a timing chart showing an operation of the horizontal distortion correction device according to the third embodiment of the present invention.

13 is an explanatory diagram of a relationship between a raster screen and horizontal scanning lines in the operation shown in FIG.

14 is an explanatory diagram of a waveform of a waveform signal in the horizontal distortion correction device shown in FIG.

15 is an explanatory diagram of a relationship between a raster screen and horizontal scanning lines in the operation shown in FIG.

16 is an explanatory diagram of a relationship between a raster screen and horizontal scanning lines in the operation shown in FIG.

17 is an explanatory diagram of a method of correcting bow distortion by the horizontal distortion correction device shown in FIG.

18 is an explanatory diagram of a relationship between a raster screen and horizontal scanning lines in the operation shown in FIG.

19 is an explanatory diagram of a relationship between a raster screen and horizontal scanning lines in the operation shown in FIG.

FIG. 20 is an explanatory diagram illustrating an example of horizontal distortion corrected by the horizontal distortion correction device according to the fourth embodiment of the present invention.

FIG. 21 is a diagram showing V for correcting the horizontal distortion shown in FIG. 20;
FIG. 4 is an explanatory diagram showing a bias voltage Vc superimposed on a CO control reference voltage.

FIG. 22 is a diagram illustrating an example of the correction of the horizontal distortion shown in FIG.
FIG. 4 is an explanatory diagram showing a relationship between a pulse and a flyback pulse FBP.

FIG. 23 is a diagram illustrating an example of the correction of the horizontal distortion shown in FIG.
FIG. 4 is an explanatory diagram showing a relationship between a pulse and a flyback pulse FBP.

24 is an explanatory diagram illustrating a relationship between a raster screen Fr and a horizontal synchronization signal Hsync when correcting horizontal distortion illustrated in FIG. 20;

FIG. 25 is an explanatory diagram illustrating a shape of a correction wave used in the third embodiment of the present invention.

26 is an explanatory diagram of a state of a raster screen and an image screen when the correction wave illustrated in FIG. 25 is used for an ideal PLL circuit that can follow any correction wave.

FIG. 27 is a block diagram showing a CRT display device incorporating a horizontal distortion correction device according to a fifth embodiment of the present invention.

FIG. 28 is a block diagram showing a structure of a distortion correction waveform generator used in the horizontal correction device shown in FIG.

29 is an explanatory diagram showing the relationship between the number of horizontal lines recorded in the storage device shown in FIG. 28 and the amplitude of an additional signal added to a sawtooth wave.

30 is a flowchart showing an operation of the horizontal distortion correction device shown in FIG. 27.

FIG. 31 is an explanatory diagram of a relationship between various signals forming a video signal and a screen displayed on a CRT display device.

FIG. 32 is an explanatory diagram illustrating an example of center shift distortion of an image displayed on a CRT display device.

FIG. 33 is an explanatory diagram showing an example of parallelogram distortion of an image displayed on a CRT display device.

FIG. 34 is an explanatory diagram illustrating an example of bow distortion of an image displayed on a CRT display device.

FIG. 35 is an explanatory diagram of a display when an electron beam deflecting device is correctly attached to a CRT display device.

FIG. 36 is an explanatory diagram of a display when an electron beam deflecting device is attached to a CRT display device so as to be shifted;

FIG. 37: CRT incorporating a conventional horizontal distortion correction device
FIG. 3 is a block diagram illustrating a structure of a display device.

FIG. 38 is an explanatory diagram of a relationship between a horizontal deflection current and a horizontal distortion correction current at the time of adjusting a displacement of an image screen.

FIG. 39 is a block diagram showing a configuration of a PLL circuit used in the horizontal distortion correction device for images.

FIG. 40 is an explanatory diagram of a relationship between an input voltage and a transmission frequency in a VCO.

FIG. 41 is a timing chart schematically showing a process in which a PLL circuit generates a horizontal deflection current synchronized with an H pulse Hp.

FIG. 42 is an explanatory diagram showing that the position of the raster screen with respect to the cabinet display frame Fc shifts when the horizontal distortion correction current is superimposed on the horizontal deflection current.

FIG. 43 is an explanatory diagram of a relationship between a raster screen distorted into a parallelogram and a horizontal scanning line due to a factor at the time of assembling the CRT display device.

44 is an explanatory diagram of a relationship between a raster screen and horizontal scanning lines at the time of horizontal distortion correction by the horizontal distortion correction shown in FIG. 37.

FIG. 45 is an explanatory diagram of a relationship between a raster screen and horizontal scanning lines at the time of horizontal distortion correction by the horizontal distortion correction shown in FIG. 37.

46 is an explanatory diagram of a relationship between an output current of a centering circuit and a V pulse during the horizontal distortion correction shown in FIG. 37.

[Explanation of symbols]

 Pcrt, Ccrt CRT display device 11 signal separation controller 12 video signal controller 13 vertical deflection controller 14 PLL circuit 15 horizontal deflection power supply 16 coupling coil 17 coupling coil 18 centering circuit 19 horizontal drive coil 20 linearity coil 21 S-shaped capacitor 21 22 Controller 24 CRT 29 Phase comparator 30 LPF 31 VCO 32 1 / N divider 33 Pulse generator 34 Horizontal output circuit 100 Distortion correction waveform generator 100f Waveform adjuster 110 Controller 111 Memory 112 Waveform generator 115 Constant voltage Generator 116 Saw wave generator 117 Parabolic wave generator 118 Additional waveform generator 180 Centering adjuster Si Input signal Svi Video signal Vp V pulse Hp H pulse Ihd Horizontal deflection current Sw Waveform signal FBP Flyback Pulse VCSV VCO control reference voltage Vc bias voltage Fr, Frc raster screen Fc cabinet display frame Fv, Fvc image screen

Claims (4)

[Claims] 1. A horizontal distortion correction device for correcting horizontal distortion of an image caused by assembly accuracy of a CRT display device that scans a video signal and displays an image based on a horizontal synchronization signal included in the video signal. Deflecting means for deflecting an electron beam to display an image on the CRT; and applying a horizontal pulse synchronized with the horizontal synchronization signal to the deflecting means to control a display position of the image. Control means; and residual phase adding means for giving a residual phase to the deflection control means to shift the phase of the horizontal pulse in a direction to cancel the horizontal distortion, wherein the image scanned in the horizontal direction is in the horizontal direction. Horizontal distortion correction device characterized in that the image is displayed without distortion. 2. The apparatus according to claim 1, wherein the deflection control unit includes a PLL, and the residual phase adding unit is a waveform generator that can generate a modulation signal having a waveform having a predetermined waveform. The modulation signal is input to the PLL. By being done
The horizontal distortion correction device according to claim 1, wherein the phase of the horizontal pulse is controlled. 3. The horizontal distortion correction device according to claim 2, wherein the waveform of the modulation signal is a sawtooth wave, and can correct parallelogram distortion of the image. 4. A horizontal distortion correction method for correcting horizontal distortion of an image caused by assembly accuracy of a CRT display device for displaying an image by scanning the video signal based on a horizontal synchronization signal included in the video signal. A deflection step of deflecting the electron beam to display an image on the CRT; a deflection control step of applying a horizontal pulse synchronized with the horizontal synchronization signal to control a display position of the image; Providing a phase and shifting the phase of the horizontal pulse in a direction to eliminate the horizontal distortion, wherein the image scanned in the horizontal direction is displayed without distortion in the horizontal direction. Horizontal distortion correction method.