JPH01238223A - Pll circuit - Google Patents

Abstract

PURPOSE:To shorten lock up time by providing a voltage controlled oscillator, a voltage holding means, a phase generating means and a voltage correcting means. CONSTITUTION:VCO 1 receives a first voltage, generates the oscillating output of a frequency according to the scale thereof and the voltage holding means 2 holds a VCO voltage. The plural phase comparing means 3 compares one of respectively different reference frequency inputs with the VCO output through a frequency dividing means 5 respectively and generates a phase difference signal therebetween. The correcting means 4 receives these phase difference signals and corrects the first voltage in response to the selected on of them. By such a constitution, when the plural phase comparators 3 of different types or characteristics are switched and used, the turbulence of the oscillating output of the VCO can be made minimum, so that the lock up time can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a PLL circuit that generates an oscillation output at a desired frequency from a plurality of reference frequency inputs.

PRIOR ART Conventionally, PLL circuits equipped with a plurality of different types of phase comparators have been used in synchronous coupling circuits in TV signal generators, frequency synthesizers in standard signal generators, and the like. For example, a PLL circuit used in a synchronous coupling circuit uses such different types of phase comparators, such as an analog multiplication type phase comparator and a digital frequency phase comparator, to achieve oscillation at a desired frequency. output,
It is configured such that different signal forms can be generated from the reference frequency input. PLL circuits used in frequency synthesizers also connect such analog phase comparators and digital phase comparators to receive one common reference frequency input, thereby reducing P1. It is constructed so that the lock-up time of the L circuit can be shortened.

FIG. 7 shows a typical circuit configuration of such a PLL circuit. As shown, the analog multiplication includes a phase comparator and a digital frequency phase comparator. Each phase comparator receives the reference input applied to its reference input terminal and the oscillation output of the voltage controlled oscillator VCO through the corresponding divider, and provides an error voltage representing the phase difference between them to the corresponding integrator. It looks like this. The outputs of these integrators are DC voltages input to vCO, and a switching circuit receiving these DC voltage outputs is provided to connect only one selected one to vCO.

For example, this switching circuit is activated when switching the reference frequency input in a synchronous coupling circuit, and in a frequency synthesizer, it selects the integrator output on the digital phase comparator side for a predetermined time at the same time as switching the oscillation frequency, and then selects the integrator output on the digital phase comparator side for a predetermined time, and then It is operated to select the integrator output on the phase comparator side.

In the conventional PLL circuit as described above, when the switching circuit switches the integrator output, a large disturbance occurs in the frequency of the oscillation output of the vCO, which makes it difficult for the loop to reach a stable lock state. The problem is that it takes a long time to lock up.

One of the reasons for this is that the output voltage of the integrator that is disconnected from the vCO and placed outside the loop becomes significantly different from the voltage when the integrator is connected to the VCO. The reason for this is that this out-of-loop integrator still receives the phase error voltage from the corresponding out-of-loop phase comparator, as well as the amplifier included in that phase comparator and this integrator itself. This is because stationary offset voltages (such offset voltages are not a problem because they are corrected when connected in a loop) and these voltages are accumulated and appear at the integrator output. be. As a result, a voltage that is almost unrelated to the lock voltage before switching is applied to vCO, resulting in a longer lock-up time.

In particular, in TV signal generators that use PLL circuits with such problems as synchronous coupling circuits, during the above-mentioned switching, for example, the television receiver receiving the TV signal may notice visually noticeable image fluctuations and color shifts. appear.

Therefore, an object of the present invention is to minimize the change in the input voltage to vCO when switching a plurality of phase comparators, thereby shortening the lock-up time to reach the lock state.
The object of the present invention is to provide an LL circuit.

Means for Solving the Problems In order to achieve the above object, the PLL circuit of the present invention:
Means for holding the VCO voltage input to vCO is shared by a plurality of phase comparators or a plurality of phase-locked loops.

Specifically, the PLL circuit of the present invention generates an oscillation output of a predetermined frequency from a predetermined number of reference frequency inputs.
As shown in the basic configuration diagram of FIG. The voltage holding means 2 and the predetermined number of phase comparison means 3 are provided. Each of the plurality of phase comparison means 3 is connected to receive a different one of the plurality of reference frequency inputs and the oscillation output, and generates a phase difference signal representing a phase difference therebetween.

The PLL circuit of the present invention further includes VCO voltage correction means 4, which comprises the plurality of phase comparison means 3.
is connected to receive a plurality of said phase difference signals from said plurality of phase difference signals, and corrects said VCO voltage in response to a selected one of said plurality of phase difference signals.

Further, the PLL circuit of the present invention may include the predetermined number of the plurality of dividing means 5, each of the dividing means 5 having a frequency division ratio including 1, and the plurality of phase comparing means. The oscillation output frequency-divided by the division ratio is supplied to the corresponding one of 3.

(2) In the P+-L circuit of the present invention configured as described above, the vCO voltage correction means 4 converts the common vCO voltage held in the vco voltage holding means 2 into a plurality of reference frequency inputs based on each of the plurality of reference frequency inputs. of the selected one of the phase difference signals.

Example Examples of the present invention will be described in detail below.

The first embodiment of the PLL circuit according to the present invention shown in FIG. 2 is an example having two reference frequency inputs, first and second.

This PLL circuit is for generating an oscillation output of a predetermined frequency from a first reference frequency input and a second reference frequency input, which may be the same or different.
Corresponding to 2.3.4.5, the voltage controlled oscillator VCOIO
, a vCO voltage holder 20, and a first type phase comparator 3.
0 and a second type phase comparator 32, a vCO voltage corrector 40, and two frequency dividers 50 and 52.

The first type and second type phase comparators 30 and 32 have different phase detection characteristics, and are, for example, an analog multiplication type phase comparator and a digital frequency phase comparator.

The pressure corrector 40 includes a first correction characteristic adjuster 400 connected to receive a phase error voltage representing a phase difference from the first phase comparator 30 and a phase difference voltage from the second phase comparator 32. a second correction characteristic regulator 402 connected to receive a phase error voltage representing
The switching circuit 404 selects one of the two outputs, and a voltage corrector 406 connected to the output of the switching circuit 404.

The voltage corrector 406 has basic correction characteristics common to the two phase-locked loops, and the first and second regulators 400, 402 adjust their basic correction characteristics to Adjust the correction characteristics to suit the loop. In addition, corrector 4
If the basic correction characteristics of 06 are optimal for either loop, the regulator on this loop side may be simply connected.

The above correction characteristics determine the capture range, lock range, and lock-up time of the PLL circuit, and are, for example, the loop gain of each loop, the frequency characteristics of the voltage corrector 40, etc.

In the PLL circuit shown in FIG. 2, a switching circuit 4 is used to switch the reference frequency input or to switch the phase comparator.
04, since the vCO voltage holder 20 is common, the lock voltage immediately before switching is applied to vCO substantially as is.

Next, a second embodiment of the PLL circuit of the present invention will be described with reference to FIG. The PLL circuit of this second embodiment is similar to the PLL circuit shown in FIG. 2, and the same elements are given the same numbers. What differs from the one in FIG. 2 is that the PLL circuit in FIG. 3 includes a VCO pressure compensator 42.

As shown in the figure, this vCO voltage corrector 42 includes a first voltage corrector 420' connected to receive a phase error voltage from the first phase comparator 30, and a phase error voltage from the second phase comparator 32. A second voltage corrector 422 is connected to receive the voltage, and a switching circuit 424 connects a selected one of the outputs of the correctors 420 and 422 to the holder 20. First and second correctors 420.422
each has correction characteristics that are optimal for each looseness involved.

Also in this PLL circuit, the vCO voltage holder 20 is
Common to the two loops. Furthermore, in this example, since each loop is provided with a separate voltage corrector, it is possible to easily provide each loop with an optimal correction characteristic, as in the prior art.

Next, more specific embodiments of the first and second embodiments described above will be described below.

The third embodiment of the present invention shown in FIG. 4 is an application of the PLL circuit shown in FIG. 2 to a synchronous coupling circuit for a TV signal generator, and the signal forms of two reference frequency inputs are different. An example is shown below.

This synchronous coupling circuit receives a composite video signal as a reference for synchronization at an input terminal 60, and outputs an oscillation output at a frequency 4fse, which is four times the subcarrier frequency f sc (3,58MHz), to an output terminal 6. It happens.

In this synchronous coupling circuit, the color burst of the composite video signal is used as the first reference frequency input, and the horizontal synchronization pulse is used as the reference frequency input of fJg2. An input buffer 62, a chrominance amplifier 63 that filters and amplifies only the chrominance signal component, a limiter 64 that limits the output of the amplifier 63 to a constant amplitude, a chrominance detector 66 that detects the chrominance signal, and a synchronizer that extracts the synchronization signal. The separation circuit 70 and the gate pulse generator 68, which generates a gate pulse only during the color burst portion, are used to operate the analog multiplication type phase comparator 302 only for the color burst portion of the composite video signal.

On the other hand, the input cover 7762, the synchronization separation circuit 70, and the H pulse generator 72 that extracts the horizontal synchronization pulse from the output from the circuit 70 are for operating the digital frequency phase comparator 322 with respect to the horizontal synchronization pulse. . These circuits 62 to 72 are conventionally well known, and further explanation will be omitted.

The analog phase comparator 302 has phase detection characteristics that allow it to operate even with intermittent signals, and therefore, in this synchronous coupling circuit, it is used as a phase comparator that uses discontinuous color bursts as a reference frequency input. has been done.

The error voltage outputs of phase comparators 302 and 322 are connected to resistors R1 and R2, respectively, which are connected to regulators 400.
402 respectively) via the analog switch 4042
is connected to the input of

Operational amplifier 4062, resistor R3, and capacitor CI
is the main part of the integrator (operational amplifier 4062 and resistor R
3 corresponds to the voltage corrector 406 in FIG.
1 corresponds to the VCO voltage holder 20). The output of analog switch 4o42 is connected to the inverting input of operational amplifier 4062.

The DC voltage stored in the capacitor c1 is applied to the voltage controlled oscillator VCXO102 (for example, input voltage is 0 to 5 volts) connected to the output of the operational amplifier 54062. In the locked state, vcXO oscillates at a frequency of 4 fsc, and the 174 frequency divider 502 receiving this oscillation output
The frequency-divided signal of sc is supplied to the phase comparator 302, and the 1/
910 frequency divider 522 has a horizontal frequency fh (15,75
kHz) is supplied to the phase comparator 322.

To explain the operation, when using the horizontal sync pulse as the reference frequency input, the analog switch 4042
2 side, this resistor R2 then forms a complete integrator with the following amplifier 4062, resistor R3, and capacitor CI. In this case, resistor R2 is
The loop gain of the lower loop is selected to be an appropriate value. When this loose state reaches the locked state, a DC lock voltage corresponding to the 4fsc oscillation frequency of the vcxo is stored in the capacitor C1.

In this state, when the analog switch 4042 is switched to the R1 side to use the color burst as a reference frequency input, the resistor R1 and 1ikjfc
Amplifier 4062, resistor R3, and capacitor C1 form a complete integrator. However, since the capacitor C1 is shared, it holds the lock voltage as it was before switching, and this lock voltage continues to vcx
o. Therefore, the time for the upper loop to reach the locked state is minimized. Note that the resistor R1 is set to a value such that the loop gain of the upper loop is appropriate.

As described above, the synchronous coupling circuit shown in FIG. 4 can minimize the lock-up time when switching the analog switch, and can ensure oscillation at a stable frequency. This makes it possible to reduce image fluctuations and color shifts that occur during switching to an extent that cannot be visually recognized.

Next, a fourth embodiment of the present invention will be described with reference to FIG. This fourth embodiment is similar to the first embodiment shown in FIG.
The embodiment is more specifically implemented as a frequency synthesizer for a standard signal generator, illustrating an example where the two reference frequency inputs are the same.

As can be seen from the fifth factor, the frequency synthesizer has one reference frequency input terminal 8o and an output terminal 82 that generates an oscillation output at a desired frequency. The circuit configuration of this synthesizer is similar to the right half of the circuit in FIG. 4, except that the same reference frequency input is applied to analog phase comparator 304 and digital phase comparator 324. be. The digital phase comparator 324 has a wide capture range and is therefore used for a short period of time (eg, 10 m5) immediately after frequency switching. - On the other hand, although the capture range of the analog phase comparator 304 is narrow, it is possible to increase the C/N ratio of the output of the VCO 104 in the locked state (high signal purity), so it is used after the above-mentioned short time has ended. .

Furthermore, the difference is that one variable frequency divider 500 is used as a frequency divider, and the variable frequency divider 50
0, the frequency division ratio can be changed in order to switch the oscillation frequency.

The remaining circuit parts, namely R4-R6, analog switch 4
044, operational amplifier 4064, and capacitor C2,
It operates on the same principle as its counterpart in FIG.

In the frequency synthesizer shown in FIG. 5, the capacitor C2 is also used in common. Therefore, for a short time immediately after the frequency change, a lock voltage is established on capacitor C2 by the loop including digital phase comparator 324, and this lock voltage is then applied to analog phase comparator 304.
This will be adjusted more precisely in a loop containing By sharing the capacitors in this way, the lock-up time in at least the latter loop can be further reduced.

Finally, a fifth embodiment of the present invention will be described with reference to FIG. This fifth embodiment is a more specific version of the second embodiment shown in FIG. 3, and only the parts corresponding to the vCO voltage corrector 42 and vCO voltage holder 20 in FIG. It is shown in detail.

The circuit of FIG. 6 can be similarly applied to a synchronous coupling circuit, a frequency synthesizer, etc. In that case, the output of the analog phase comparator and digital phase comparator shown in FIG. 4 or FIG. 5 and the input of vCO All you have to do is replace it with the circuit between .

Operational amplifier 4200 and resistors R7 and R8 constitute a first voltage compensator 420, while operational amplifier 4220 and resistors R9 and RIO constitute a second voltage compensator 422. Capacitor C3 constitutes voltage holder 20. When a loop containing an analog phase comparator is used, a pair of analog switches 4240 and 4242 are switched to side a in conjunction, and at this time amplifier 4200, resistors R7, R
8. Capacitor C3 constitutes an integrator. On the other hand, when a loop containing a digital phase comparator is used, analog switches 4240, 4242 are switched to the b side, whereby amplifier 4220, resistor R9, RIO and capacitor C3 form another integrator.

In the circuit of FIG. 6 as well, since the capacitor C3 is shared, the same operation as in the previous embodiment can be obtained.

Effects According to the PLL circuit of the present invention described in detail above, when a plurality of phase comparators of different types or characteristics are switched and used, disturbances in the oscillation output of the VCO can be minimized, and lock-up time can therefore be shortened. can do.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the basic configuration of a PLL circuit of the present invention. FIG. 2 is a diagram showing a first embodiment of the PLL circuit of the present invention. FIG. 3 is a diagram showing a second embodiment of the PLL circuit of the present invention. FIG. 4 is a circuit diagram showing a more specific third embodiment in which the first embodiment is applied to a synchronous coupling circuit. FIG. 5 is a circuit diagram showing a more specific fourth embodiment in which the first embodiment is applied to a frequency synthesizer. FIG. 6 is a circuit diagram showing a fifth embodiment that is a more specific version of the second embodiment. FIG. 7 is a block diagram showing a typical conventional PLL circuit using multiple phase comparators. [Explanation of symbols] ll 10.102.104: Voltage controlled oscillator, 2:
VCO', tEE holding means, 20: VCO voltage holder, 3: Phase comparison means, 30: First type phase comparator, 32: Second type phase comparator, 302.304: Analog multiplication type phase comparator, 322 ．．
324: Digital frequency phase comparator, 4: VCO voltage correction means, 40.42: VCO voltage correction device, 5: Frequency division means,

Claims (8)

[Claims] (1) In a PLL circuit that generates an oscillation output of a predetermined frequency from a predetermined number of reference frequency inputs, a) is connected to receive a first voltage, and has a frequency corresponding to the magnitude of the first voltage. (b) Voltage holding means for holding the first voltage; (c) The predetermined number of the plurality of phase comparison means, each of the plurality of phase comparison means being connected to the plurality of phase comparison means. connected to receive the oscillation output and a different one of the reference frequency inputs of the plurality of reference frequency inputs, and generating a phase difference signal representing a phase difference therebetween; A PLL circuit comprising: voltage correction means connected to receive the phase difference signal and correcting the first voltage in response to a selected one of the plurality of phase difference signals. (2) In a PLL circuit that generates an oscillation output of a predetermined frequency from a first reference frequency input and a second reference frequency input, a) the PLL circuit is connected to receive a first voltage; a voltage controlled oscillator that generates an oscillation output with a frequency corresponding to the magnitude; b) voltage holding means that holds the first voltage; c) connected to receive the first reference frequency input and the oscillation output. and a first type of phase comparison means for generating a first phase difference signal representing a phase difference therebetween; d) connected to receive the second reference frequency input and the oscillation output; , a second type of phase comparison means for generating a second phase difference signal representing a phase difference therebetween; e) connected to receive the first phase difference signal and the second phase difference signal; A PLL circuit comprising: voltage correction means for correcting the first voltage in response to a selected one of the first and second phase difference signals. (3) In the PLL circuit according to claim 2, the voltage correction means has: (a) an input, and a common correction means for correcting the first voltage; and (b) a common correction means for correcting the first voltage. a first correction characteristic adjusting means connected to receive the phase difference signal and for adjusting the correction characteristic of the correction means by the first phase difference signal; c) connected to receive the second phase difference signal; d) second correction characteristic adjustment means connected to the second phase difference signal for adjusting the correction characteristic of the correction means; d) receiving outputs from the first and second correction characteristic adjustment means; 1. A PLL circuit, comprising: a switching means connected to the common correction means, and connecting a selected one of the outputs of the first and second correction characteristic adjusting means to the input of the common correction means. (4) In the PLL circuit according to claim 2, the voltage correction means is connected to (a) receive the first phase difference signal, and in response to the first phase difference signal, the voltage correction means a first correction means for generating a first correction signal for correcting the first voltage; b) connected to receive the second phase difference signal and responsive to the second phase difference signal; a second correction means for generating a second correction signal for correcting the first voltage; c) connected to receive the first correction signal and the second correction signal; and switching means for connecting the selected one of the second correction signals to the voltage holding means to correct the first voltage. (5) The PLL circuit according to claim 2, further comprising: (a) connected to receive the oscillation output of the voltage controlled oscillator, and at a first frequency division ratio including a frequency division ratio of 1. a first frequency dividing means for supplying the oscillation output to the first phase comparison means; b) a second frequency dividing means connected to receive the oscillation output of the voltage controlled oscillator and having a frequency division ratio of 1; a PLL circuit, comprising: second frequency dividing means for supplying the oscillation output to the second phase comparing means at a ratio of 1 to 3; (6) P according to any one of claims 2 to 5
In the LL circuit, the first type of phase comparison means is an analog multiplication type phase comparator, and the second type of phase comparison means is a digital frequency phase comparator. . (7) A synchronous coupling circuit in a TV signal generator using a PLL circuit according to claim 6, wherein the first reference frequency input is a color burst and the second reference frequency input is a horizontal synchronization pulse. . (8) A frequency synthesizer using a PLL circuit according to claim 6, wherein the first reference frequency input and the second reference frequency input are the same.