JPH0350979A - Clock generating circuit - Google Patents

Abstract

PURPOSE:To improve the picture quality independently of the input of a standard signal or a nonstandard signal by applying phase-lock of a line lock clock to a burst lock clock only when an input video signal is the standard signal. CONSTITUTION:A standard/nonstandard signal detection circuit 106 detects whether a video signal from a terminal 101 is a standard signal satisfying the prescribed standard or a nonstandard signal not meeting the standard. When the video signal is detected to be the standard signal, a switch 108b is controlled with a signal delayed by a delay circuit 113. A switch 108b phase-locks a line lock clock 103 to a burst lock clock 105. When the nonstandard signal is inputted to a line lock clock generating circuit 102, the clock 103 is given and when the standard signal is inputted, the clock 105 or the clock 103 synchronously with the clock 105 is given. Thus, even when any signal is inputted, the picture quality is improved.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a television receiver that digitally processes and outputs a video signal, and in particular generates a system clock and reference signal synchronized with an input horizontal synchronization signal. Related to synchronous deflection circuits.

[Conventional technology]

In recent years, the development of television receivers has become active, and IDT V (IDTV), which replaces the video circuit that traditionally processes signals with analog circuits with digital circuits to achieve higher image quality.
Io+proved Definition TV) has been put into practical use.

FIG. 2 shows a conventional clock generation/synchronous deflection circuit used in this IDTV. In the same figure, 201
is an input terminal, 202 is a phase comparator (PD), 203 is a low pass filter (LPF), 204 is a voltage controlled oscillator (
VCO), 205 is a 910 frequency divider, 206 is a horizontal output,
207 is flyback transformer (FBT), 2o8・2
09 is a frequency divider.

The horizontal synchronization signal input to the input terminal 201 is input to the phase comparator 202, which is the other input to the frequency divider 2.
08 output, and the result is output according to the phase difference. The output of the phase comparator is filtered by a low-pass filter 203 so as to obtain a predetermined response characteristic, and then input to a voltage controlled oscillator 204. The voltage controlled oscillator 204 emits a signal whose low frequency has an oscillation frequency corresponding to the output of the wave generator 203.

The output of the voltage controlled oscillator 204 is then passed through a 910 frequency divider 205.
The frequency is divided by 910 and a double-speed horizontal synchronizing signal 205 is output. This horizontal synchronizing signal 205 output is simultaneously sent to a horizontal output circuit 206 to perform horizontal scanning. The signal that moves the deflection yoke for horizontal scanning is boosted by a flyback transformer 207. At this time, the frequency of the flyback pulse generated on the secondary side of the flyback transformer is divided by two by a frequency divider 208 and input to the phase comparator 202 . In this way, the circuit constituted by 202 to 208 is subjected to feedback control as a whole, and is controlled so that the output of the frequency divider 208 is phase-synchronized with the input signal from the input terminal 201.

Furthermore, in order to perform digital processing, in addition to the 205 output, which is a signal with the same frequency as the horizontal output circuit 206, the 209 output, which is equal to the horizontal period of the input signal, is divided by 2 by the 2 frequency divider 209. It is obtained by

As such a conventional technique, there is Japanese Unexamined Patent Publication No. 64-29174.

[Problem to be solved by the invention]

In the above conventional technology, the Q value of the voltage controlled oscillator 204 is set low in order to accommodate video signals from various types of equipment whose horizontal frequencies are not accurately managed, and the stability of the generated clock is also low. It became. Therefore, since the clock jitter is large, pixels cannot be correctly matched between lines or fields, and the effect of improving image quality by digital processing is low.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a first clock generating means that generates a burst lock clock that is synchronized with a color burst signal included in a video signal, and a first clock generator that generates a burst lock clock that is synchronized with a horizontal synchronization signal that is included in the video signal. a second clock generating means for generating a line lock clock; a detecting means for detecting whether the video signal is a standard signal conforming to a predetermined standard; When the detection result of the delay means for later delaying and the detection means delayed by the delay means is that the video signal is a signal that conforms to the standard,
a phase control means for phase-synchronizing the second clock with the first clock; a phase control means for inputting the first and second clocks;
and a second clock, a selection means for selecting and outputting one of the second clocks, a synchronization signal generation means for generating a synchronization signal, and a signal processing means for performing signal processing, and the synchronization signal generation means has the above-mentioned. The clock generation circuit is characterized in that it supplies a second clock, and supplies the signal processing means with the clock output from the selection means.

In addition, in order to achieve the above object, the present invention provides a first clock generating means for generating a first clock synchronized with a color burst signal included in a video signal, and a first clock generating means included in the video signal. means for suppressing an equivalent pulse generated by the suppression means; second clock generation means for generating a second clock synchronized with a horizontal synchronization signal included in the output of the suppression means; and the video signal is a signal that conforms to a predetermined standard. a detection means for detecting whether or not the above-mentioned clock is present; and a phase control for synchronizing the phase of the second clock with the first clock when the detection result of the detection means is that the video signal conforms to the standard. means for inputting the first and second clocks, selecting means for selecting and outputting one of the first and second clocks according to the result of detection by the detecting means, and a synchronizing signal. A synchronizing signal generating means for generating a synchronizing signal and a signal processing means for performing signal processing are provided, the synchronizing signal generating means is supplied with the second clock, and the signal processing means is supplied with a clock output from the selecting means. The clock generation circuit is equipped with a clock generation circuit characterized by:

[Function] In the present invention, the detection means detects whether the video signal is an m quasi-signal that satisfies a predetermined standard or a non-standard signal that does not meet a predetermined standard, and determines that the video signal is a jlA quasi-signal. When detected, the phase control means is controlled by the signal delayed by the delay means. The phase control means synchronizes the phase of the line lock clock with the burst lock clock.

Here, for the above signal processing circuit, if a non-standard signal is input, a line lock clock is input, and if a standard signal is input, a burst lock clock or a line lock clock synchronized with the burst lock clock is input. are given respectively. Therefore, in the signal processing circuit, whether a standard signal is input or a non-standard signal is input, the clock that is most effective in improving image quality is supplied, and high image quality can be achieved.

In addition, the synchronization signal generation circuit uses a line lock clock with a wide pull-in range when a non-standard signal is input, and a line lock clock synchronized with the burst lock clock when a standard signal is input. are given respectively. Therefore, in a synchronous circuit, it is possible to synchronize with signals of various pull-in ranges from various types of devices, and when a standard signal is input, a very stable synchronous signal can be generated. Is possible.

In the first method of the present invention, the control timing of the phase control is shifted by the delay means to the non-equivalent pulse period of the video signal. Therefore, the above-mentioned phase control is not applied during the period when the line clock is erratic due to the equivalent pulse, and smooth lock control can be performed as described later.

Furthermore, in the second method of the present invention, equivalent pulses of the video signal are suppressed. Therefore, since there is no equivalent pulse, there is no line lock irregularity due to this, and smooth lock control is possible in this case as well.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG.

In FIG. 1, 101 is an input video signal.

102 is a line lock clock generation circuit, 103 is a line lock clock, 1o4 is a burst lock clock generation circuit, 105 is a burst lock clock, 106 is a standard/non-standard detection circuit, and 108a.

108b is a switch, 109 is a synchronization signal generation circuit, 11o is a signal processing circuit, 111 is a synchronization signal output terminal, 112 is a video signal output terminal, 118 is a synchronization separation/phase comparison circuit, 119 is a voltage controlled oscillator, and 120 is an addition vessel,
113 is a delay circuit.

The operation of this embodiment will now be explained.

The input video signal 101 is sent to the line lock clock generation circuit 102. Burst lock clock generation circuit 104
．． and sent to the standard/non-standard signal detection circuit 106.

The line lock clock generation circuit 102 separates the horizontal synchronization signal included in the video signal, and generates a line lock clock 103 having a frequency 1820 times the frequency fl of the horizontal synchronization signal to the synchronization separation/phase comparison circuit 118. ．．
Adder 120. The signal is generated by a phase locked loop (PLL) circuit including a voltage controlled oscillator 119.

The burst lock clock generation circuit 104 also generates a frequency fj of the color burst signal included in the video signal.
Burst lock clock 1 with a frequency that is 8 times c
05 is generated. This burst lock clock 1
05 is very stable and locked by using a crystal oscillator.

On the other hand, the synchronization signal generation circuit 109 always receives the line lock clock 103 and divides the frequency of this clock 103 to generate a synchronization signal synchronized with the horizontal synchronization signal of the input video signal 101. It is output from 111.

In addition, the standard/non-standard signal detection circuit 106 detects a signal between the frequency fH of the horizontal synchronizing signal of the input video signal and the frequency fsc of the color burst signal, which is the standard of a predetermined broadcasting system (in the case of NTSC). f, C=-f, (1) Detect whether the following relationship is satisfied, and (1)
If the formula holds true, it is determined that the input video signal 101 is an m-quasi signal, and if the formula (1) does not hold, it is determined that the video signal 101 is a non-standard signal. Incidentally, a known example of such a standard/non-4illI quasi-signal detection circuit 1 can be cited, for example, in Japanese Patent Laid-Open No. 184082/1982.

Further, the switch 108a includes a standard/non-standard signal detection port,
! Outputs the detection signal from '6106, and when the input signal is a non-standard signal, it is sent to the line lock clock side.
Further, when the signal is a standard signal, it closes to the burst lock clock side and outputs each clock to the signal processing circuit 110. The signal processing circuit 110 receives the video signal 101 and performs digital signal processing using the clock supplied from the switch 8a. The digitally processed video signal is then output from the video signal output terminal 112.

Next, the operation of clock phase control will be explained. The switch 8b, like the switch 8a, is controlled by a detection signal from the standard/non-standard signal detection circuit 106, and closes the switch when the input video signal 101 is a standard signal, and closes the switch when it is a non-standard signal. open. Therefore, the switch 8b switches the burst lock 105 to the line lock generation circuit 10 only when the signal is a standard signal.
Output to 2.

The line lock clock generation circuit 102 has a switch 8b.
Therefore, when the burst lock clock 105 is input, for the phase of the burst 1-lock clock 105,
Phase control is applied to match the phase of the output line lock clock 103.

Here, the operation of the line lock clock generation circuit 102 will be explained in more detail.

In the line lock clock generation circuit 102, the synchronization separation/phase comparison circuit 118 is configured to input the input video signal 101.
Separate the horizontal synchronization signal included in the.

The phases of the separated horizontal synchronization signal and the frequency-divided output obtained by dividing the line lock clock 103 output from the voltage-controlled oscillator 119 by the frequency divider circuit 121 are compared, and a voltage corresponding to the phase difference is used as a control voltage in an adder. It is input to the voltage controlled oscillator 119 via 120. The voltage controlled oscillator 119 oscillates at a frequency according to the input control voltage, and outputs the oscillation output as the line lock clock 103. Therefore, when the output signal from switch 8b is not input, that is, when clock phase control is not performed, line lock clock 103 becomes a clock synchronized with the horizontal synchronization signal.

On the other hand, when the output signal from the switch 8b is input, that is, when clock phase control is performed, the burst signal input as a signal from the switch 8b is added to the control voltage output from the synchronous separation/phase comparison circuit 118. A lock clock 105 is superimposed. As a result, the line lock clock 103 which is the output of the voltage controlled oscillator 119 is phase-synchronized with the burst lock clock 105. Regarding such circuit operation, please refer to "Nonlinear Circuit Theory" by Masamichi Shimura (Electronic Circuit Course 3), pages 69 to 74.

Next, the phase control timing for the output of the line lock clock generation circuit 102 by the burst lock clock 105 will be explained. FIG. 3 shows an explanatory diagram of the operation of one embodiment of the present invention shown in FIG.

First, a case where phase control is performed within a video period will be described.

FIGS. 3(a) to 3(c) are operational waveform diagrams during the video period. FIG. 3(a) is a waveform diagram of the input video signal 101. During this video period, there is no signal with the same level as horizontal synchronization, such as an equivalent pulse.

The waveform of the output of the synchronous separation/phase comparison circuit 118 maintains a constant DC level as shown in (b). In this case, the burst lock clock 10 is set by the switch 8b.
Even if 5 is applied to the line lock clock generation circuit 102, the DC level will still be DCI as shown in (c). Therefore, the frequency dividing circuit 1 using the line lock clock generation circuit
The phase relationship between the output 21 and the video signal 101 is determined by the switch 8.
It is the same as before the phase control by b.

On the other hand, if phase control is performed within the vertical retrace period, the waveforms will be as shown in FIGS. 3(d) to 3(f). Third
Figure (d) shows a video signal near the vertical retrace period. Do not close switch 8b here.

If the output from the synchronous separation/phase comparison port Ft11118 is shown in the case where the phase control using the stroke clocks 1 and 05 is not performed, the output from the synchronous separation/phase comparison port Ft11118 is found to be near the equivalent pulse as shown in (e). If the switch 8b is closed at point A above e), the output of the synchronous separation/phase comparison circuit 118 is (
f), and after point A.

Try to maintain the DC level at point A, DC2.

In this state, the line lock clock generation circuit 102 is balanced, and in this case, the phase relationship of the output of the frequency dividing circuit 121 with respect to the input video signal 101 is changed to that of the switch 8b.
The phase will change from before the phase control and will be in equilibrium. In this case, all the synchronization pulses created based on the output of the frequency dividing circuit 121 will change before and after the phase control, and the screen will shift momentarily in the horizontal direction. In order to avoid this, the phase control by the switch 8b may be performed after the 0 point where the output of the synchronous separation/phase comparison circuit 118 becomes in a steady state. As is clear from the figure, this phase control timing may be anywhere except near the equivalent pulse. In the present invention, this timing is obtained by the delay circuit 113. A specific example of the delay circuit 113 is a D-type flip-flop, whose D input is connected to the output of the standard/non-standard signal detection circuit 106, and the clock input of the flip-flop is connected to a vertical synchronization pulse that rises outside the equivalent pulse period. Just do it. If this is done, the lock phase of the line lock crotter generating circuit 102 will not change, so the above-mentioned problem will not occur.

FIG. 4 shows an embodiment according to the second means of the present invention. 4 has almost the same configuration as that in FIG. 1, and blocks showing the same functions are given the same numbers as in FIG. 1. Fourth
The difference between the figure and FIG. 1 is that the equivalent pulse suppression circuit 40
1 is provided, and the delay circuit 113 in FIG. 1 is not configured.

Further, FIG. 5 shows another embodiment according to the second means of the present invention. The structure of FIG. 5 is almost the same as that of FIG. 1, and blocks showing the same functions are given the same numbers as in FIG. 1. The difference between FIG. 5 and FIG. 1 is that an equivalent pulse suppression circuit 401 is provided.

Next, the operation of the systems shown in FIGS. 4 and 5 will be explained using FIGS. 6 and 7. As mentioned above, the phase control timing problem is solved by the equivalent pulse in the synchronous separation/phase comparator circuit 1.
This is due to the phase control of the line lock clock generation circuit 102 using the burst lock clock during this period. Therefore, this problem can be solved by suppressing the equivalent pulse and then supplying it to the synchronous separation/phase comparison circuit. Figures 4 and 5 were constructed based on this idea.

In Fig. 4, a vertical gate pulse as shown in Fig. 6(b) that suppresses the equivalent pulse period is generated, and the video No. 43 101 and O
By performing R, an output as shown in FIG. 6(c) is obtained. Then, the output of the synchronous separation/phase comparator circuit 118 becomes a DC level as shown in (d), and there is no period in which the voltage is unstable. Therefore, the problem of phase control timing is eliminated,
Phase control may be performed anywhere.

In Fig. 5, in order to suppress the equivalent pulse, Fig. 7 Jf)
By generating a horizontal gate pulse like this and ORing it with the video signal 101, an output like that shown in FIG. 7(g) is obtained. Then, the output of the synchronous separation/phase comparison circuit 118 will have fewer fluctuations during the period in which the equivalent pulse is suppressed. Then, the delay circuit 113 may remove this turbulent period and perform phase control. If the configuration is as shown in FIG. 5, not only equivalent pulses but also impulse noise as shown in FIG. 7(e) will be mixed into the synchronous separation/phase comparison circuit 118.
It is possible to suppress output errors.

Here, a specific example of the equivalent pulse suppression circuit 401 is shown in FIG. The equivalent pulse suppression circuit 401 receives a clock and counts the clock by a predetermined number using a counter circuit. The count output value is then decoded by a decoder circuit to obtain the gate pulse waveform shown in FIG. 6(b) or FIG. 7(f). Furthermore, the equivalent pulse can be suppressed by ORing this gate pulse waveform and the input video signal.

Hiro: In the explanation so far, we have described suppressing the equivalent pulse before synchronous separation, but of course it is sufficient to suppress the equivalent pulse before the phase comparator circuit, so we can suppress the equivalent pulse after synchronous separation. It may be suppressed.

〔Effect of the invention〕

In the present invention, the phase of the line lock clock is synchronized with the burst lock clock only when the input video signal is a standard signal.

In this way, the signal processing circuit receives a line-locked clock when a non-standard signal is input, and a burst-locked clock or a line phase-synchronized to the burst-locked clock when a standard signal is inputted. A lock clock is given to each. Therefore, in signal processing, it is possible to improve image quality whether a standard signal is input or a non-standard signal is input.

In addition, the synchronization signal generation circuit is provided with a line lock clock when a non-standard signal is input, and a line lock clock synchronized with the burst lock clock when a standard signal is input. . Therefore, the synchronization signal generation circuit can synchronize no matter what kind of non-standard signal is input, and can generate extremely stable synchronization signals when a standard signal is input. It is. Furthermore, when a standard signal is input,
Burst lock clock for signal processing circuit.

Furthermore, since the synchronization signal generation circuit is supplied with a line lock clock that is phase-synchronized with the burst lock clock, the system is essentially supplied with a single clock, which causes problems such as interference due to beats and image quality fluctuations. This has the effect of eliminating possibilities.

By the way, in the first means of the present invention, since phase synchronization control to the line lock clock by the burst lock clock after standard signal detection is performed outside the equivalent pulse period of the input video signal, the line lock clock generation circuit 10
This has the advantage that there is no synchronization phase jump of 2, and there is no problem of synchronization discontinuity associated with this.

In addition, in the second means of the present invention, since the equivalent pulse period of the input video signal is suppressed, the line lock clock is also controlled when the phase of the line lock clock is controlled by the burst lock clock after standard signal detection. This has the advantage that there is no synchronization phase jump in the generating circuit 102, and there is no problem of synchronization discontinuity associated with this.

Furthermore, the second means of the present invention is configured to suppress the equivalent pulse period of the input video signal, but this configuration works to mask signals other than the horizontal synchronization signal, so it is difficult to suppress impulse noise. also has a suppressive effect. Therefore, there is an effect of preventing a phenomenon in which impulse noise causes a synchronization phase jump in the line lock generation circuit 102 in the same way as an equivalent pulse.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment according to the present invention, and FIG.
The figure is a block diagram of a conventional clock/synchronous deflection circuit.
3 is an explanatory diagram of the operation of the clock generation circuit having the configuration shown in FIG. 1, FIG. 4 is a block diagram of another embodiment of the present invention, and FIG. 5 is a block diagram of yet another embodiment of the present invention. 6 is an explanatory diagram of the operation according to the embodiment of FIG. 4, FIG. 7 is an explanatory diagram of the operation according to the embodiment of FIG. 5, and FIG. 8 is an explanatory diagram of the equivalent pulse suppression circuit. 101...Video circuit, 1o2...Line lock clock generation circuit, 103...Line lock clock. 104... Burst lock clock generation circuit, 105
...Burst lock clock, 1o6...Standard/non-standard signal detection circuit, 108a, 108b...Switch. 109...Synchronization signal generation circuit, 110...Signal processing circuit, 111...Synchronization signal output terminal, 112...Video signal output terminal, 118...Synchronization separation/phase comparison circuit. 119... Voltage controlled oscillator, 120... Adder, 1
13 is a delay circuit.

Claims (1)

[Claims] 1. A first clock generating means for generating a first clock synchronized with a color burst signal included in a video signal;
a second clock generation means for generating a second clock synchronized with a horizontal synchronization signal included in the video signal; a detection means for detecting whether the video signal conforms to a predetermined standard; a delay means for delaying the output signal of the detection means so as not to include the equivalent pulse period of the video signal; and a detection result of the detection means delayed by the delay means is a signal in which the video signal conforms to the standard. In this case, phase control means for phase-synchronizing the second clock with the first clock, inputting the first and second clocks, and controlling the first clock according to the result of detection by the detection means. and a second clock, a selection means for selecting and outputting one of the second clocks, a synchronization signal generation means for generating a synchronization signal, and a signal processing means for performing signal processing. 2 clocks,
A clock generation circuit characterized in that the signal processing means is supplied with a clock output from the selection means. 2. first clock generation means for generating a first clock synchronized with a color burst signal included in the video signal;
a suppression means for suppressing equivalent pulses contained in the video signal; a second clock generation means for generating a second clock synchronized with a horizontal synchronization signal contained in the output of the suppression means; a detection means for detecting whether the signal conforms to the standard, and when the detection result of the detection means indicates that the video signal conforms to the standard, the second clock is set to the first clock. a phase control means for synchronizing the phase with the first and second clocks; and a selection for inputting the first and second clocks and selecting and outputting one of the first and second clocks according to the result of detection by the detection means. means, a synchronization signal generation means for generating a synchronization signal, and a signal processing means for performing signal processing, the synchronization signal generation means is supplied with the second clock, and the signal processing means outputs the selection means. A clock generation circuit characterized in that it supplies a clock. 3. A clock generation circuit according to claim 2, wherein the suppression means performs suppression using a vertical synchronization pulse of the video signal. 4. first clock generation means for generating a first clock synchronized with a color burst signal included in the video signal;
a suppression means for suppressing equivalent pulses contained in the video signal; a second clock generation means for generating a second clock synchronized with a horizontal synchronization signal contained in the output of the suppression means; a detection means for detecting whether or not the signal matches the video signal; a delay means for delaying the detection means so as not to include the vicinity of the equivalent pulse period of the video signal; and a detection means for delaying the detection means delayed by the delay means. When the detection result is that the video signal conforms to the standard, a phase control means for synchronizing the phase of the second clock with the first clock;
a selection means for inputting the clock of the clock and selecting and outputting one of the first and second clocks according to the result of detection by the detection means; a synchronization signal generation means for generating a synchronization signal; and a signal processing means for processing,
A clock generation circuit characterized in that the signal processing means is supplied with a clock output from the selection means.