JP2721927B2 - PLL circuit - Google Patents
PLL circuitInfo
- Publication number
- JP2721927B2 JP2721927B2 JP2083049A JP8304990A JP2721927B2 JP 2721927 B2 JP2721927 B2 JP 2721927B2 JP 2083049 A JP2083049 A JP 2083049A JP 8304990 A JP8304990 A JP 8304990A JP 2721927 B2 JP2721927 B2 JP 2721927B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- frequency
- circuit
- oscillator
- phase
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Description
【発明の詳細な説明】 ＜本発明の産業上の利用分野＞ 本発明は発振信号を参照信号に同期させるPLL回路に
関する。The present invention relates to a PLL circuit that synchronizes an oscillation signal with a reference signal.
＜従来技術と解決すべき課題＞ PLL回路は、各種の周波数シンセサイザ、復調器等に
応用されており、例えば、第５図に示す構成を備えてい
る。<Prior Art and Problems to be Solved> The PLL circuit is applied to various frequency synthesizers, demodulators, and the like, and has, for example, a configuration shown in FIG.
即ち、電圧制御発振器（以下VCOと記す）１からの発
振信号は基準となる参照信号とともに位相比較器２に入
力され、その誤差信号が直流増幅器３で増幅されてルー
プフィルタ４に入力され、ループフィルタ４からの制御
信号によりVCO1の周波数および位相は参照信号と同期す
る方向に制御される。That is, an oscillation signal from a voltage controlled oscillator (hereinafter referred to as VCO) 1 is input to a phase comparator 2 together with a reference signal serving as a reference, an error signal thereof is amplified by a DC amplifier 3 and input to a loop filter 4, and The control signal from the filter 4 controls the frequency and phase of the VCO 1 in a direction synchronized with the reference signal.
このため、発振信号の周波数Foは参照信号の周波数Fr
に同期した状態でその周波数変化に追従する。Therefore, the frequency Fo of the oscillation signal is equal to the frequency Fr of the reference signal.
Following the frequency change in a state synchronized with.
この種のPLL回路でVCO1の発振周波数を広帯域に変化
させる場合、VCO1自身の電圧対自走周波数特性（以下VF
特性と記す）の傾きが全帯域で一定であることが望まし
い。When changing the oscillation frequency of VCO1 over a wide band with this type of PLL circuit, the voltage vs. free-running frequency characteristic of VCO1 itself (hereinafter VF
It is desirable that the slope of the characteristic is constant in all the bands.
ところが、一般にVCOのVF特性は第６図に示すよう
に、高域側ほど傾きが小さくなる傾向を有しており、そ
の制御電圧の微小な変化に対する利得係数（dF/dV）は
第７図に示すように周波数領域によって変化する。However, as shown in FIG. 6, the VF characteristic of a VCO generally has a tendency that the slope becomes smaller toward the higher frequency side, and the gain coefficient (dF / dV) for a small change in the control voltage is shown in FIG. As shown in FIG.
このままの状態でPLLループを構成した場合、ループ
ゲインが周波数領域によって大きく変化することにな
り、ループ応答特性等を最適化することができない。If a PLL loop is configured in this state, the loop gain will vary greatly depending on the frequency domain, and the loop response characteristics and the like cannot be optimized.
このため、従来では各周波数領域毎に直流増幅器３の
利得を外部から可変（第５図に示しているように入力抵
抗Riに対する期間抵抗Rfの大きさを変える）して、VCO1
の見かけ上の利得係数が一定となるように補正してい
る。For this reason, in the related art, the gain of the DC amplifier 3 is externally variable (the magnitude of the period resistance Rf with respect to the input resistance Ri is changed as shown in FIG. 5) for each frequency region, so that the VCO 1
Are corrected so that the apparent gain coefficient becomes constant.
しかしながら、このように直流増幅器３による補正回
路を有する広帯域なPLL回路では、高域周波数側でのSSB
位相雑音を十分に抑圧できないという問題があった。However, in such a wideband PLL circuit having a correction circuit using the DC amplifier 3, the SSB on the high frequency side is not used.
There is a problem that the phase noise cannot be sufficiently suppressed.
以下、この問題について説明する。 Hereinafter, this problem will be described.
一般に、VCO自身のSSB位相雑音特性は、キャリア周波
数を中心として所定の広がりを有しており、第８図のよ
うにキャリア周波数がF1のときの特性（イ）と2F1のと
きの特性（ロ）とでは6dBの差をもつことが知られてい
る。In general, SSB phase noise characteristics of the VCO itself has a certain spread around the carrier frequency, characteristics when characteristic when the carrier frequency is F 1 and (b) of 2F 1 as FIG. 8 It is known that (b) has a difference of 6 dB.
この裸特性のVCOを前記PLLループで制御する場合、例
えばオフセット周波数（キャリア周波数からの偏差）10
kHzで−120dBc/Hzの位相雑音をキャリア周波数F1で実現
するためには20dBのループゲインを必要とし、このルー
プゲインが確保されているときの出力信号のSSB位相雑
音は、同図の（ハ）のように抑圧される。When controlling the VCO having the naked characteristic by the PLL loop, for example, an offset frequency (a deviation from the carrier frequency) of 10
The phase noise of -120 dBc / Hz in order to implement a carrier frequencies F 1 in kHz requires a loop gain of 20 dB, SSB phase noise of the output signals when the loop gain is ensured, in FIG ( It is suppressed as in c).
ところが、前記のような直流増幅器３では、第９図に
示すように利得が高くなる程カットオフ周波数が低下し
てしまい、利得係数の補正のために高い利得が必要な周
波数領域で十分な利得が得られず、キャリア周波数2F1
のときに必要な26dBのループゲインを実現することが困
難になる。However, in the DC amplifier 3 as described above, as shown in FIG. 9, as the gain increases, the cutoff frequency decreases, and a sufficient gain is obtained in a frequency region where a high gain is required to correct the gain coefficient. , Carrier frequency 2F 1
In such a case, it becomes difficult to achieve the required 26 dB loop gain.
このため、キャリア周波数が高い場合の位相雑音は第
８図の（ニ）に示すようにオフセット周波数の高域周波
数側（この場合100kHz以上）で抑圧されないで、信号の
純度が著しく低下してしまう。For this reason, the phase noise when the carrier frequency is high is not suppressed on the higher frequency side of the offset frequency (100 kHz or more in this case) as shown in FIG. .
本発明は、この課題を解決して、高純度な信号を広帯
域に出力できるPLL回路を提供することを目的としてい
る。An object of the present invention is to solve this problem and to provide a PLL circuit that can output a high-purity signal in a wide band.
＜課題を解決するための手段＞ 前記課題を解決するために、本発明のPLL回路は、 制御信号により所定周波数範囲にわたって発振周波数
が可変される発振器（21）と、該発振器からの信号と参
照信号との位相を比較し、その位相差に対応する誤差信
号を出力する位相比較器（22）と、該位相比較器からの
誤差信号を制御信号として前記発振器に与えるループフ
ィルタ（24）とを備え、前記発振器の出力信号を前記参
照信号に位相同期させるPLL回路において、 前記位相比較器とループフィルタとの間に挿入され、
前記位相比較器が出力する誤差信号を積分して前記ルー
プフィルタに出力する積分器（23）と、 受動素子からなり前記位相比較器が出力する誤差信号
の交流成分のみを前記制御信号に加えて前記発振器に入
力する交流結合回路（30）と、 利得補正用の抵抗と位相補償用のコンデンサとを並列
接続してなる複数の並列回路と、該複数の並列回路を選
択的に組合せて前記交流結合回路の交流成分の信号経路
に挿入するためのスイッチとからなる補正回路（31）
と、 前記発振器の前記交流成分に対する利得係数が前記所
定周波数範囲の全域にわたってほぼ均一となりSSB位相
雑音が一定レベルに抑圧されるように、前記発振器の発
振周波数に応じて前記補正回路のスイッチを開閉制御す
る制御回路（10）とを備えている。<Means for Solving the Problems> In order to solve the above problems, a PLL circuit according to the present invention includes an oscillator (21) whose oscillation frequency is varied over a predetermined frequency range by a control signal, and a signal from the oscillator. A phase comparator (22) for comparing the phase with the signal and outputting an error signal corresponding to the phase difference; and a loop filter (24) for giving the error signal from the phase comparator as a control signal to the oscillator. A PLL circuit for synchronizing the output signal of the oscillator with the reference signal, wherein the PLL circuit is inserted between the phase comparator and a loop filter,
An integrator (23) for integrating an error signal output from the phase comparator and outputting the integrated signal to the loop filter; and adding only an AC component of the error signal output from the phase comparator to the control signal. An AC coupling circuit (30) to be input to the oscillator; a plurality of parallel circuits formed by connecting a resistor for gain correction and a capacitor for phase compensation in parallel; A correction circuit comprising a switch for insertion into the signal path of the AC component of the coupling circuit (31)
Opening and closing the switch of the correction circuit according to the oscillation frequency of the oscillator so that the gain coefficient of the oscillator with respect to the AC component becomes substantially uniform over the entire range of the predetermined frequency range and SSB phase noise is suppressed to a constant level. And a control circuit (10) for controlling.
＜作用＞ このように構成したため本発明のPLL回路では、位相
比較器から出力される誤差信号の交流成分が、発振器の
発振周波数の帯域に応じて補正されて発振器に加えら
れ、発振器の交流成分に対する利得係数が所定周波数範
囲の全域にわたってほぼ均一となる。<Operation> Due to such a configuration, in the PLL circuit of the present invention, the AC component of the error signal output from the phase comparator is corrected according to the oscillation frequency band of the oscillator and added to the oscillator. Is substantially uniform over the entire frequency range.
＜本発明の実施例＞ 以下、図面に基づいて本発明の一実施例を説明する。Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
第１図は本発明のPLL回路を用いた周波数シンセサイ
ザの構成を示すブロック図である。FIG. 1 is a block diagram showing a configuration of a frequency synthesizer using the PLL circuit of the present invention.
10はPLL回路20からの出力周波数を決定するための周
波数制御回路であり、後述する周波数粗調回路25に対す
る分周比の切換えおよび補正回路31の切換えを行う。Reference numeral 10 denotes a frequency control circuit for determining the output frequency from the PLL circuit 20, which performs switching of the frequency division ratio with respect to the coarse frequency adjustment circuit 25 described later and switching of the correction circuit 31.
PLL回路20のVCO21は前述したVCO1と同様に第６図、第
７図に示した特性を有しているものとする。It is assumed that the VCO 21 of the PLL circuit 20 has the characteristics shown in FIGS. 6 and 7, similarly to the VCO 1 described above.
VCO21の発振出力と参照信号はミキサ型の位相比較器2
2に入力されている。この参照信号は、周波数制御回路1
0に設定されている周波数データに等しい周波数Frの信
号を発生する他回路から入力される。VCO21 oscillation output and reference signal are mixer-type phase comparator 2
Entered in 2. This reference signal is transmitted to the frequency control circuit 1
It is input from another circuit that generates a signal with a frequency Fr equal to the frequency data set to 0.
23は、位相比較器22の誤差信号を積分して直流電圧を
出力する積分器であり、演算増幅器による積分回路で構
成されている。Reference numeral 23 denotes an integrator for integrating the error signal of the phase comparator 22 and outputting a DC voltage, and is configured by an integration circuit including an operational amplifier.
24は、このPLL回路20のループ応答特性を決定するラ
グリード型のループフィルタであり、VCO21に対する制
御電圧を出力する。Reference numeral 24 denotes a lag-lead type loop filter that determines a loop response characteristic of the PLL circuit 20, and outputs a control voltage for the VCO 21.
周波数粗調回路25は、指定された周波数FrにVCO21の
発振周波数を粗調するための回路であり、VCO21の出力
を分周器26で分周し、その分周出力と基準信号（周波数
Fz）とを周波数比較器27へ入力して、両者の周波数差
が、所定値以下となるように積分器23の出力を充放電制
御している。The frequency coarse adjustment circuit 25 is a circuit for coarsely adjusting the oscillation frequency of the VCO 21 to a specified frequency Fr. The frequency of the output of the VCO 21 is divided by a frequency divider 26, and the divided output and a reference signal (frequency
Fz) is input to the frequency comparator 27, and the output of the integrator 23 is subjected to charge / discharge control so that the frequency difference between the two becomes equal to or less than a predetermined value.
30は、位相比較器22とループフィルタ24の間をコンデ
ンサ（C2、C3）結合して位相比較器22の誤差信号に含ま
れる交流信号成分のみをループフィルタ24を介してVCO2
1に伝達する交流結合回路であり、コンデンサC2、C3の
間には、ループ内におけるVCO21の交流成分に対する利
得係数を均一に補正するための補正回路31が設けられて
いる。Reference numeral 30 denotes a capacitor (C 2 , C 3 ) coupled between the phase comparator 22 and the loop filter 24 to convert only the AC signal component included in the error signal of the phase comparator 22 through the VCO 2
This is an AC coupling circuit for transmitting the signal to 1, and a correction circuit 31 for uniformly correcting the gain coefficient for the AC component of the VCO 21 in the loop is provided between the capacitors C 2 and C 3 .
この補正回路31の切換えは、周波数制御回路10によっ
てなされ、例えば所望周波数Frが第６図でFaからFbの範
囲に設定されている場合には両スイッチSb、Scとも開い
たままで、FbからFcの範囲ではスイッチSbが閉じられ、
FcからFdの範囲ではスイッチSb、Scがともに閉じられ
る。The switching of the correction circuit 31 is performed by the frequency control circuit 10. For example, when the desired frequency Fr is set in a range from Fa to Fb in FIG. 6, both switches Sb and Sc are kept open and Fb to Fc The switch Sb is closed in the range of
In the range from Fc to Fd, the switches Sb and Sc are both closed.
各抵抗値RaRb、RaRbRcは、第２図に示すように
VCO21の上限および下限付近の交流信号成分に対する利
得係数が中央部と同一になる値に設定されている。Each resistance value RaRb, RaRbRc is as shown in FIG.
The gain coefficient for the AC signal component near the upper and lower limits of the VCO 21 is set to a value that is the same as that at the center.
また、この各抵抗Ra、Rb、Rcに並列接続されたコンデ
ンサCa、Cb、Ccは、ループ内の位相を安定させるための
位相補償用のコンデンサである。The capacitors Ca, Cb, and Cc connected in parallel with the resistors Ra, Rb, and Rc are capacitors for phase compensation for stabilizing the phase in the loop.
なお、この交流結合回路30の交流信号の通過特性は、
第３図に（ホ）で示した積分器23側の通過特性に対して
同図の（ヘ）に示すようにより高域側の交流成分を通す
ように各コンデンサC1、C2、C3の値が決められている。The AC signal passing characteristic of the AC coupling circuit 30 is as follows.
The capacitors C 1 , C 2 , and C 3 pass through the integrator 23 shown in FIG. 3E so that the AC component on the higher frequency side passes as shown in FIG. Is determined.
したがって、位相比較器とループフィルタ24との間の
信号通過帯域は、積分器23側のカットオフ周波数を越え
た広い範囲にわたってほぼ一定となる（同図（ト））。Therefore, the signal pass band between the phase comparator and the loop filter 24 is substantially constant over a wide range exceeding the cutoff frequency on the integrator 23 side (FIG. 10 (g)).
次に、この周波数シンセサイザの動作について説明す
る。周波数制御回路10に対して周波数Fr（例えばFc＜Fr
＜Fd）が設定されると、周波数粗調回路25の分周器26に
例えばFr＝Ｎ・Fzとなるような分周比Ｎが設定される。Next, the operation of the frequency synthesizer will be described. For the frequency control circuit 10, the frequency Fr (for example, Fc <Fr
When <Fd) is set, the frequency division ratio N is set in the frequency divider 26 of the coarse frequency adjustment circuit 25 so that, for example, Fr = N · Fz.
このため、VCO21の周波数Foは強制的にFr近くの（Ｎ
−１）Fzから（Ｎ＋１）Fzの範囲に制御され、周波数Fr
の参照信号と位相比較器22で位相比較され、PLLループ
の引込みによって参照信号の周波数Frにロックされる。For this reason, the frequency Fo of the VCO 21 is forcibly set to (N
-1) is controlled in the range from Fz to (N + 1) Fz, and the frequency Fr
Is compared with the reference signal by the phase comparator 22, and is locked to the frequency Fr of the reference signal by the pull-in of the PLL loop.
なお、このとき、補正回路31のスイッチSb、Scがとも
にオンするため、ループ内におけるVCO21の交流信号成
分に対する見かけ上の利得係数が抵抗Ra、Rb、Rcの並列
抵抗値（RaRbRc）によって増大し、中央領域と同等
に補正される（第２図）。At this time, since the switches Sb and Sc of the correction circuit 31 are both turned on, the apparent gain coefficient for the AC signal component of the VCO 21 in the loop increases due to the parallel resistance value (RaRbRc) of the resistors Ra, Rb and Rc. , The same as the central area (FIG. 2).
この利得係数は、積分器23側の直流ループの特性に左
右されず交流結合回路30側の交流ループによりオフセッ
ト周波数に対して広帯域にわたってほぼ一定であり、第
４図に示すように１オクターブ以上変化するVCO21の自
走時におけるSSB位相雑音特性（イ）、（ロ）は、
（ハ）に示すように、ともに十分且つ一定レベルに抑圧
され、高純度な信号が出力されることになる。The gain coefficient is substantially constant over a wide band with respect to the offset frequency by the AC loop on the AC coupling circuit 30 side without being affected by the characteristics of the DC loop on the integrator 23 side, and varies by one octave or more as shown in FIG. SCO phase noise characteristics (a) and (b) during self-running of VCO21
As shown in (c), both are suppressed to a sufficient and constant level, and a high-purity signal is output.
＜本発明の他の実施例＞ なお、前記実施例では、UCO21のVF特性に応じて３つ
の補正抵抗Ra、Rb、Rcを用いていたが、これは、実際の
VCOのVF特性を３つの折線で近似したものであり、より
細かく利得係数の補正を行う場合には、さらに周波数領
域を細分化してそれぞれの領域毎抵抗の切換えを行えば
よい。<Another embodiment of the present invention> In the above embodiment, three correction resistors Ra, Rb, and Rc are used according to the VF characteristic of the UCO 21.
The VF characteristic of the VCO is approximated by three broken lines, and when the gain coefficient is to be corrected more finely, the frequency region may be further subdivided to switch the resistance for each region.
また、その切換方法についても前記実施例のように並
列に抵抗を接続しないで、それぞれの周波数領域毎に独
立した抵抗を接続するようにしてもよい。As for the switching method, independent resistors may be connected for each frequency range without connecting the resistors in parallel as in the above-described embodiment.
また、前記実施例ではループフィルタとしてラグリー
ド型のフィルタを用いていたが他の形式のフィルタを用
いてもよい。In the above embodiment, a lag-lead type filter is used as the loop filter. However, another type of filter may be used.
また、前記実施例では、参照信号の周波数にVCO21の
出力を同期させるために周波数粗調回路25を用いていた
が、これは本発明に必要な構成ではなく他の方式を用い
てもよい。Further, in the above-described embodiment, the frequency coarse adjustment circuit 25 is used to synchronize the output of the VCO 21 with the frequency of the reference signal. However, this may be other than the configuration required for the present invention.
また、前記実施例では、VCO21の出力を直接位相比較
器22に入力していたが、VCO21の出力をヘテロダイン変
換して位相比較器22に入力するPLL回路についても本発
明を同様に適用することができる。In the above-described embodiment, the output of the VCO 21 is directly input to the phase comparator 22, but the present invention is similarly applied to a PLL circuit that heterodyne-converts the output of the VCO 21 and inputs the output to the phase comparator 22. Can be.
＜本発明の効果＞ 以上説明したように、本発明のPLL回路は、位相比較
器から出力される誤差信号を積分器で積分してループフ
ィルタに与えるとともに、誤差信号の交流成分を受動素
子からなる交流結合回路を介して発振器へ与え、その交
流結合回路の利得を利得補正用の抵抗と位相補償用のコ
ンデンサとを並列接続してなる複数の並列回路を、発振
器の発振周波数の帯域に応じて選択的に組合せて交流結
合回路に挿入することにより、発振器の交流成分に対す
る利得係数が発振器の周波数可変範囲の全域にわたって
ほぼ均一となるようにしている。<Effects of the Present Invention> As described above, the PLL circuit of the present invention integrates the error signal output from the phase comparator with the integrator and supplies the integrated signal to the loop filter, and also converts the AC component of the error signal from the passive element. A plurality of parallel circuits formed by connecting a resistor for gain correction and a capacitor for phase compensation in parallel with the gain of the AC coupling circuit according to the oscillation frequency band of the oscillator. By selectively combining and inserting the AC coupling circuit into the AC coupling circuit, the gain coefficient of the oscillator with respect to the AC component is made substantially uniform over the entire variable frequency range of the oscillator.
このため、オフセット周波数に対するSSB位相雑音抑
制帯域を、系全体のループゲインが一様な状態で容易に
広帯域化することができ、広い周波数可変範囲にわたっ
てループの応答が最適化された高純度な信号を出力する
ことができる。As a result, the SSB phase noise suppression band for the offset frequency can be easily widened with the loop gain of the entire system being uniform, and the high-purity signal whose loop response is optimized over a wide frequency variable range Can be output.
第１図は本発明の一実施例の構成を示すブロック図、第
２図および第３図は、一実施例の要部の特性を示す図、
第４図は一実施例による雑音抑圧を説明する図である。 第５図は従来回路を示すブロック図、第６図、第７図は
VCOの一般的な特性を示す図である。 第８図は従来回路による雑音抑圧を説明する図、第９図
は従来回路の要部の特性を示す図である。 20……PLL回路、21……VCO、22……位相比較器、23……
積分器、24……ループフィルタ、25……周波数粗調回
路、30……交流結合回路、31……補正回路。FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention, FIGS. 2 and 3 are diagrams showing characteristics of main parts of the embodiment,
FIG. 4 is a diagram illustrating noise suppression according to one embodiment. FIG. 5 is a block diagram showing a conventional circuit, FIG. 6 and FIG.
FIG. 3 is a diagram illustrating general characteristics of a VCO. FIG. 8 is a diagram illustrating noise suppression by a conventional circuit, and FIG. 9 is a diagram illustrating characteristics of main parts of the conventional circuit. 20 …… PLL circuit, 21 …… VCO, 22 …… Phase comparator, 23 ……
Integrator, 24 loop filter, 25 coarse frequency adjustment circuit, 30 AC coupling circuit, 31 correction circuit.
Claims (1)
発振周波数が可変される発振器（21）と、該発振器から
の信号と参照信号との位相を比較し、その位相差に対応
する誤差信号を出力する位相比較器（22）と、該位相比
較器からの誤差信号を制御信号として前記発振器に与え
るループフィルタ（24）とを備え、前記発振器の出力信
号を前記参照信号に位相同期させるPLL回路において、 前記位相比較器とループフィルタとの間に挿入され、前
記位相比較器が出力する誤差信号を積分して前記ループ
フィルタに出力する積分器（23）と、 受動素子からなり前記位相比較器が出力する誤差信号の
交流成分のみを前記制御信号に加えて前記発振器に入力
する交流結合回路（30）と、 利得補正用の抵抗と位相補償用のコンデンサとを並列接
続してなる複数の並列回路と、該複数の並列回路を選択
的に組合せて前記交流結合回路の交流成分の信号経路に
挿入するためのスイッチとからなる補正回路（31）と、 前記発振器の前記交流成分に対する利得係数が前記所定
周波数範囲の全域にわたってほぼ均一となりSSB位相雑
音が一定レベルに抑圧されるように、前記発振器の発振
周波数に応じて前記補正回路のスイッチを開閉制御する
制御回路（10）とを備えたことを特徴とするPLL回路。An oscillator whose oscillation frequency is varied over a predetermined frequency range by a control signal, a phase of a signal from the oscillator and a reference signal are compared, and an error signal corresponding to the phase difference is output. A PLL circuit comprising: a phase comparator (22); and a loop filter (24) for providing an error signal from the phase comparator to the oscillator as a control signal, wherein the PLL circuit synchronizes an output signal of the oscillator with the reference signal. An integrator (23) inserted between the phase comparator and the loop filter for integrating the error signal output by the phase comparator and outputting the integrated error signal to the loop filter; An AC coupling circuit (30) for adding only the AC component of the error signal to be added to the control signal and inputting the signal to the oscillator, a resistor for gain correction and a capacitor for phase compensation are connected in parallel. A correction circuit (31) comprising a plurality of parallel circuits, a switch for selectively combining the plurality of parallel circuits and inserting the plurality of parallel circuits into a signal path of an AC component of the AC coupling circuit; A control circuit (10) that controls opening and closing of a switch of the correction circuit in accordance with the oscillation frequency of the oscillator so that a gain coefficient becomes substantially uniform over the entire predetermined frequency range and SSB phase noise is suppressed to a constant level. A PLL circuit comprising:
Priority Applications (14)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2083049A JP2721927B2 (en) | 1990-03-30 | 1990-03-30 | PLL circuit |
| US07/570,048 US5122763A (en) | 1989-08-25 | 1990-08-20 | Frequency snythesizer for implementing generator of highly pure signals and circuit devices, such as vcq, bll and sg, used therein |
| EP93117167A EP0583800B1 (en) | 1989-08-25 | 1990-08-24 | A voltage controlled oscillator |
| DE69030794T DE69030794T2 (en) | 1989-08-25 | 1990-08-24 | Frequency synthesizer for a generator for generating signals of high purity as well as associated circuit elements such as VCO, PLL and signal generator |
| DE69031738T DE69031738T2 (en) | 1989-08-25 | 1990-08-24 | Voltage controlled oscillator |
| EP93117172A EP0583801A1 (en) | 1989-08-25 | 1990-08-24 | A phase locked loop circuit including a frequency detection function |
| DE69031134T DE69031134T2 (en) | 1989-08-25 | 1990-08-24 | Phase locked loop circuit |
| EP90116261A EP0414260B1 (en) | 1989-08-25 | 1990-08-24 | Frequency synthesizer for implementing generator of highly pure signals and circuit devices, such as VCO, PLL and SG, used therein |
| EP93117188A EP0583802B1 (en) | 1989-08-25 | 1990-08-24 | A signal generator suitable for use in a frequency synthesizer |
| DE69033013T DE69033013T2 (en) | 1989-08-25 | 1990-08-24 | Signal generator for use in a frequency synthesizer |
| EP93117197A EP0583804B1 (en) | 1989-08-25 | 1990-08-24 | A phase locked loop circuit |
| US07/727,840 US5254955A (en) | 1989-08-25 | 1991-07-09 | Advanced phase locked loop circuit |
| US07/727,839 US5160902A (en) | 1989-08-25 | 1991-07-09 | Voltage controlled oscillator with controlled capacitance ratio in positive feedback loop to broaden bandwidth |
| US07/767,012 US5218313A (en) | 1989-08-25 | 1991-09-27 | Frequency synthesizer for implementing generator of highly pure signals and circuit devices, such as VCO, PLL and SG used therein |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2083049A JP2721927B2 (en) | 1990-03-30 | 1990-03-30 | PLL circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03283820A JPH03283820A (en) | 1991-12-13 |
| JP2721927B2 true JP2721927B2 (en) | 1998-03-04 |
Family
ID=13791342
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2083049A Expired - Fee Related JP2721927B2 (en) | 1989-08-25 | 1990-03-30 | PLL circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2721927B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6952644B2 (en) | 2018-05-14 | 2021-10-20 | 株式会社東芝 | Semiconductor integrated circuit |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59138127A (en) * | 1983-01-28 | 1984-08-08 | Nec Corp | Phase controlled oscillating circuit |
| JPS61224641A (en) * | 1985-03-29 | 1986-10-06 | Toshiba Corp | Frequency stabilizing circuit |
-
1990
- 1990-03-30 JP JP2083049A patent/JP2721927B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03283820A (en) | 1991-12-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0583804B1 (en) | A phase locked loop circuit | |
| JP3001735B2 (en) | Phase locked loop frequency synthesizer | |
| KR101012510B1 (en) | Phase-locked loop with automatic frequency tuning | |
| US4952889A (en) | Loop filter modulated synthesizer | |
| JP2729028B2 (en) | Method and circuit for demodulating FM carrier | |
| JP2005532016A (en) | Automatic frequency tuning phase lock loop | |
| JPH0447812A (en) | Frequency synthesizer | |
| JPS62231548A (en) | Frequency modulated signal receiver | |
| JPH07170176A (en) | Device for setting up tuning frequency of pll circuit and its method | |
| US5281930A (en) | Frequency modulator | |
| JP2721927B2 (en) | PLL circuit | |
| US5406631A (en) | Stereo signal demodulator circuit and stereo signal demodulator using the same | |
| US5221911A (en) | Receiver having pll frequency synthesizer with rc loop filter | |
| US5045818A (en) | PLL frequency modulator having bias voltage applied to filter capacitor | |
| EP0361746B1 (en) | Automatic phase controlling circuit | |
| JPH0156580B2 (en) | ||
| US6519008B1 (en) | Filter circuit | |
| JPS5846586Y2 (en) | Circuit with phase locked loop | |
| JPH0459808B2 (en) | ||
| JPS59138127A (en) | Phase controlled oscillating circuit | |
| JP3152929B2 (en) | FM signal demodulation method and FM detector | |
| KR0163900B1 (en) | Plltype fm detecting circuit including amplification stage | |
| JP2000188544A (en) | Phase locked loop circuit | |
| JPH04344713A (en) | Phase synchronizing circuit | |
| JPH01238223A (en) | Pll circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313532 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20071128 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081128 Year of fee payment: 11 |
|
| LAPS | Cancellation because of no payment of annual fees |