JPH0459808B2 - - Google Patents
Info
- Publication number
- JPH0459808B2 JPH0459808B2 JP56204123A JP20412381A JPH0459808B2 JP H0459808 B2 JPH0459808 B2 JP H0459808B2 JP 56204123 A JP56204123 A JP 56204123A JP 20412381 A JP20412381 A JP 20412381A JP H0459808 B2 JPH0459808 B2 JP H0459808B2
- Authority
- JP
- Japan
- Prior art keywords
- input
- frequency
- output
- circuit
- phase
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000001360 synchronised effect Effects 0.000 claims description 10
- 238000000034 method Methods 0.000 description 5
- 230000010355 oscillation Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
- H03L7/23—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop with pulse counters or frequency dividers
- H03L7/235—Nested phase locked loops
Description
【発明の詳細な説明】
本発明は周波数の異なる同期信号を選択可能に
した位相同期回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase synchronization circuit that allows selection of synchronization signals having different frequencies.
位相同期回路は、位相検波器、ループ・フイル
タ、電圧制御発振器（以下VCOと略す）の少く
とも３つで構成される。位相同期回路は入力信号
の位相に追随する回路構成になつており、位相同
期回路内のVCOの発信周波数は、常に入力信号
周波数に一致する。そのため、従来の位相同期回
路は、同期する信号以外に不要な信号が入ると目
的外の信号に同期するために不安定な動作をする
欠点がある。この欠点を補う方法として位相同期
回路に入る前に目的外の信号をフイルタにより阻
止する方法が知られている。しかし、この方法で
は、同期信号の周波数が変化するとフイルタも換
えなければならず、回路規模の増大と高い周波数
において高価になる欠点があつた。 A phase locked circuit is composed of at least three components: a phase detector, a loop filter, and a voltage controlled oscillator (hereinafter abbreviated as VCO). The phase-locked circuit has a circuit configuration that follows the phase of the input signal, and the oscillation frequency of the VCO within the phase-locked circuit always matches the input signal frequency. Therefore, the conventional phase synchronization circuit has the drawback that if an unnecessary signal is input in addition to the synchronizing signal, the circuit synchronizes with the unintended signal, resulting in unstable operation. As a method for compensating for this drawback, a method is known in which unintended signals are blocked by a filter before entering the phase locked circuit. However, this method has the disadvantage that when the frequency of the synchronizing signal changes, the filter must also be replaced, which increases the circuit scale and increases the cost at high frequencies.
本発明の目的はこれらの欠点を除き、周波数の
異なる同期信号を選択でき、選択度の高い位相同
期回路を提供することにある。 SUMMARY OF THE INVENTION An object of the present invention is to eliminate these drawbacks and to provide a phase synchronization circuit that can select synchronization signals of different frequencies and has high selectivity.
本発明によれば、第１のVCOの出力を入力と
する可変Ｎ分周回路と前記可変Ｎ分周回路の出力
を一方の入力とする第１の位相検波器と前記第１
の位相検波器の出力を入力とする、第１のループ
フイルタと、前記第１のループフイルタの出力を
入力とする前記第１のVCOとで、少くとも構成
される位相同期型周波数シンセサイザと、同期信
号が入力される入力端子と、前記入力端子より入
力された同期信号と、前記第１のVCOの出力と
を入力とする第２の位相検波器と、前記第２の位
相検波器の出力を入力とする第２のループフイル
タと前記第２のループフイルタの出力を入力とす
る第２のVCOと、前記第２のVCOの出力を入力
とするＭ分周回路を設け、前記Ｍ分周回路の出力
を前記第１の位相検波器の、もう一方の入力信号
としたことで前記目的が達成できる。 According to the present invention, a variable N frequency divider circuit whose input is the output of the first VCO, a first phase detector whose one input is the output of the variable N frequency divider circuit, and the first
A phase synchronized frequency synthesizer configured at least of a first loop filter that receives the output of the phase detector as an input, and the first VCO that receives the output of the first loop filter as the input; an input terminal into which a synchronization signal is input; a second phase detector which receives the synchronization signal input from the input terminal; and the output of the first VCO; and an output of the second phase detector. a second loop filter that receives as input, a second VCO that receives the output of the second loop filter as input, and an M frequency divider circuit that receives the output of the second VCO as input; The above object can be achieved by using the output of the circuit as the other input signal of the first phase detector.
以下、図面を用いて詳しく説明する。 This will be explained in detail below using the drawings.
図は本発明による位相同期回路の実施例を示
す。同図の第２のVCO１０４は、周波数安定度
の高い、例えば、電圧制御水晶発振器（以下
VCXOと略す）を使用するものとする。 The figure shows an embodiment of a phase-locked circuit according to the invention. The second VCO 104 in the same figure is a voltage-controlled crystal oscillator (hereinafter referred to as VCO) with high frequency stability, for example.
(abbreviated as VCXO) shall be used.
まず、入力端子１０１に同期する信号が入つて
いない状態を説明する。VCXO１０４から出力
されたf1なる周波数の信号は、周波数シンセサイ
ザのステツプ周波数を決めるＭ分周回路１０５に
入り分周され、fzなる周波数の信号を出力する。 First, a state in which no synchronized signal is input to the input terminal 101 will be described. A signal with a frequency of f1 outputted from the VCXO 104 enters an M frequency divider circuit 105 that determines the step frequency of the frequency synthesizer, and is frequency-divided to output a signal with a frequency of fz.
次に、Ｍ分周回路１０５の出力信号を、点線で
囲まれた位相同期型周波数シンセサイザの基準信
号として位相検波器１０６の入力の一方に入力す
る。位相検波器１０６の他方の入力信号として
は、VCO１０９の出力を入力とする可変Ｎ分周
回路１０８の出力信号を使用する。位相検波器１
０６の出力信号はループフイルタ１０７を介して
VCO１０９を制御する。VCO１０９の発振周波
数f3は、基準信号f2に同期した状態において、
f3−Ｎ・f2−Ｎ／Ｍ・f1 ……(1)
となり、その周波数安定度は、VCXO１０４の
周波数安定度で決まる。発信周波数f3は可変Ｎ分
周回路１０８の制御入力端子１１０へ制御信号を
入力することで変化できる。ここで、VCXO１
０４、Ｍ分周回路１０５および点線内の位相同期
型周波数シンセサイザを１つのVCOと考えると、
その制御可能な周波数範囲△f4は、VCXO１０４
の制御可能な周波数範囲を△f1とすると、(1)式よ
り、
Δf4−Ｎ／Ｍ・△f1 ……(2)
となる。 Next, the output signal of the M frequency divider circuit 105 is inputted to one of the inputs of the phase detector 106 as a reference signal of a phase synchronized frequency synthesizer surrounded by a dotted line. As the other input signal of the phase detector 106, the output signal of the variable N frequency divider circuit 108 which inputs the output of the VCO 109 is used. Phase detector 1
The output signal of 06 is passed through the loop filter 107.
Controls VCO109. The oscillation frequency f 3 of the VCO 109 is f 3 −N・f 2 −N/M・f 1 (1) when synchronized with the reference signal f 2 , and its frequency stability is equal to the frequency stability of the VCXO 104. It is determined by The oscillation frequency f 3 can be changed by inputting a control signal to the control input terminal 110 of the variable N frequency divider circuit 108 . Here, VCXO1
04. Considering the M frequency divider circuit 105 and the phase-locked frequency synthesizer inside the dotted line as one VCO,
Its controllable frequency range △f 4 is VCXO104
If the controllable frequency range is △f 1 , then from equation (1), △f 4 -N/M·△f 1 ...(2).
次に入力端子１０１に同期信号が入つた場合を
説明する。入力端子１０１に入つた同期信号は、
VCO１０９の出力信号と位相検波器１０２で位
相比較されその検波出力信号はループフイルタ１
０３を介してVCXO１０４を制御する。入力信
号に同期した信号は出力端子１１０に出力され
る。同回路の同期する周波数およびその範囲は、
ほぼ(1)式と(2)式で求められたものとなる。同期し
た状態における同回路の雑音抑圧特性はループフ
イルタ１０３及びループフイルタ１０７の帯域が
支配的となり決定される。 Next, a case where a synchronization signal is input to the input terminal 101 will be explained. The synchronization signal input to the input terminal 101 is
The phase of the output signal of the VCO 109 is compared with the phase detector 102, and the detected output signal is sent to the loop filter 1.
03 to control the VCXO 104. A signal synchronized with the input signal is output to the output terminal 110. The synchronized frequency and range of the circuit are:
This is approximately calculated using equations (1) and (2). The noise suppression characteristics of the circuit in the synchronized state are determined by the dominant bands of the loop filters 103 and 107.
以上、図で示した本発明による位相同期回路
は、周波数シンセサイザを構成した位相同期回路
と第２のループフイルタ１０３、VCXO１０４
とＭ分周回路１０５を含んだ２重の位相同期回路
を構成しており、周波数シンセサイザの分周比Ｎ
を変えることによつて周波数の異なる同期信号を
選択できる。また、同期する周波数範囲△f4を一
定にして分周比ＮをＭに比べて大きくすれば、△
f1を小さくできるので、VCXO１０４の発信周波
数の安定度を上げることができる。 As described above, the phase-locked circuit according to the present invention shown in the diagram includes the phase-locked circuit that constitutes a frequency synthesizer, the second loop filter 103, and the VCXO 104.
A double phase synchronized circuit including a frequency divider circuit 105 and an M frequency divider circuit 105 is configured, and the frequency divider ratio N of the frequency synthesizer is
By changing , synchronization signals with different frequencies can be selected. Also, if the synchronized frequency range △f 4 is kept constant and the frequency division ratio N is made larger than M, then △
Since f 1 can be made small, the stability of the oscillation frequency of the VCXO 104 can be increased.
更に、分周比ＮをＭに比べて大きくすると、低
い周波数の安定なるVCXOを使用して高い周波
数の同期信号に同期する回路を構成できる。 Furthermore, if the frequency division ratio N is made larger than M, it is possible to construct a circuit that synchronizes with a high frequency synchronization signal using a stable low frequency VCXO.
又、Ｍ分周回路を設けたことで、その分周比Ｍ
によつて周波数シンセサイザのステツプ周波数を
任意に選択できる。 Also, by providing the M frequency divider circuit, the frequency division ratio M
The step frequency of the frequency synthesizer can be arbitrarily selected by .
尚、同回路に使用した周波数シンセサイザは、
VCO１０９の出力信号を直接分周する方式を採
用したが、途中に周波数変換器が入つたものでも
同様に実施できる。 The frequency synthesizer used in this circuit is
Although a method of directly frequency dividing the output signal of the VCO 109 was adopted, the same method can be implemented by inserting a frequency converter in the middle.
その他、本発明による位相同期回路は、周波数
変調波の復調回路等に適しており高い周波数の信
号を直接同回路に入力して復調でき、受信回路の
簡略化を計ることができる。更に、分周比Ｎを変
えることによつて受信周波数を変えることができ
る。 In addition, the phase synchronization circuit according to the present invention is suitable for a demodulation circuit of frequency modulated waves, etc., and can demodulate a high frequency signal by directly inputting it to the same circuit, thereby simplifying the receiving circuit. Furthermore, by changing the frequency division ratio N, the receiving frequency can be changed.
図は本発明による位相同期回路の実施例を示す
構成図である。
図において、１０１は同期信号の入力端子、１
０２，１０６は位相検波器、１０３，１０７はル
ープフイルタ、１０４はVCXO、１０５はＭ分
周回路、１０８は可変Ｎ分周回路、１０９は
VCO、１１０は可変Ｎ分周回路の分周比を変え
るための制御信号入力端子であり、１１１は出力
端子である。
The figure is a configuration diagram showing an embodiment of a phase locked circuit according to the present invention. In the figure, 101 is a synchronization signal input terminal;
02 and 106 are phase detectors, 103 and 107 are loop filters, 104 is a VCXO, 105 is an M frequency divider circuit, 108 is a variable N frequency divider circuit, and 109 is a
VCO 110 is a control signal input terminal for changing the frequency division ratio of the variable N frequency divider circuit, and 111 is an output terminal.
Claims (1)
変Ｎ（Ｎは整数）分周回路と前記可変Ｎ分周回路
の出力を一方の入力とする第１の位相検波器と、
前記第１の位相検波器の出力を入力とする第１の
ループフイルタと、前記第１のループフイルタの
出力を入力とする前記第１の電圧制御発振器とで
すくなくとも構成される位相同期型周波数シンセ
サイザと、同期信号が入力される入力端子と前記
入力端子より入力された同期信号と前記第１の電
圧制御発振器の出力とを入力とする第２の位相検
波器と前記第２の位相検波器の出力を入力とする
第２のループフイルタと前記第２のループフイル
タの出力を入力とする第２の電圧制御発振器と、
前記第２の電圧制御発振器の出力を入力とするＭ
（Ｍは整数）分周回路を設け、前記Ｍ分周回路の
出力を前記第１の位相検波器の、もう一方の入力
信号としたことを特徴とした位相同期回路。1 a variable N (N is an integer) frequency divider circuit that receives the output of the first voltage controlled oscillator as an input, and a first phase detector that receives the output of the variable N frequency divider circuit as one input;
A phase-locked frequency synthesizer comprising at least a first loop filter that receives the output of the first phase detector as an input, and a first voltage-controlled oscillator that receives the output of the first loop filter as an input. and an input terminal into which a synchronization signal is input, a second phase detector which receives the synchronization signal input from the input terminal and the output of the first voltage controlled oscillator, and the second phase detector. a second loop filter that receives the output as an input; and a second voltage controlled oscillator that receives the output of the second loop filter as an input;
M whose input is the output of the second voltage controlled oscillator
(M is an integer) A phase synchronized circuit comprising a frequency dividing circuit, and an output of the M frequency dividing circuit is used as the other input signal of the first phase detector.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56204123A JPS58105630A (en) | 1981-12-17 | 1981-12-17 | Phase synchronizing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56204123A JPS58105630A (en) | 1981-12-17 | 1981-12-17 | Phase synchronizing circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58105630A JPS58105630A (en) | 1983-06-23 |
| JPH0459808B2 true JPH0459808B2 (en) | 1992-09-24 |
Family
ID=16485195
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56204123A Granted JPS58105630A (en) | 1981-12-17 | 1981-12-17 | Phase synchronizing circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58105630A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0528830Y2 (en) * | 1986-03-27 | 1993-07-23 | ||
| JPS6382084A (en) * | 1986-09-25 | 1988-04-12 | Fujitsu Ltd | Oscillation system for highly stable reference frequency |
| JP2724142B2 (en) * | 1986-12-19 | 1998-03-09 | 株式会社リコー | Rotation speed signal generator |
| JP4686432B2 (en) * | 2006-10-13 | 2011-05-25 | 三菱電機株式会社 | Clock phase shift device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5399858A (en) * | 1977-02-14 | 1978-08-31 | Tdk Corp | Phase lock circuit |
-
1981
- 1981-12-17 JP JP56204123A patent/JPS58105630A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5399858A (en) * | 1977-02-14 | 1978-08-31 | Tdk Corp | Phase lock circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58105630A (en) | 1983-06-23 |
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