JPH0528830Y2 - - Google Patents

Description

[Detailed Description of the Invention] A. Field of Industrial Application The present invention relates to an oscillation circuit, and particularly to an oscillation circuit formed by cascading a plurality of PLL circuits.

B. Summary of the invention This invention constitutes a conventional independent feedback circuit.
Instead of an oscillation circuit in which PLL circuits are connected in cascade, each
By cascade-connecting frequency divider circuits, which are the feedback circuits of the PLL circuit, it is possible to obtain an output signal that is more stable and accurate than conventional ones.

C. Prior Art Conventionally, in an oscillation circuit such as a frequency synthesizer, a PLL circuit configuration as shown in Fig. 3 has been used in order to obtain an oscillation output signal with high precision and a stable frequency. .

That is, a phase comparison circuit 1, a low pass filter 2, a voltage controlled oscillator (VCO) 3, a frequency division ratio N
It consists of a frequency divider circuit 4 with a frequency division ratio of M and a frequency divider circuit 5 with a frequency division ratio M.
The PLL circuit 6 receives the original reference signal S1 of frequency 1 obtained from the reference signal oscillation circuit 7, and receives the original reference signal S1.
An output signal S2 of frequency 2 (=1·N/M) locked to 1 is obtained.

By configuring the original reference signal oscillation circuit 7 with, for example, a crystal oscillation circuit, the original reference signal S with high stability and accuracy can be generated.
By outputting 1, the frequency 2 of the output signal S2 can also be obtained stably and with high accuracy.

However, when the frequency 3 of the reference signal S3 input to the phase comparator circuit 1 changes significantly, the loop characteristics of the PLL circuit 6 change greatly, and the frequency-divided output signal S
There is a possibility that the frequency 4 of the reference signal S3 may not lock onto the frequency 3 of the reference signal S3.

For this reason, in the past, the frequency division ratio M of the frequency divider circuit 5 was fixed, and the frequency division ratio N of the frequency divider circuit 4 was changed to output the desired frequency 2 = (1・N/M). A signal S2 is obtained.

However, frequency 2 (=
1・25/6) to obtain the output signal S2,
The frequency division ratio M (=
6) must be set to a large value and the frequency 3 (=1·1/6) of the reference signal S3 input to the phase comparator circuit 1 must be lowered.

However, the reference signal S input to the phase comparison circuit 1
When the frequency 3 of 3 becomes lower, the bandwidth of the low-pass filter 2 must be made narrower accordingly, and as a result, the response speed of the PLL circuit 6 as a whole becomes slower and the stability of the output signal S2 deteriorates. There's a problem.

Therefore, in order to obtain an output signal S2 with a frequency 2 that is in a fractional relationship with the frequency 1 of the conventional original reference signal S1, for example, multiple PLL circuits are connected in cascade as shown in FIGS. 4 and 5. configuration is used.

In other words, the oscillation circuit in FIG. 4, in which parts corresponding to those in FIG. A first PLL circuit 61 consisting of a circuit 51 receives the original reference signal S1, and then outputs a phase comparison circuit 12, a low-pass filter 22,
VCO32, frequency divider circuit 42 with frequency division ratio N2 and frequency division ratio
A second PLL circuit 62 consisting of an M2 frequency divider circuit 52
It receives the output signal S21 of the PLL circuit 61.

The frequency 31 of the reference signal S31 input to the phase comparison circuit 11 of the first PLL circuit 61 is 1·1/M1
Therefore, from the first PLL circuit 61, the frequency 21
An output signal S21 of =1·N1/M1 is obtained.

Therefore, the phase comparison circuit 1 of the second PLL circuit 62
The frequency 32 of the reference signal S32 input to 2 is:
(1・N1)/(M1・M2), and from the second PLL circuit 62 the frequency 22=(1・N1・N2)/
An output signal S22 of (M1/M2) can be obtained.

Therefore, in order to obtain the output signal S22 having the above-mentioned fractional relationship of frequency 1.25/6, the respective frequency division ratios M1, M2, N1, N2 are set as M1=1, M2=6,
If N1 = 5 and N2 = 5, the frequencies 31 and 32 of the reference signals S31 and S32 become frequencies 1 and 1.5/6, respectively, and an output signal S22 with a frequency of 22 = 1.25/6 can be obtained. .

Thus, the first and second PLL circuits 61 and 6
The frequencies 31 and 32 of the reference signals S31 and S32 input to the phase comparison circuits 11 and 12 of No. 2 are maintained at values close to the frequency of the original reference signal 1, and as a result, an oscillation circuit with good response characteristics is obtained. I can do it.

Similarly, in FIG. 5, in which parts corresponding to those in FIG. 4 are given the same reference numerals, a frequency divider circuit 43 with a frequency division ratio N3 (=M2/N1) is provided in place of the frequency divider circuit 41 in FIG. from the third PLL circuit 63 which outputs the output signal S23 via the frequency dividing circuit 52 and the fourth PLL circuit 64 which receives the output signal S23 of the third PLL circuit 63 as the reference signal S32 of the phase comparator circuit 12. configured.

In the oscillation circuit of FIG. 5, as in the case of FIG. 4, the third and fourth PLL circuits 63 and 64
The frequencies 31 and 32 of the reference signals S31 and S32 input to the phase comparison circuits 11 and 12 are respectively 31=1・1/M1 and 32=1・N1/M1=
(1・N1)/(M1・M2), and an oscillation circuit with good response characteristics can be constructed.

D. Problems that the invention aims to solve: However, when PLL circuits are connected in series, the output signal of the next stage PLL circuit becomes locked to the output signal containing the slight phase error and jitter present in one stage PLL circuit. It becomes like this.

Therefore, the output signal S22 that is finally obtained has an error that is the cumulative addition of phase errors and jitter of each PLL circuit that makes up the oscillation circuit.
When PLL circuits are connected in cascade in multiple stages, there is a problem in that it is not possible to obtain a highly accurate and stable output signal.

This idea was created taking the above points into consideration.
In an oscillation circuit with multiple PLL circuits connected in cascade,
This paper attempts to propose an oscillation circuit that can obtain output signals with high stability and precision.

E Means for solving the problem Frequency divider 4 that outputs frequency-divided signals S42 and S45
2, 43, and phase comparators 12, 11 that compare the phases of the frequency-divided signals S42, S45 and predetermined input reference signals S32, S31 and output a phase comparison signal,
Based on the phase comparison signal, a predetermined oscillation signal S24,
It has voltage controlled oscillators 32, 31 that output S25, a plurality of PLL circuits 64, 65 that output oscillation signals S24, 25, and an original reference signal oscillator 7 that oscillates the original reference signal S1, front stage
The oscillation signal S25 of the PLL circuit 65 is supplied as the input reference signal S32 to the PLL circuit 64 in the next stage, and the frequency divider 43 of the PLL circuit 65 in the previous stage is supplied as the input reference signal S32 to the PLL circuit 64 in the next stage.
A plurality of PLL circuits 64 and 65 are connected in cascade so as to supply the frequency-divided signal S42 of the PLL circuit 64,
The first stage of the cascaded PLL circuits 64 and 65
The PLL circuit 65 inputs the original reference signal S1 of the original reference signal oscillator 7 as an input reference signal S31, and outputs the final stage of the cascaded PLL circuits 64 and 65.
The PLL circuit 64 transmits the oscillation signal S24 to the frequency divider 42.
to return to.

F Effect The oscillation signal S24 of the final stage PLL circuit 64 is
The signal is fed back through the frequency dividers 42 and 43 of each PLL circuit 64 and 65, thereby reducing the phase error and jitter contained in the oscillation signal S24.

G. Embodiment An embodiment of the present invention will be described below in detail with reference to the drawings.

In FIG. 1, in which parts corresponding to those in FIG. 5 are given the same reference numerals, except that the output signal S42 of the frequency divider circuit 42 is received by the frequency divider circuit 43.
It has the same configuration as the oscillation circuit shown in FIG.

In the configuration shown in FIG. 1, the frequency 24 of the output signal S24 is the frequency of the output signal S42 of the frequency dividing circuit 42.
42 (=24/N2) is the frequency 32 of the reference signal S32
The frequency dividing circuit 4 of the fifth PLL circuit 65 is controlled to be locked to the frequency dividing circuit 42 via the frequency dividing circuit 42.
3 will be returned.

Therefore, the reference signal S3 of the fourth PLL circuit 64
The output signal S25 of the fifth PLL circuit 65, which is output as 2, is the frequency 45 (=24/ (N1・
N3)=(24·M2)/(N1·N2)) is controlled so as to lock to the frequency 31 (=1/M1) of the reference signal S31.

Therefore, frequency 24 = (1・N1・N2)/(M1・
M2) output signal S24 can be obtained.

According to the configuration of FIG. 1, the fourth and fifth PLLs
Phase comparison circuits 11 and 12 of circuits 64 and 65
Then, the output signal S24 containing the phase error and jitter generated in each PLL circuit 64 and 65 is sent to the frequency dividing circuit 42.
and is fed back via the frequency dividing circuit 43, so that each
Compared to a conventional oscillation circuit in which the feedback circuit of the PLL circuit is configured independently, a highly stable and accurate output signal S24 can be obtained.

FIG. 2, in which parts corresponding to those in FIG. 1 are given the same reference numerals, shows a second embodiment of the present invention, in which
The case is shown when applied to an oscillation circuit formed by cascading PLL circuits.

Of n PLL circuits 64, 65 to 6m
The PLL circuits 64, 66-6m output signals S65-S6(m-1) of the previous stage PLL circuits 65-6(m-1).
-1) is received by each phase comparator circuit 12, 16 to 1m.

Furthermore, the PLL circuits 64, 65 to 6 (m-1) are frequency dividing circuits 43, 44, 46 to 4 (m-1)
, the output signals S44, S4 of the frequency dividing circuits 44, 46-4m of the PLL circuits 64, 66-6m in the subsequent stage
Receive 6-S4m. Thus, the nth stage PLL
The output signal S6m of the circuit 6m is output from each PLL circuit 64 to
It is designed to be returned directly to a height of 6 m.

In the configuration shown in FIG. 2, the output signal S6m is directly sent to each PLL circuit 64, 65 to 6m by the frequency dividing circuit 43,
44, 46 to 4m, and each PLL circuit 64 to 6m receives the feedback signal S4.
4~S4m are reference signals S31, S32, S36~
Its output signal S to match the frequency of S3m
64-S6m Frequency 64-6m is controlled.

Thus, the frequency dividing circuits 43, 44, 46-4m and 51,5 provided in each PLL circuit 64-6m
Output signal S6m determined by the frequency division ratio of 2,56~5m
can be obtained.

According to the configuration shown in Figure 2, each PLL circuit has 64 to 6 m
Since the output signal S6m is fed back to the phase comparator circuits 11, 12, 16-1m of the PLL circuits 11, 12, 16-1m via the frequency dividing circuits 43, 44, 46-4m of each PLL circuit 64-6m, the feedback circuit of each PLL circuit can be made independent. It is possible to obtain an output signal S6m with higher stability and accuracy compared to the conventional oscillation circuit configured as shown in FIG.

H. Effect of the invention As described above, according to the invention, the final stage PLL
Since the oscillation signal of the circuit is fed back to the phase comparator of each PLL circuit, a more stable and accurate output signal can be obtained compared to the conventional case where each PLL circuit forms an independent feedback circuit. be able to.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an oscillation circuit according to the present invention, FIG. 2 is a block diagram of an oscillation circuit having an n-stage cascaded configuration, and FIG. 3 is a block diagram showing the basic configuration of a PLL circuit. 4 and 5 are block diagrams of conventional oscillation circuits consisting of cascaded PLL circuits. 1, 11, 12, 16, 1m... Phase comparison circuit, 2, 21, 22, 2m... Low pass filter, 3, 31, 32, 3m... VCO, 4, 5,
41,42,43,44,46,4m,51,5
2, 56, 5m... Frequency divider circuit, 6, 61, 62,
63, 64, 65, 66, 6m...PLL circuit (oscillation circuit), 7...Reference signal oscillation circuit.

Claims (1)

[Claims for Utility Model Registration] A frequency divider that outputs a frequency-divided signal, a phase comparator that compares the phases of the frequency-divided signal and a predetermined input reference signal and outputs a phase comparison signal, and a phase comparator that outputs a phase comparison signal. a voltage-controlled oscillator that outputs a predetermined oscillation signal based on the signal, a plurality of PLL circuits that output the oscillation signal, and an original reference signal oscillator that oscillates the original reference signal; supplying the oscillation signal of the PLL circuit as the input reference signal of the PLL circuit in the next stage, and supplying the frequency divided signal of the PLL circuit in the subsequent stage to the frequency divider of the PLL circuit in the previous stage; The above plurality of PLL circuits are cascade-connected, and the above-mentioned
The PLL circuit inputs the original reference signal of the original reference signal oscillator as the input reference signal, and inputs the original reference signal of the original reference signal oscillator as the input reference signal.
The PLL circuit is an oscillation circuit characterized in that the oscillation signal is fed back to the frequency divider.