JPH08274629A - Digital pll circuit - Google Patents

Abstract

PURPOSE: To secure a delay accuracy without preparing any high frequency by taking a clock that has the most approximate phase to an input clock signal as an output clock out of those clocks of different phases which are generated from the variably divided clocks. CONSTITUTION: The signals Sin and Sout are inputted to a frequency comparator 8, and the frequency error signals are outputted. A loop filter 7 integrates the frequency error signals and outputs a control signal to a variable divider 6. A clock generation circuit 5 generates M pieces of clocks having equally shifted phases based on the output clock of the divider 6. An output clock selection circuit 3 outputs an optimum signal as an Sout out of M pieces of clocks based on the value of an output clock selection signal, so that the phase error is minimized between both Sin and Sout. In such a way, a clock that has the most approximate phase to the Sin is selected out of those M pieces of clocks, i.e., the Sout is controlled so as to be most approximate to the Sin.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital PLL circuit.

[0002]

2. Description of the Related Art A conventional digital PLL circuit (hereinafter referred to as DP
FIG. 4 shows a configuration example of LL). In FIG. 4, 1 is a digital phase comparator for comparing the phases of an input clock and an output clock, 2 is a decoder for outputting a selection signal from the phase comparison result, 4 is an oscillator for generating a reference clock, and 5 is a plurality of taps for the reference clock. A clock delay circuit that generates M clocks that have the same frequency as the reference clock and are out of phase at equal intervals by delaying with a delay line
Indicates a selection circuit for selecting one of M clocks from the signal of the decoder 2.

First, the phase comparator 1 compares the phases of the input clock Sin and the output clock Sout and outputs a phase error signal. The decoder 2 decodes the phase error signal and outputs the selection signal to the selection circuit. The output of the oscillator 4 is input to a clock delay circuit, and M clocks having different phases are taken out by a delay circuit having a plurality of output terminals.

Next, the clock delay circuit will be described.
When T is the period of the reference clock and M is the number of clocks to generate, the clock delay circuit delays the reference signal by Δtn = (T / M) × N (N = 1, 2, ... M−1). And produce signals with different phases. Δt
n corresponds to the desired resolution of the phase. The delay generation method is
There are a method using a counter and a method using a delay line. In the method using the counter, the reference clock is delayed by a clock having a cycle of Δtn and having a frequency several times higher than that of the reference clock.

There is also a method of generating a desired clock by using a delay line with taps without using a counter. In this method, M taps are provided in a delay line that delays the phase of a signal in an analog manner in order to extract M clocks that are equally out of phase from one reference clock.
Each clock is taken out from there. Based on the output signal of the decoder 2, the selection circuit 3 extracts the clock having the closest phase to the input signal among the M clocks as the output clock signal.

By the above operation, the circuit of FIG. 4 extracts the output signal which is phase-locked with the input signal.

[0007]

In the DPLL circuit of the system shown in the conventional example, M clocks having different phases are
Since the fixed-frequency reference clock is generated by delaying it at equal intervals using a counter or delay line, there is no problem if the input signal Sin and the reference clock frequency match, but Sin and the reference There is a problem that jitter occurs when the clock frequencies are different.

Further, the clock delay circuit is an important element in the DPLL of the system described in the prior art, but the clock delay circuit in the conventional DPLL is
A counter is operated by a high-speed clock to create a delay, or an analog delay line is used to delay the clock to generate a plurality of clocks having different phases. However, in the former method using the counter, the higher the precision of the phase control, that is, the number M of clocks to be generated.
, The higher the phase resolution, the higher the frequency clock required for the clock delay circuit. Further, in the latter method using the delay line, in the delay line for producing M clocks that are accurately out of phase, it is difficult to secure the accuracy of the delay and the change in the characteristics of the delay line due to temperature change,
The process variation of the delay line becomes a problem when integrated into an IC.

[0009]

[Means for Solving the Problems]

(Means 1) In the present invention, since it is possible to follow the frequency fluctuation of the input signal Sin, the input signal Sin and the output signal Sin
By additionally providing frequency control means composed of a frequency comparison means for out and a variable frequency divider for dividing the reference clock according to the evaluation result in addition to the phase control means, the input signal Sin and the output signal Sout Even if the frequencies are different, the variable frequency divider can divide the reference clock to change its period. That is, it is possible to match the frequencies of M clocks, which are generated by delaying the reference clock and have different phases, with the frequencies of the input signal as much as possible, and reduce the jitter of the output signal Sout.

(Means 2) In the present invention, an analog voltage controlled oscillator (VCO) constructed by connecting an odd number of delay inverters in a ring shape in order to generate M clocks which are out of phase with each other. It is possible to generate a plurality of clocks having the same period but different phases by extracting the respective outputs of the inverters.
As a result, unlike the conventional counter delay method, it is possible to obtain a plurality of clocks with an accurate delay amount without adding a clock having a frequency higher than the reference clock, and it is possible to simplify the circuit configuration. Also, for tapped delay line system, accuracy, stability and IC
This is advantageous in terms of ease of conversion.

(Means 3) In the present invention, an analog voltage controlled oscillator (VCO) for generating M clocks whose phases are equally shifted is a voltage control of an analog phase locked loop synchronized with a stable reference clock such as a crystal oscillator. By being provided as an oscillator, the VCO can oscillate at a stable frequency. That is, it is possible to increase the frequency stability of M clocks generated from the VCO and having the same phase shift.

Further, by controlling the feedback clock of the analog phase locked loop with the variable frequency divider, the oscillation frequency of the VCO can be easily changed.

[0013]

The DPLL circuit of the present invention comprises the phase control means (hereinafter referred to as the first loop) for selecting the clock having the closest phase to the input signal from the plurality of clocks having the same frequency as the input signal Sin, and the input signal Sin. And a frequency comparison means for comparing the output signal Sout with the output signal Sout, and a frequency control means (hereinafter referred to as a second loop) for matching the frequency of the reference clock input to the clock generation circuit according to the comparison result.

In the DPLL according to the present invention, first, the frequency comparison means included in the second loop detects the period difference between the input signal and the output signal, and the results are integrated to detect the period difference for a certain period. In this case, the frequency division of the variable frequency divider is changed to match the frequency of Sout with the frequency of Sin. Next, the variable frequency divider generates a plurality of clocks whose phases are shifted from each other by the clock generation circuit from the signals having the same frequency. Details of the clock generation circuit will be described later. The phase comparators included in the first loop are Sin and Sou.
By detecting the phase difference of t and selecting the clock closest to the phase of Sin as Sout from the plurality of clocks having different phases, the phase is followed. Further, the DP of the present invention
The LL circuit extracts, as clock generation means, each inverter output of a delay inverter of an analog voltage controlled oscillator (VCO) configured by connecting an odd number of inverters in a ring shape, so that the frequency of a frequency extremely higher than a desired frequency is obtained. It is possible to generate M clocks whose phases are shifted at equal intervals without adding the clocks to the clock generation circuit. This analog voltage controlled oscillator type clock generation circuit is an analog phase locked loop voltage controlled oscillator that is synchronized with a stable reference clock source (eg, crystal oscillator), and can oscillate at a stable frequency and equal. Clocks with different phases can be generated. Further, the oscillation frequency of the analog VCO type clock generation circuit can be changed by changing the cycle of the feedback signal of the analog phase locked loop by a variable frequency divider or the like.

[0015]

【Example】

(Embodiment 1) Hereinafter, a concrete embodiment of the means 1 of the present invention will be described in detail with reference to FIG. First, Sin and Sout are input to the frequency comparator 8 included in the frequency control loop, and the frequency error signal is output. The loop filter 7 integrates the frequency error signals and outputs a control signal to the variable frequency divider in order to prevent tracking of fine frequency fluctuations.
The variable frequency divider 6 is normally divided by N = 8, but the frequency division ratio N is N-2, N-1, N, N + 1, N + according to the value of the control signal.
It is possible to change the frequency by dividing the master clock generated by the reference oscillator 4 by changing the frequency such as 2.

Next, the clock generating circuit 5 generates M clocks which are out of phase with each other based on the output clock of the variable frequency divider 6. The phase comparator 1 included in the phase control means detects a phase error between Sin and Sout and outputs a phase error signal.

The decoder 2 decodes the phase error signal,
Generate an output clock select signal.

The output clock selection circuit 3 uses the value of the output clock selection signal to output the optimum signal Sout from the M clocks so that the phase error between Sin and Sout is minimized.
Output as The selection circuit 3 selects the clock having the closest phase to Sin from the M clocks having the same phase shift. That is, Sout is controlled so that the phase and frequency are closest to Sin.

(Embodiment 2) Next, a concrete configuration example of the clock generation circuit in the means 2 and the means 3 according to the present invention will be shown below.

In FIG. 2 (a), first, the output of the oscillator 4 is input to the phase comparator 8, which compares the output signal of the voltage controlled oscillator (hereinafter referred to as VCO) 5 with the output of the oscillator and proceeds. The pulse Q1 or the delayed pulse Q2 is output.
The charge pump 7 controls the charge / discharge current of the capacitor C included in the analog loop filter 6 at the next stage by Q1 or Q2. The output voltage of the loop filter 6 changes according to the charging and discharging of the capacitance C by the current signal. Next, the VCO 5 changes the oscillation frequency according to the output voltage of the loop filter 6. The internal structure of the VCO 5 is shown in FIG.

The output voltage signal of the loop filter 6 in FIG. 2A is first converted into a current signal by the I / V conversion circuit 50 and supplied to the ring oscillator 51 in which an odd number of inverter circuits are connected in a ring shape. As shown in FIG. 2B, 51 is configured by connecting an odd number of inverters in a ring shape. Oscillation can be performed by utilizing the delay due to the charging / discharging time of the current with respect to the input capacity per inverter. By controlling the charging / discharging current of the inverter, the delay amount per one stage of the inverter changes, and the oscillation frequency of the ring oscillator 51 is controlled.

With the above configuration, it is possible to obtain a plurality of clocks that are not easily affected by a disturbance such as temperature change and have exactly the same phase shift, without using a higher-order clock.

(Embodiment 3) Next, an embodiment in which the means 1 to 3 are combined will be described.

In FIG. 3, the frequency comparator 9 compares the cycles of the input clock signal Sin and the output clock signal Sout and outputs a frequency error signal. The loop filter 10 integrates the frequency error signal and outputs a frequency control signal. The variable frequency divider 11 frequency-divides the feedback signal to the phase comparator 8 included in the second phase control loop synchronized with the stable clock. The frequency division ratio of the variable division period 11 is controlled by the frequency control signal. That is, the frequency of Sin and S
The oscillating frequency of the analog VCO included in the second phase locked loop is determined so that the out frequencies become substantially equal.
On the other hand, the phase comparator 1 compares the phases of Sin and Sout and outputs a phase error signal.

The analog VCO clock generation circuit 5 oscillates at the above-mentioned frequency and generates M clocks which are equally different in phase. The phase error signal is input to the output clock selection circuit 3, and the output clock selection circuit 3 selects a signal whose phase is closest to Sin from the generated M clocks and outputs it as Sout.

[0026]

As described above, the DPLL according to the present invention
Can realize a highly accurate DPLL without preparing an extremely high frequency for a target clock. In addition, the VC of the analog PLL synchronized with the reference clock
Since O has a configuration in which a plurality of clocks having different phases are generated, it is possible to accurately generate a delayed clock. Further, in the DPLL of the present invention, the frequency of the clock generator can be changed by changing the cycle of the reference clock by using the variable frequency divider, so that the frequency can be synchronized with a wider range of frequencies.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a phase locked loop circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a phase locked loop circuit according to a second embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a phase locked loop circuit according to a third embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of a conventional phase locked loop circuit.

[Explanation of symbols]

 1 ... Phase comparator 2 ... Decoder 3 ... Clock selection circuit 4 ... Reference clock oscillator 5 ... Analog voltage controlled oscillator 51 ... Voltage-current converter 52 ... Ring oscillator 6・ ・ ・ Analog loop filter 7 ・ ・ ・ Charge pump 8 ・ ・ ・ Phase comparator 9 ・ ・ ・ Frequency comparator 10 ・ ・ ・ Loop filter 11 ・ ・ ・ Variable frequency divider

Claims (3)

[Claims] 1. A phase comparison means and a frequency comparison means for an input clock signal and an output clock signal, and a clock generation circuit for generating M clock signals having the same frequency but different phases from a reference clock, the frequency comparison means. Based on the frequency comparison result according to (1), the master clock is variably divided, and the number-of-cycles control means for controlling the cycles of the input clock signal and the output clock signal to be as equal as possible, and the phase comparison result output by the phase comparison means A digital PLL circuit having a phase control means for extracting, as an output clock, a clock having a phase closest to the input clock signal from M clocks having different phases generated from the variable frequency-divided clock. 2. In a digital PLL for performing phase control by selecting a clock whose phase is closest to that of an input signal from M clocks having different phases, the M clocks having different phases are an odd number of inverter circuits. A digital PLL circuit comprising a clock generation circuit configured to take out from outputs of respective delay inverters of an analog voltage controlled oscillator (VCO) configured to be connected in a ring shape. 3. The VCO according to claim 2 is provided as a VCO of an analog phase locked loop synchronized with a reference clock, and the feedback clock frequency division number in the analog phase locked loop is changed by using a variable frequency divider. Accordingly, a digital PL including a plurality of clock generation circuits capable of changing the frequency of the reference clock
L circuit.