JPH10173498A - Variable delay circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a variable delay circuit capable of setting an external clock cycle as a reference with respect to the size of a delay time, and of setting a timing being the reference of the generation of delay time as the input timing of an input signal to be inputted at random. SOLUTION: In the variable delay circuit, the reference point of a delay time (delay starting timing) is set as the input timing (falling timing) tin of an input signal Sin irrespective of the external clock CK0 . Thus, a VCO 111b for starting an oscillating operation based on an oscillation control signal OScont at the same time as the applying of the input signal Sin is separately provided from a phase-locked-loop circuit 110a for performing an operation synchronized with the external clock CK0 , and the VCO 111b generates oscillated output. A synchronizing inner clock CKSINK which is synchronized with the input signal Sin is counted by a counter 112, and the counter output Cout is outputted as a delay circuit to the input signal Sin .

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable delay circuit, and more particularly, to a circuit configuration that can use an external clock cycle as a reference for a delay time and set an arbitrary trigger signal input timing as a signal delay start timing. Things.

[0002]

2. Description of the Related Art Conventionally, there are various types of delay circuits. For example, as a simple circuit configuration, as shown in FIG. 13A, a plurality of serially connected delay gates C ₁ , C ₂ ,
There is a delay circuit 50 composed of C ₃ ,..., C _X. In this delay circuit 50, as shown in FIG. 13 (b), when the input signal S _IN is input to the input terminal 51a, the output terminal 5
1b outputs a delayed output S _OUT obtained by delaying the input signal S _IN by a predetermined time Td.

That is, in the delay circuit 50, the basic delay time is the delay time tpd of each delay gate composed of, for example, an inverter or the like. Delay time T
d (= tpd × X). Normally, the delay time in each delay gate is 10 to 100 ps. For example, if this delay time is 100 ps,
If they are arranged in series, a delay time of about 1 ns can be obtained.

However, when a plurality of delay circuits are used to generate a plurality of delay signals, the delay time of each delay circuit 50 varies due to variations in the characteristics of the delay gates. is there. For example, as shown in FIG.
0a _1, 50a _2, ···, equipped with 50a _n, a plurality of delayed outputs SD required the signals S ₁ and delayed by respective delay circuits
_1, SD _2, · · ·, when configured to generate a SD _n, variation of the device, i.e. the variations in the characteristics of configuration elements of the delay gates in the delay circuits, in each of the delay circuits 50a ₁ ~50a _n, that This means that a desired delay time corresponding to the number of stages of the delay gate cannot be obtained.

Therefore, a variable delay capable of obtaining a desired delay time based on the cycle of a reference clock such as an external clock, specifically, a delay time which is n / M times (n and M are natural numbers) times the cycle of the external clock. Delay circuits have already been developed.

FIG. 14 (a) is a block diagram showing an example of the configuration of such a variable delay circuit, and FIG. 15 (a) is its PLL (P
FIG. 3 is a block diagram illustrating a configuration of a control system. In the figure, reference numeral 200 denotes a conventional variable delay circuit using a PLL control system. The variable delay circuit 200 generates a voltage controlled oscillator (VCO: Voltage CCO) that generates an internal clock CK _PLL having a predetermined cycle based on the oscillation control signal OScont.
phase locked loop circuit 2 having an ontrolled oscillator (240) and controlling its oscillation frequency by a PLL control system.
01a and the oscillation output of the VCO 240 (internal clock)
The CK _PLL is counted, and the count value is equal to the set value C
s (that is, the count value from the start of counting to the occurrence of the counter output), the counter 202 generates a counter output Sout and changes the set value Cs by the set value control signal CDcont. It has.

[0007] The above-mentioned phase locked loop circuit 201 is shown in FIG.
As shown in FIG. 5 (a), an oscillator control means 201a which receives the external clock CKo and the internal clock CK _PLL, and controls the oscillation frequency of the VCO 240 by the oscillation control signal OScont so that their phases match. VCO
And an n / M frequency divider 250 that divides the output CK _PLL of 240 by n / M (in this case, １ ／ frequency division), and synchronizes the internal clock CK _PLL with the external clock CKo and the period thereof. Period T _PLL of a predetermined multiple (here, 1/8 times) of T _O
It is configured to have the following.

Here, the oscillator control means 201a includes:
The external clock CKo and the frequency-divided output CK of the n / M frequency divider
_The phase comparator 210 compares the phase of the signal _DM with the signal _DM, and outputs a signal (phase comparison output) PD including phase difference information indicating which phase is advanced by how much. The phase comparator 210 converts the phase comparison output PD into a voltage V _PD . And a loop filter 230 that extracts a DC component of the output of the charge pump 220 and uses the extracted DC component as the oscillation control signal OScont.

[0009] Specifically, the circuit configuration of the phase comparator 210, for example, one of the external clock CKo and the divided output CK _DM, amount of phase lead with respect to its other, a pulse width corresponding to the phase delay A circuit configuration for outputting a phase advance pulse and a phase delay pulse is used.
In this case, for example, the charge pump 220 has a circuit configuration that charges a capacitor according to the pulse width of the phase lead pulse and discharges the capacitor according to the pulse width of the phase delay pulse. Further, the loop filter 230 receives a voltage generated at both ends of the capacitor, and extracts the voltage as a signal obtained by averaging voltage fluctuations caused by individual phase advance pulses or phase delay pulses.

Further, the voltage controlled oscillator 240 has a configuration shown in FIG.
5 (b) as shown in, the delay gate adjustable delay time by the oscillation control signal OScont, are those formed by 2n + 1 stages connected in a ring, the delay gates A ₁ to A of each stage
_{The 2n + 1} delay time adjustment terminals are commonly connected to form an oscillation frequency adjustment input terminal 24a.
The oscillation control signal OScont is applied. Here, assuming that the delay time per one stage of the delay gate is tpd, the oscillation frequency F of this VCO 240 is F = １ ／ tpd (2n + 1).

As described above, the VCO 240 can adjust its oscillation frequency by adjusting the delay time tpd per delay gate by the oscillation control signal OScont.

Incidentally, in FIGS. 14A and 15A, 20
Reference numerals a, 20b, 21a, and 21b denote an external clock input terminal, a delay output terminal, a delay input terminal, and a delay control terminal of the variable delay circuit 200, respectively, 20c an internal clock output terminal of the phase locked loop circuit 201, and 24b a VCO.
Reference numeral 240 denotes an internal clock output terminal, and reference numerals 21c and 21d denote an internal clock input terminal and an external clock input terminal of the counter 202.

Next, the operation will be briefly described with reference to FIG. In the variable delay circuit 200, the internal clock CK generated in the phase locked loop circuit 201 is used.
_By counting the _PLL by the counter 202, a delay time Td that is an integral multiple (in this case, four times) of the cycle T _PLL of the internal clock CK _PLL is generated.

That is, as shown in FIG. 15A, when the external clock CKo is input to the input terminal 20a, the external clock CKo and the divided clock CK are input.
Phase comparison between _DM is performed by the phase comparator 210, the phase comparison output PD is converted by the charge pump 220 to the voltage V _PD, further the output voltage V _PD is the loop filter 2
30 as the oscillation control signal OScont as the VCO 240
Is applied to the oscillation frequency adjustment input terminal 24a.

In the VCO 240, the delay time tpd in each delay gate is determined based on the oscillation control signal OScont.
Is adjusted, and the period T _PLL (= 1 /
An internal clock CK _PLL of F = 2tpd (2n + 1)) is generated, and the subsequent stage n / M frequency divider 250 divides the internal clock CK _PLL by n / M. Where n / M is 8
It is. The frequency-divided clock CK _DM of the internal clock CK _PLL is input to the phase comparator 210 together with the external clock CKo, where the phases of these clocks are compared.

In the variable delay circuit 200, the PLL
The control system is stable, i.e. the frequency and phase of the external clock CKo, by repeating this operation until the frequency and phase of n / M frequency-divided clock CK _DM matches, the internal clock output terminal 24b of the VCO240 is The internal clock CK _PLL synchronized with the external clock CKo is output.

At this time, a set value control signal CDcont is supplied to the delay control terminal 21b of the counter 202, and the counter 202 generates a counter output from the start of counting of the internal clock CK _PLL by this signal. For example, four are set as the count setting values Cs. At this time, the internal clock CK _PLL and the external clock CKo are supplied to the respective clock input terminals 21c and 21d of the counter 202.

In this state, when the input signal S _in is supplied to the delay input terminal 21a of the counter 202, the counter 202 synchronizes with the external clock CKo and has an internal clock having a period of n / M times as long as the external clock CKo. CK _PLL
Is counted as the rising timing t _O of the first external clock CKo after the input time t _in of the input signal S _in.
When the count value reaches the set value Cs (timing t _out ), the counter output S _out is generated as a delayed output with respect to the input signal S _in . The counter 202 is reset when a reset time T _cr elapses after the generation of the counter output S _out .

The delay time Td generated at this time is as shown in FIG.
(b), the rising timing t _o of the next external clock CKo timing t _in the input signal S _in enters as a trigger is a reference.

In the variable delay circuit 200 having such a configuration, the delay time Td can be set by the set value Cs of the counter 202 that counts the internal clock CK _PLL output from the VCO 240. A large delay time can be easily obtained as compared with. For example, in a delay circuit 50 having delay gates connected in series as shown in FIG. 13A, if a delay time of one delay gate is 100 ps, a delay gate of 10 ns is required to obtain a delay time of 10 ns. In the variable delay circuit 200, only the set value Cs of the counter 202 is changed by the set value control signal CDcont, and the cycle T of the internal clock CK _PLL is changed.
_The delay time Td can be freely set in units of _PLL . Specifically, the frequency of the external clock CKo is 100M
Hz, and the frequency of the internal clock CK _PLL can be 1 GHz, which is about ten times as high as that when GaAs is used as a constituent material of the circuit element. Therefore, the variable delay circuit 20
At 0, to obtain a 10 ns delay time, the counter 202
May be set to 10.

In the above case, the delay circuit 50 needs power to drive 100 delay gates, and furthermore, due to variations in the characteristics of the individual delay gates, a delay just 100 times the unit delay time tpd is required. Although it is difficult to obtain a time, in the variable delay circuit 202, since VCO240 is feedback controlled by the PLL control system, the frequency of the internal clock CK _PLL, the external clock regardless of variations in characteristics of components of VCO240 CK
_O is a fixed multiple of the frequency of _O, and the delay time Td can be set with reference to the period To of the external clock CKo. The control can be accurately performed by the control signal CDcont having the value Cs.

Next, another configuration example of the conventional variable delay circuit will be described. FIG. 16A shows a DLL (Delay-Locked Lo
op) is a block diagram illustrating a circuit configuration of a variable delay circuit using a control system. In the figure, reference numeral 300 denotes a conventional variable delay circuit using DLL control. This variable delay circuit 3
00 indicates that the external clock CKo is supplied to the delay time control signal DTco.
voltage control delay circuit (VC
DL: Voltage Controlled Delay Line) 340 and a delay circuit that receives the feedback output D _FB of the output clock of the delay circuit 340 and the external clock CKo, and controls the delay circuit 340 so that the phases of these clocks match. Control means 300a and the delay circuit 340
And the delay output Se between the input and the input signal S _in, AND gate 3 for outputting the delay output So with respect to the input signal S _in
01, and the delay circuit 340 and its control means 300b constitute a delay locked loop circuit 300a that synchronizes the output clock of the delay circuit 340 with the external clock CKo.

[0023] The delay locked loop circuit 300a is the external clock CKo and performs phase comparison between the feedback output D _FB, signal including the phase difference information indicating which advances extent any phase (phase comparison output) PD And a phase comparator 310 which outputs the voltage V
_{It comprises} a charge pump 320 for converting to a _PD , and a loop filter 330 for extracting the DC component of the output of the charge pump 320 and using the extracted DC component as the delay time control signal DTcont. Here, the phase comparator 310, the charge pump 320, and the loop filter 330 are the same as those in FIG.
Has the same configuration as that of the variable delay circuit 200 shown in FIG.

The voltage control delay circuit (hereinafter, VC)
Abbreviated as DL. ) 340 are the delay time control signals DT connected in series as shown in FIG.
The K stage delay gates B ₁ , B ₂ , B ₃ ,..., B _K whose delay time can be adjusted by cont, and the input signals of the delay gates of each stage are selected and output by the delay stage number control signal DScont. are those composed of a selector 340a, a delay time adjustment terminal of the delay gate B ₁ .about.B _K of each stage has a gate delay adjustment terminal 34a are commonly connected to the terminal 34a is, the delay time control signal DTcont is applied. Here, assuming that the delay time per stage of the delay gate is tpd, a signal is input to the delay input terminal 34b and then the delay feedback terminal 34c
The delay time Td until the data is output to is as follows: Td = k × tpd. In FIG. 16, 34d and 34e are VCDL3.
40, a delay control terminal and a delay output terminal.
Reference numerals 1 and 32 denote a delay input terminal and a delay output terminal of the variable delay circuit 300.

In such a VCDL 340, the time until the signal input to the delay input terminal 34b is output to the delay feedback terminal 34c is adjusted by the delay time control signal DTcont, so that the selector 3
The variable width of the delay time that can be changed by the
It is possible to adjust the total TD _k (see FIG. 17) of the delay time in each delay gate constituting CDL 340.
Therefore, the total TD of the delay time at each delay gate
The _k, by matching the period T _O of the external clock CKo, the delay time is set by the selector 340a T
The d, those based on the period T _O of the external clock CKo,
That is, the period T _O can be set to an integral multiple of a value (T _O / k) obtained by dividing the number of stages of the delay gate k. The resolution of the delay time Td at this time is the delay time tpd at each delay gate.

Next, the operation will be briefly described with reference to FIG. In the variable delay circuit 300, a clock delayed by one cycle from the external clock CKo is generated as a delayed feedback output D _FB by the delay locked loop circuit 300a in a state where the DLL control system is stable. In VCDL 340, the delay stage number control signal D is selected from the outputs DG _{1 to} DG _k of the _k delay gates.
External clock CK for delay time TDe corresponding to Scont
o Select the delay clock DG ₃ was delayed, and outputs to the delay output terminal 34e this as a selector output Se. In this state, the input signal S _in is output from the AND gate 3
01, the input signal S _in and the selector output Se are input to the AND gate 301.
The delay output as the delayed output S _out a logical product of the 3
Output to 2.

[0027] That is, in the state where the DLL loop control system is stable, the phase comparison between the external clock CKo and the internal clock (delayed feedback signal) V _PD is performed in the phase comparator 310, the phase comparison output PD There are V _PD converted into a voltage by the charge pump 320, further the voltage output V _PD is applied to the delay time control input terminal 34a of VCDL340 as a delay time control signal DTcont via the loop filter 330.

In the VCDL 340, the unit delay time tpd in each delay gate is adjusted based on the delay time control signal DTcont, and the total T
Internal clock DG _k delayed by time D _k is generated as a delayed feedback output D _FB. The internal clock D _FB is input to the phase comparator 310 together with the external clock CKo, where the phases of these clocks are compared.

In the variable delay circuit 300, the DLL
Loop control system is stabilized, that is by the phase of the internal clock D _FB of the external clock CKo repeats this operation until it matches, the delayed output terminal 34e of the VCDL340 the delay clock synchronized with the external clock CKo (Selector output) Se is output.

In this state, the AND gate 30
When an input signal S _in is applied to one input terminal 31, a logical product of the input signal S _in and the selector output Se is output from the delay output terminal 32 of the AND gate 301 as a delay output S _out .

The delay time Td generated at this time is as shown in FIG.
As shown in FIG. 7, the timing is not the timing t _in at which the input signal S _in enters as a trigger, but the rising timing t _O of the external clock immediately thereafter.

In the variable delay circuit 300 using such a DLL control system, the number of delay stages in the VCDL 340 is determined by a delay stage number control signal DS for controlling the selector 340a.
Since it can be set by cont, the delay time can be easily changed. Further, since VCDL340 is feedback controlled by the DLL control system, the total TD _k of the delay time of each delay gate, one cycle of the external clock CKo T
_The delay feedback output D
_FB phase becomes a be consistent with no external clock phase relationship to variations in characteristics of components of VCDL340, can set the delay time Td of the period T _O of the external clock CKo for reference. Thereby, the variable delay circuit 300
Then, the external clock CK is output from the selector 340a.
o the delay time Td of the integral multiples 1 / k twice the time as the unit delay time of the period T _O is possible to reliably obtain the.

The unit delay time of the variable delay circuit 300 is based on the delay time tpd of each delay gate, specifically, 10 to 100 ps. As shown in the variable delay circuit 200, the unit delay time is equal to the internal clock CK.
Compared to what is the period T _PLL (1ns) about the _PLL,
Suitable for generating a small delay time.

[0034]

By the way, as the above-mentioned delay time Td, there is a case where it is desired to use the delay time Td based on the rising timing t _in of the input signal S _in . That is, there may be a delay circuit which starts measurement of the input and at the same time the delay time of the input signal S _in to generate a delayed signal to the input signal S _in is required.

However, the above-mentioned PLL control system and DLL
Variable delay circuits 200 and 3 using phase control by a control system
00, to generate a delay time Td relative to the period T _O of the external clock CKo, the external clock CK
The phase of the internal clock CK _PLL or D _FB is compared with the phase o and the phase of the internal clock is locked with respect to the external clock CKo. Therefore, in the variable delay circuit described above, even if the input signal S _in as an input trigger for the delay time generated in the variable delay circuit, instead of the input timing t _in the input signal S _in, then the external clock CKo Signal S _{in with} respect to the input signal S _{in based} on the rising (or falling) edge t _O of
_out will occur. That is, in the variable delay circuits 200 and 300, only the delay time Td based on the external clock CKo can be generated, and like the delay circuit 50 shown in FIG. _The delay time Td cannot be generated based on in.

In short, the conventional variable delay circuits 200 and 3
00, instead of generating a constant delay time as a trigger input timing t _in the input signal S _in, last for the reference delay time generator is an external clock CK _O rising (or falling) edge t _O However, a delay time triggered by an arbitrary input signal cannot be obtained.

The present invention has been made in order to solve the above-mentioned problems, and the magnitude of the delay time can be set with reference to the period of the external clock. That is, an object of the present invention is to provide a variable delay circuit that can set the delay start timing of an input signal to be the input timing of an input signal that is randomly input.

[0038]

A variable delay circuit according to the present invention (claim 1) includes a first oscillator for generating a first internal clock having a predetermined cycle based on an oscillation control signal, an external clock, and an external clock. Oscillator control means for controlling the oscillation frequency of the first oscillator by the oscillation control signal based on the frequency-divided clock of the first internal clock so that the phases of the clocks coincide with each other; A phase-locked loop circuit whose frequency-divided clock is synchronized with the external clock and has a cycle that is a predetermined multiple of the external clock. Generating a second internal clock synchronized with the input signal, the second internal clock having a cycle that is a predetermined multiple of the external clock based on the oscillation control signal output from the oscillator control means; And a counter that counts the second internal clock, generates a counter output when the count value reaches a set value, and changes the set value by a set value control signal, The counter output is output as a delay signal with respect to the input signal.

According to a second aspect of the present invention, in the variable delay circuit according to the first aspect, the first and second oscillators each include a plurality of semiconductor elements formed on a semiconductor substrate. A semiconductor circuit comprising a circuit and constituting the first oscillator and a semiconductor circuit constituting the second oscillator are arranged on the semiconductor substrate so as to be adjacent to each other.

According to a third aspect of the present invention, in the variable delay circuit according to the first aspect, the first and second oscillators each include a semiconductor element formed on a semiconductor substrate as a constituent element. A plurality of gate circuits forming the first oscillator and a plurality of gate circuits forming the second oscillator are alternately arranged on the semiconductor substrate. is there.

The variable delay circuit according to the present invention (claim 4) has a plurality of stages of delay gates connected in series, and uses an external clock to set a delay time control signal for setting the delay time of each stage delay gate. A first delay circuit that delays by a predetermined time based on the external clock and the output of the first delay circuit, and controls each of the first delay circuit by the delay time control signal so that their phases match. A delay lock loop circuit including a delay circuit control means for controlling a delay time of the delay gate, wherein the output of the first delay circuit is synchronized with the external clock; and a plurality of stages of delay gates connected in series. Based on a delay time control signal output from the delay circuit control means, sequentially outputting the set number of delay gates by the number of delay gates, and setting the set number of delay stages And a second delay circuit can be changed by the control signal, the output of the second delay circuit is output as a delay signal to the input signal.

According to a fifth aspect of the present invention, there is provided the variable delay circuit according to the first aspect, further comprising a plurality of stages of delay gates connected in series, wherein the synchronous internal clock is supplied to the delay time of each stage delay gate. A first delay circuit that delays a predetermined time based on a delay time control signal that sets the first and second internal clocks and an output of the first delay circuit;
A delay circuit control means for controlling a delay time of each delay gate in the first delay circuit by the delay time control signal so that these phases coincide with each other; and outputting an output of the first delay circuit to the first or the first delay circuit. A delay lock loop circuit synchronized with a second internal clock; and a delay gate of a plurality of stages connected in series. The counter output is converted to a delay time control signal output from the delay circuit control means. A second delay circuit capable of changing the set number of stages by a delay stage number control signal, and outputting the output of the second delay circuit. , And outputs the counter output, which is a delay signal for the input signal, as a final delayed signal that is delayed.

According to a sixth aspect of the present invention, in the variable delay circuit according to the first aspect, the second delay circuit is connected between the second oscillator and the counter and is an output of the second oscillator.
An additional variable delay circuit unit that delays the internal clock of and supplies the counter to the counter, the additional variable delay circuit unit includes a plurality of stages of delay gates connected in series, and the second internal clock is A first delay circuit that delays by a predetermined time based on a delay time control signal that sets a delay time of a delay gate of each stage; and a second internal clock and an output of the first delay circuit. Delay circuit control means for controlling the delay time of each delay gate in the first delay circuit by the delay time control signal so that the phases coincide with each other;
A delay lock loop circuit for synchronizing the output of the delay circuit with the second internal clock, and a plurality of stages of delay gates connected in series. A second delay circuit that sequentially delays and outputs the set number of stages based on the delay time control signal output from the control means and that can change the set number of stages by the delay stage number control signal; And the counter is configured to count the output of the second delay circuit.

According to a seventh aspect of the present invention, in the variable delay circuit according to the first aspect, an additional variable delay circuit for delaying a second internal clock synchronized with the input signal, which is an output of the second oscillator. And a flip-flop that receives the output of the additional variable delay circuit and the counter output as inputs. The additional variable delay circuit has a plurality of stages of delay gates connected in series, A first delay circuit for delaying the internal clock of the second clock by a predetermined time based on a delay time control signal for setting a delay time of the delay gate of each stage; and a second internal clock and an output of the first delay circuit. And delay circuit control means for controlling the delay time of each delay gate in the first delay circuit by the delay time control signal so that their phases match. The output of the first delay circuit is The above A delay lock loop circuit that is synchronized with the internal clock, and a plurality of stages of delay gates connected in series. The delay clock control signal is an output of the delay circuit control means. And a second delay circuit capable of changing the set number of stages by a delay-stage number control signal and sequentially outputting the delayed signals by the number of delay gates corresponding to the set number of stages. The counter output, which is a delay signal for
At the output timing of the delay circuit of FIG.

[0045]

Embodiments of the present invention will be described below. Embodiment 1 FIG. FIG. 1A is a block diagram showing a circuit configuration of a variable delay circuit according to Embodiment 1 of the present invention. 14, the same reference numerals as those in FIGS. 14 and 15 denote the same components as those of the conventional variable delay circuit 200, and reference numeral 110 denotes a variable delay circuit using the PLL control system of the first embodiment. The variable delay circuit 110 generates a first voltage-controlled oscillator (VCO) that generates a _PLL internal clock (first internal clock) CK _PLL having a predetermined cycle based on the oscillation control signal OScont.
1) Oscillator control means 110 for controlling the oscillation frequency of the first oscillator 111a by the oscillation control signal OScont based on 111a and the external clock CKo and the PLL internal clock CK _{PLL so} that the phases thereof match.
b, and has a phase-locked loop circuit 110a that synchronizes the _PLL internal clock CK _PLL with the external clock CKo and has a cycle that is a predetermined multiple thereof.

The variable delay circuit 110 receives the input signal S _in and receives an external clock based on the oscillation control signal OScont, which is the output of the oscillator control means 110b, from the input timing to the next input timing. C
A synchronous internal clock (second internal clock) CK _{SI NK} having a cycle that is a predetermined multiple of Ko and synchronized with the input signal S _in
A second voltage controlled oscillator for generating a (VCO2), counts the synchronous internal clock CK _{SI NK,} along with the time the count value reaches the set value, generates a counter output C _{ou t,} setting value And a counter 112 that can be changed by the set value control signal CDcont, and outputs the counter output C _out as a delay signal with respect to the input signal S _in .

Here, the oscillator control means 110b includes:
Oscillator control means 20 in conventional variable delay circuit 200
1a, the phase comparator 210, the charge pump circuit 2
20 and a loop filter 230. Also, the first and second oscillators 111a, 111
b has a configuration in which the start and stop of the oscillation operation can be controlled by an external signal.

FIG. 1B shows a detailed circuit configuration of the first voltage controlled oscillator (hereinafter abbreviated as a first VCO) 111a. In this example, the stage delay gate A _{2n + 1} is replaced with a NOR gate A ₀ . Here, the first and second stages
The delay control terminal of the delay gates A ₁ to A _2n n stages connected in common to the oscillation frequency adjustment input terminal 11a, connected to the output of the delay gate A _2n 2n-th stage to one input of NOR gate A _0, The output of the NOR gate A ₀ is connected to the input of the first-stage delay gate A ₁ , and the other input of the NOR gate A ₀ is connected to the reset input terminal 11b. Also,
Although the specific configuration of the second voltage-controlled oscillator (hereinafter abbreviated as “second VCO”) 111b is not shown, it is exactly the same as the first oscillator 111a. In FIG. 1, reference numeral 10a denotes an external clock terminal, 10b denotes a delay output terminal, and 11c denotes a VCO output terminal.

The first and second VCOs having such a circuit configuration
In 111a and 111b, when the signal input to the reset input terminal 11b is at H level, the oscillation output is fixed at L level and no oscillation is performed. When the signal input to the reset input terminal 11b goes low, oscillation starts at the same time. At this time, the VCOs 111a, 1
Reference numeral 11b denotes an oscillation frequency corresponding to the oscillation control signal OScont, which outputs the PLL internal clock CK _PLL and the synchronous internal clock CK _SINK .

Therefore, an L level signal is always applied to the reset input terminal 11b of the first VCO 111a, so that the VCO 111a always oscillates. From above the second reset input terminal 11b of VCO111b, as the input signal S _in as a reference of the delay time is applied, the fall timing t _in the input signal S _in, i.e. the input signal S _in the H level Oscillation is started at the moment when the level becomes L level. Further, the oscillation frequency adjusting terminals 11 of the VCOs 111a and 111b are used.
The oscillation control signal OScont, which is the output of the oscillation control means 110b, is supplied to a, so that the oscillation frequency of the two VCOs 111a and 111b is always the same. The internal clock CK _PLL for PLL, which is the output of the first VCO 111a, is connected to the n / M frequency divider 250.
A synchronous internal clock CK _SINK is the output of the second VCO111b are to be supplied to the counter 112.

The counter 112 receives the input signal S _in together with the synchronous internal clock CK _SINK and receives the input signal S in.
from the input time point t _in the _in it is configured to start counting of the clock CK _SINK. Note that this counter 11
2 is a counter 20 in the conventional variable delay circuit 200.
2 and the delay control terminal 112a
Is supplied with a set value control signal CDcont for adjusting the set value Cs of the counter, and is reset when a reset time T _cr elapses after the generation of the counter output C _out . Reference numeral 112b denotes a delay input terminal of the counter 112 to which the input signal S _in is input.

As described above, in the variable delay circuit 110, the delay time Td is generated by counting the synchronous internal clock CK _SINK by the counter 112.

Next, the operation will be described with reference to FIG.
In the variable delay circuit 110, the phase locked loop circuit 1
10a performs the same operation as that of the conventional variable delay circuit 200. That is, as shown in FIG. 2, in the state in which the external clock CKo is input to the terminal 10a, the external clock CKo and the divided clock CK _DM is input to the phase comparator 210, the phase difference between these clocks A certain phase comparison output PD is applied as an oscillation control signal OScont to the oscillation frequency adjustment input terminal 11a of the first VCO 111a via the charge pump 220 and the loop filter 230. At this time, since the signal level of the reset input terminal 11b of the VCO 111a is set to L level, the VCO 111a outputs a period T _PLL (here, T _PLL = T _O) based on the oscillation control signal OScont.
/ 10) PLL internal clock CK _PLL is output,
This is frequency-divided by n / M (here, n / M = 10) by an n / M frequency divider 250 in the subsequent stage, and the phase comparator 21
Input to 0.

Here, the phase comparator 210, the charge pump 220, the loop filter 230, and the first VCO 1
A signal feedback control system (PLL control system) for synchronizing the internal clock CK _PLL with the external clock CKo is formed by the 11a and the n / M divider 250. Until this PLL control system is stabilized, By repeating the control operation of the first VCO 111a by the phase comparison output, the internal clock CK _PLL
Is synchronized with the external clock CKo.

The oscillation control signal OScont is also applied to the oscillation frequency adjustment input terminal 11a of the second VCO 111b, similarly to the first VCO 111a. In the VCO 111b, since the input signal S _in is applied to the reset input terminal 11b, the oscillation operation is not performed while the input signal S _in is at the H level, and the signal level of the output terminal 11c is not changed. Is at the L level.

Then, at timing t _in , the input signal S
_in changes from the H level to the L level, that synchronization input trigger starts the oscillation operation at the same time into the reset input terminal 11b, the VCO output terminal 11c on the input signal S _in, strictly synchronized with the input trigger Internal clock CK _SINK
Is output. Further, the input signal S _in is output from the counter 11
2 is also applied to the delay input terminal 112b of the counter 112 at the timing t _in at which the input trigger is generated.
Starts the counting operation of the synchronous internal clock CK _SINK . This counting operation is performed based on the set value control signal CDcont input to the delay control terminal 112a of the counter 112. That the counter 112 when the count value of the synchronous internal clock CK _SINK is became set value control signal CDcont in accordance with the set value Cs (here five), the counter output C _out, the at timing t _out and outputs it as a delay signal to the input signal S _in. Incidentally, the counter 112 is set with a unique reset time Tcr, the reset time Tcr After generating the counter output is reset at elapsed time (timing t _cr). In FIG. 2, t _sr is a reset timing (rising timing) of the input signal S _in and a fixed time T _in the input trigger (falling timing of the input signal) t _in.
It is set in front of sr.

As described above, in the first embodiment, the first V
The PLL control system including the CO 111a has a second VCO 111b independent of the PLL control system in addition to the phase locked loop circuit 110a that generates the oscillation control signal OScont based on the external clock CKo.
The O111b, configured to start the oscillation operation based on the same time the oscillation control signal OScont with the application of the input signal S _in, an oscillation output of the second VCO111b, the input signal S _in synchronization is synchronized with the internal clock CK _{Since the SINK} is counted by the counter 112 and the counter output C _out is output as a delay signal for the input signal S _in , the reference point of the delay time Td (delay start timing)
Can be set as the input timing (falling timing) t _in of the input signal S _in irrelevant to the external clock CKo.

[0058] Further, the control of the second VCO111b, since carried out by the oscillation control signal OScont generated by the PLL control system, the period T _SINK synchronous internal clock CK _SINK an oscillation output of the VCO111b is, for PLL As with the internal clock CK _PLL , the period T of the external clock CKo
It becomes a fixed multiple of _O (for example, 1/10 times). This allows
Delay time Td generated by counting the synchronous internal clock CK _SINK are those relative to the period T _O of the external clock CKo, i.e. in the embodiment described above (T _O / 10) ×
It becomes 5.

[0059] Further, the counter 112, because it is capable of changing the setting value control signal CDcont the setting value Cs, the magnitude of the delay time Td, the period of the synchronization internal clock CK _SINK T _SINK (= T _O / 10) can be freely set by changing the width of the minimum unit (resolution of delay time Td).

Embodiment 2 FIG. 3 is a diagram for explaining a variable delay circuit according to the second embodiment of the present invention. The variable delay circuit according to the second embodiment has exactly the same circuit configuration as the variable delay circuit according to the first embodiment. As shown in a), as in the first embodiment, 2n delay gates A _{1 to} A _2n and one NOR gate
Consisting of gate A _0.

In the variable delay circuit according to the second embodiment, as shown in FIG. 3B, the gates are gate circuits 3a ₀ to 3a each including a plurality of semiconductor elements 2 as constituent elements.
a _2n , 3b _{0 to} 3b _2n , and the semiconductor element 2 is formed on a semiconductor substrate 1 constituting a semiconductor chip. Here, the gate circuits 3a _{0 to} 3a
_2n constitutes a semiconductor circuit 3a corresponding to the first VCO 111a, and the gate circuits 3b _{0 to} 3b _2n constitute a semiconductor circuit 3b corresponding to the second VCO 111b. The semiconductor circuit 3b is arranged on the semiconductor substrate 1 so as to be adjacent to each other.

Next, the function and effect will be described. In the first embodiment, a second VCO111b for generating a synchronous internal clock CK _SINK synchronized with the input signal S _in, the internal clock CK _PLL for PLL in synchronization with an external clock CKo
A first VCO111a that generates, by controlling the same oscillation control signal OScont, the internal clock CK for PLL the frequency of the synchronizing internal clocks CK _SINK
Match those of the _PLL, thereby the input signal S _in the external size of the delay time Td of the delayed signal to the clock CK
o in accordance with the period T ₀ .

In this case, both VCOs 111a, 111
In order for b to have the same oscillation frequency, the first
In addition, it is necessary to input the same signal to the oscillation frequency adjustment input terminal 11a of each of the VCOs 111a and 111b.
It is necessary to make the characteristics of the gates constituting each of the VCOs 111a and 111b the same.

In the second embodiment, the first VCO 111
a and the second VCO 111b
Are arranged on the semiconductor substrate 1 so that their layout patterns are adjacent to each other.
The oscillation frequency input terminals 11a of the COs 111a and 111b are located close to each other, and
The waveform of the oscillation control signal OScont input to 1b can be made close to an equal waveform. In addition, both VCOs 111
Since the semiconductor circuits 3a and 3b constituting the semiconductor circuits 3a and 3b are adjacent to each other, variations in the characteristics of the delay gates and the NOR gates in the respective semiconductor circuits in the manufacturing process can be suppressed. Properties can be made closer to equal ones.

Thus, in the second embodiment, the oscillation frequencies of the first and second VCOs 111a and 111b are
The difference between the two can be made smaller and the external clock CKo
Of the delay time Td with respect to the design value can be further reduced.

In the second embodiment, as in the first embodiment, the magnitude of the delay time Td can be set with reference to the period T _O of the external clock CKo, and the delay time can be reduced. Needless to say, the reference timing, that is, the delay start timing of the input signal can be set as the input timing t _in of the input signal S _in that is randomly input.

Embodiment 3 FIG. 4 is a diagram for explaining a variable delay circuit according to Embodiment 3 of the present invention. The variable delay circuit according to the third embodiment has exactly the same circuit configuration as the variable delay circuit according to the first embodiment. Also, the first and second VCOs 111a, 11a
1b is similar to that of Figure 4 embodiment, as shown in (a) 1, are composed of 2n number of delay gates A ₁ to A _2n and one NOR gate A ₀ Prefecture, these gates A ₀ ~ A
_2n are connected in a loop. Further, as shown in FIG. 4 (b), it is composed of the gate A ₀ to A _2n gate circuit 3a for each of the components of the plurality of semiconductor elements 2 ₀ to 3 A _2n constituting the first VCO111a each respective gates a ₀ to a _2n constituting the second VCO111b, are composed of a gate circuit 3b ₀ ~3b _2n to components a plurality of semiconductor elements 2, the semiconductor element 2
Are formed on a semiconductor substrate 1 constituting a semiconductor chip.

In the fourth embodiment, the first V
Gate circuits 3a _{0 to} 3a constituting CO 111a
And _2n, and each gate circuit 3b ₀ ~3b _2n constituting the second of VCO111b, arranged alternately and in a row between the high-potential power supply line 6a and the low potential power supply line 6b on the semiconductor substrate 1 Have been.

Next, the function and effect will be described. Also in the third embodiment, the first and second VCOs 111a, 1
As described above, the same signal is input to the oscillation frequency adjustment input terminal 11a of each VCO and each of the VCOs 111a and 111b has the same oscillation frequency.
It can be said that it is necessary to make the characteristics of the gates constituting b the same.

In the third embodiment, the gate circuits 3a _{0 to} 3a _2n constituting the VCO 111a and the VCO 111b
And a gate circuit 3b ₀ ~3b _2n constituting the, since the arranged alternately on the semiconductor substrate 1, each VCO111
Since the oscillation frequency adjustment input terminals 11a of the VCOs 111a and 111b are located close to each other, the waveform of the oscillation control signal OScont input to each of the VCOs 111a and 111b can be made closer to the same one.

Since the gate circuits of the two VCOs 111a and 111b are located adjacent to each other, the influence of process variations in the manufacturing process on the characteristics of these gate circuits will be described.
The gate circuit characteristics can be made substantially equal between the two VCOs, with almost no difference between the VCOs 11a and 111b.

Further, in the third embodiment, both VCOs
Since the gates 111a and 111b are arranged in a line, the same power supply lines 6a and 6
b, power can be supplied, and the operation of each gate can be made almost the same.

As a result, in the third embodiment, both VCs
O111a, the error of the oscillation frequency of between 111b becomes very small, is generated in the variable delay circuit, a delay time Td relative to the period T _O of the external clock CKo,
It can be set to a value almost as designed.

Embodiment 4 FIG. 5A is a block diagram showing a circuit configuration of a variable delay circuit according to Embodiment 4 of the present invention. 16, the same reference numerals as those in FIG. 16 denote the same elements as those in the conventional variable delay circuit 300, and reference numeral 140 denotes a variable delay circuit using the DLL control system of the fourth embodiment. The variable delay circuit 140 delays the external clock CKo for a predetermined time based on the delay time control signal DTcont by a first voltage control delay circuit (hereinafter abbreviated as a first VCDL) 141a and an external clock CKo. The first V
The delay time control signal DFD receives the delay feedback output D _{FD of the} CDL 141a so that their phases match.
Tcont includes delay circuit control means 140b for controlling the first VCDL 141a.
1a, a delay-locked loop circuit 1 for synchronizing the delayed feedback output D _FD with the external clock CKo.
40a.

The variable delay circuit 140 delays the input signal S _in based on a delay time control signal DTcont output from the delay circuit control means 140b. Abbreviated as VCDL.)
141b, and the output D of the second VCDL 141b.
The O has a configuration for outputting a delayed signal with respect to the input signal S _in.

Here, the delay circuit control means 140b
Comprises a phase comparator 310, a charge pump 320, and a loop filter 330, like the delay circuit control means 300b in the conventional variable delay circuit 300.

The above VCDLs 141a and 141b
Has the same circuit configuration as the conventional VCDL 340, as shown in FIG. That is, the above VCDL
141a and 141b are K-stage delay gates B ₁ , B ₂ , B ₃ ,... Connected in series and whose gate delay time can be adjusted by a delay time control signal DTcont.
And B _K, and a selector 340a for selecting and outputting the number of delay stages control signal DScont1, DScont2 input signal of the delay gate of each stage. Delay time adjustment terminal of the delay gate B ₁ .about.B _K of each stage are connected in common and a gate delay adjustment terminal 14a, the terminal 14a
, The delay time control signal DTcont is applied. For convenience of explanation, the fourth embodiment
Then, the external clock C of each VCDL 141a, 141b
Ko, the delay input terminal to which an input signal S _in is input 14
b to the delay feedback terminal from which the delay feedback output D _FD is output, and 14 c to the delay stage number control signal DS.
14 is connected to the delay control terminal to which cont1 and DScont2 are input.
d, and 14 e is assigned to the delay output terminal from which the selector output Se is output. In the circuit block shown in FIG. 5, the first and second voltage controlled oscillators 141a, 141a
b is denoted by VCDL1 and VCDL2.

Next, the operation will be described. The delay locked loop circuit 140a of the variable delay circuit 140 is the same as the delay locked loop circuit 30 of the conventional variable delay circuit 300.
It operates exactly the same as 0a.

That is, in the variable delay circuit 140,
In a state where the DLL control system stable, and generate a clock that is delayed one period relative to the external clock CKo in the delay locked loop circuit 140a as the delayed feedback output D _FB. That is, in the state where the DLL control system is stable, the phase comparison between the external clock CKo and the internal clock (delayed feedback signal) D _FD is performed by the phase comparator 310, the phase comparison output PD charge pump 320
Is converted to a voltage V _PD , and this output voltage V _PD is further transmitted through a loop filter 330 to a delay time control signal DTcont.
As the gate delay adjustment terminal 1 of the first VCDL 141a
4a.

[0080] In the first VCDL141a, unit delay time tpd of the delay gates based on the delay time control signal DTcont is adjusted, the internal clock DG _k delayed by a total time of the unit delay time is the delay feedback output Generated as _DFB . At this time, the external clock CKo is supplied from the delay gates B _{1 to} B _k of the respective stages at times TD ₁ to TD _k (TD _{k), respectively.}
= Tpd × k) delayed internal clocks DG ₁ to
DG _k is output. Then, the internal clock DG _k serving as the delay feedback output D _FD is inputted with an external clock CKo to the phase comparator 310, wherein the phase comparison of these clocks is performed.

[0081] Then, until the DLL control system is stabilized, that is by repeating this operation until the phase of the phase and the internal clock DG _k of the external clock CKo matches, the delay feedback terminal 14c of the VCDL141a, said 1 for the external clock CKo
Period T _O partial delayed by the delay feedback output D _FD so that the are output.

At this time, the delay time control signal DTcont is supplied to the second delay circuit 141b.
Unit delay time tpd of the respective delay gates B ₁ .about.B _k in the delay circuit 141b are set at all the same as the first delay circuit 141a. In this state, when an input signal S _{in serving as} a reference for the delay time is input to the delay input terminal 14b of the second delay circuit 141b, the input signal S _in is applied to each of the delay gates B ₁ to B ₁ of the delay circuit 141b. In B _{k, the} signals are sequentially delayed by the unit delay time tpd. Then, the selector 340a, (output DG ₃ of the delay gate B ₃ at the third stage in this example) the output of the delay gate of stages corresponding to the number of delay stages control signal DScont2 is selected,
From the selector 340a, the gate output DG ₃ (selector output Se ₂₎ is output to the delayed output terminal 14e as the delayed output DO to the input signal S _in.

[0083] At this time resulting delay time Td, that is, the time from the rising timing t _in the input signal S _in to the rising timing t _out of the selector output Se ₂ is the third stage in the first delay circuit 141a It is equal to the delay time TD ₃ outputs DG ₃ of the delay gate B _3.

As described above, in the fourth embodiment, the first V
The DLL control system including the CDL141a, in addition to the delay locked loop circuit 140a for generating a delay time control signal DTcont based on the external clock CKo, and the DLL control system independent, second delaying an input signal S _in VC
Since the second VCDL 141b is controlled by the delay time control signal DTcont, the reference point (delay start timing) of the delay time Td is provided.
Can be set as the input timing (falling timing) t _in of the input signal S _in irrelevant to the external clock CKo, and in the second VCDL 141b, the period T of the external clock CKo is determined by the delay time control signal DTcont.
A delay time Td based on _O can be generated.

Further, the VCDL 141b is connected to a plurality of series-connected delay gates B _{1 to} B _k each capable of controlling a gate delay time, and the output DG ₁ of each stage delay gate.
To DG _k with the selector 340a for selecting the number of delay stages by the delay stage number control signal DScont.
By selecting desired ones of the output signals DG ₁ ~DG _k of each delay gate, it is possible to adjust the delay time Td of the delay time tpd per gate one stage as a unit.

Embodiment 5 FIG. 7A is a block diagram showing an overall configuration of a variable delay circuit according to a fifth embodiment of the present invention, and FIG. 7B is a diagram showing a detailed configuration thereof.

In the figure, reference numeral 150 denotes a variable delay circuit comprising first and second variable delay circuit sections 150a and 150b, and the first variable delay circuit section 150a is identical to the variable delay circuit 110 of the first embodiment. The second variable delay circuit unit 150b is the same as the variable delay circuit 14 of the second embodiment.
The circuit configuration is exactly the same as 0.

The variable delay circuit 150 has the first
Is connected to the delay input terminal 14b of the second variable delay circuit section 150b, and the second VCO 1 of the first variable delay circuit section 150a is connected to the delay input terminal 14b of the second variable delay circuit section 150b.
The output terminal 11c of the second variable delay circuit unit 150
b, and outputs the output of the second VCDL 141b in the variable delay circuit section 150b as a final delay signal DO ₂ which is a further delay of the counter output C _out which is a delay signal for the input signal S _in . It is configured to output.

Next, the operation will be described with reference to FIG.
In the following description, as in the first embodiment, and the internal clock CK _PLL, the period T _PLL of CK _SINK, and T _SINK are both 1/10 times the period T _O of the external clock CKo, counter 112 Is 5, the second VC
The output of the delay gate selector 340a of DL141b is selected, the output DG ₃ of a three-stage, also the input signal S _in is its falling timing t _in is in the input trigger.

First, the first variable delay circuit section 150a
Performs the same operation as the variable delay circuit 110 of the first embodiment based on the external clock CKo and the input signal S _in . That is, in the phase-locked loop circuit 110a, receives the divided clock CK _DM derived by dividing the output of the external clock CKo and first VCO111a, the PLL control system, the first internal clock CK _PLL output a PLL of VCO111a Is made to coincide with the phase of the external clock CKo. In this state, when the input signal S _in is applied to the delay input terminal 11b of the first variable delay circuit unit 150a (timing t _in ), at the same time, the second VCO 1
11b is a synchronous internal clock CK synchronized with the input signal S _{in
At the same time as} the generation of _SINK is started, the counter 112 starts counting the synchronous internal clock CK _SINK . The oscillation operation of the clock synchronized with the input signal S _in in the second VCO 111b continues until the next input signal S _in reset timing (rising timing immediately before falling timing) t _sr .

When the count value of the counter 112 reaches the set value Cs of 5, the counter output C
_out (timing t _co ). First delay time Td ₁ is a result is generated as the time t _co of the fall timing t _in the input signal S _in to the rising timing of the counter output C _{ou t.}

At this time, the input terminal 41 of the second variable delay circuit section 150b is connected to the second VCO 11
Synchronous internal clock CK _SINK an oscillation output of 1b is applied, delayed input terminal 14 of the second VCDL141b
b, the above-mentioned counter output C _out is applied, and the variable delay circuit unit 150b outputs the synchronous internal clock CK _{SI NK}
Embodiment 4 based on the above and the counter output C _out
Performs the same operation as the variable delay circuit 140 of FIG. That is, the delay lock loop circuit 140 of the variable delay circuit unit 150b
In a, the output D of the first delayed feedback output D _FB (i.e. delay gates B _K in the final stage of VCDL141a
Delay time TD _K of G _K) is, synchronous internal clock CK _SINK
The period T _SINK content as the delay time control signal DTcont
Controls the first VCDL 141a.

The counter output C _out is the second
Is input to the delay input terminal 14b of the VCDL 141b, the counter output C _out is input to the input timing t _CO
Signal delayed by a delay time TD ₃ of three stages of delay gates from the delayed output terminal 14 (i.e. the output DG ₃ of the delay gate B ₃ of the third stage selected by the selector 340a)
e to output a final delay signal DO ₂ .

Here, the second VCDL 141b is
The first same delay time control signal DTcont and VCDL141a, is adjusted the delay time of the delay gates in each stage, and therefore, counter output C _out from occurring, the final delay signal DO ₂ is generated The second delay time Td _{2 up to this} is 3 / k times the period T _SINK of the synchronous internal clock CK _SINK .

As a result, in the variable delay circuit 150, the total delay time Td generated for the input signal S _in
Is the delay time Td ₁ in the first variable delay circuit section 150a.
And the delay time Td _{2 in} the second variable delay circuit section 150b.

As described above, in the fifth embodiment, since the configurations of the variable delay circuits 110 and 140 of the first and fourth embodiments are combined, similar to the first and fourth embodiments, the magnitude of the delay time Td can be reduced. Is the period T of the external clock CKo
_O can be set as a reference, and in addition to the effect that the reference timing of the delay time generation can be set as the input timing t _in of the input signal S _in input at random, the following effects can be obtained. There is.

That is, in the first variable delay circuit section 150a using the PLL control system, the cycle T of the external clock CKo is
_A predetermined number of synchronous internal clocks CK _SINK having a period T _SINK which is n / M times (specifically, 1/10 times) of _O are counted, and a constant multiple (specifically, 5 times) of the period T _SINK is counted. In the second variable delay circuit unit 150b that generates the delay time Td ₁ and further uses the DLL control system, the unit delay time is 1 / k times the period T _SINK of the synchronous internal clock CK _SINK (that is, the delay time of each delay gate). The delay time Td ₂ that is a constant multiple (specifically, three times) the delay time Td ₂ is generated.

Therefore, the first variable delay circuit section 150a
In this case, the resolution of the delay time Td is set to 1 / (n / M) of the period T _O of the external clock CKo, and the second variable delay circuit unit 1501b further sets the resolution of the delay time Td to 1 / k of that ( That is, T _o / k (n / M)), and eventually, the variable delay circuit 150
With the resolution of d as the time width T _O / k (n / M), there is an effect that the delay time can be finely set to a value of about the maximum external clock cycle T _{O using the} time width as a minimum unit.

In the fifth embodiment, the synchronous internal clock CK _SINK in the first variable delay circuit 150a is used _.
Is connected to the external clock terminal 4 of the second variable delay circuit 150b.
1, the internal clock CK _PLL for the PLL in the first variable delay circuit unit 150a may be supplied to the external clock terminal 41. Similar effects can be obtained.

Embodiment 6 FIG. FIG. 9A is a block diagram showing an overall configuration of a variable delay circuit according to Embodiment 6 of the present invention, and FIG. 9B is a diagram showing a detailed configuration thereof.

In the figure, the same reference numerals as those in FIGS. 1 and 5 denote the same parts as in the first and fourth embodiments,
Is the variable delay circuit 110 of the first embodiment.
An additional variable delay circuit 160a is connected between the second VCO 111b and the counter 112, and delays the output of the second VCO 111b and supplies the output to the counter 112. Has exactly the same circuit configuration as the variable delay circuit 140 of the fourth embodiment.

In the variable delay circuit 160, the output terminal 11c of the second VCO 111b is connected to the external clock terminal 41 of the auxiliary variable delay circuit 160a and the delay input terminal 14b of the second VCDL 141b. The delay output terminal 14e of the VCDL 141b is connected to the clock input terminal of the counter 112 to connect the second V
The output of the CDL 141b is supplied to the counter 112.

Next, the operation will be described with reference to FIG. In the following description, the internal clocks CK _PLL and C
K _SINK period T _PLL, T _{SI NK,} set value Cs of the counter 112, the output of the delay gate selector 340a of the second VCDL141b is selected, the same as the fifth embodiment, also the input signal S _in its Fall timing t _in
Is an input trigger.

In the variable delay circuit 160 of this embodiment, the phase lock loop circuit 110a and the second VCO 1
11b performs exactly the same operation as that of the first embodiment. When the input signal S _in is input (timing t _in ), the second VCO 111b synchronizes with the input signal S _in and outputs an external clock. initiating the generation of a synchronous internal clock CK _SINK with 1/10 of the period T _SINK period T _O of CKo. At this time, the counter 112 also starts counting the input clock.

Thus, the additional variable delay circuit section 160a
The external clock terminal 41 and the delay input terminal 14b of the second VCDL 141b are connected to the synchronous internal clock CK.
_SINK is supplied, and this additional variable delay circuit section 160a
The same operation as that of the variable delay circuit 140 of the fourth embodiment is performed based on the synchronous internal clock CK _SINK . That is, in the delay locked loop circuit 140a of the additional variable delay circuit section 160a, the first VCDL141a, the delay time TD _K (output DG _K of delay gates B _K of words final stage) the delayed feedback output D _FD , so that the period T _SINK partial synchronization internal clock CK _SINK, controlled by the delay time control signal DTcont.

[0106] Further, the in the second VCDL141b, as in the first VCDL141a, the delay time control signals DTcont, the delay time TD _K output DG _K of delay gates B _K of the final stage, synchronous internal clock CK
So that the period T _SINK fraction of _SINK, set the delay time of the delay gates in each stage, the further the selector 340a, the output DG ₃ of the delay gate B ₃ of the third stage is selected, as this is the selector output Se Delay output terminal 14e
Is output to Here, the selector output Se is the second
Since in the output DG ₃ of the delay gate B ₃ of the third stage in VCDL141b, the synchronous internal clock CK _SINK
The delay time TDe (Td ₂ ) with respect to the period T _SINK
3 / k times of

[0107] Then, in the counter 112, because it starts counting at the input timing t _in the input signal S _in, will be immediately counted delayed clock is the selector output Se, the count value is When the set value Cs reaches 5, a counter output C _out is generated (timing t _CO ). As a result, the further delay time Td ₁ is increased from the time when the selector output Se for the input signal S _in is generated (timing t _se ) to the counter output C
It is generated as the time until the rising timing t _{CO of out} .

[0108] Consequently, also in this variable delay circuit 160, the delay time Td of the total generated with respect to the input signal S _in the delay time by adding the variable delay circuit section 160a T
This is the sum of d ₂ and the delay time Td ₁ due to the main part of the variable delay circuit 160.

As described above, also in the sixth embodiment, as in the fifth embodiment, the magnitude of the delay time Td can be set with reference to the period T _O of the external clock CKo, and the delay time can be reduced. the timing to be a reference, together with the effect that it is possible to input timing t _in the input signal S _in input to the random, the resolution of the delay time Td as the time width _{T O / k (n / M} ), the time With the width as the minimum unit, there is an effect that the delay time can be set finely to a size of about the period T _O of the external clock.

In the sixth embodiment, the input signal S _in
The synchronous internal clock CK _{SI NK} synchronized with the second VCD
The control of the selectors 340a by the delay stage number control signal DScont ₂ in L141b, in units of time width of 1 / k of the period T _SINK of the synchronous internal clock CK _SINK,
There is also an effect that it can be delayed by an arbitrary time.

Further, according to the sixth embodiment, a delayed output with respect to an input signal is finally obtained as a counter output. Time has a small variation.

In the sixth embodiment, the additional variable delay circuit section 160a is replaced with the variable delay circuit 140 of the fourth embodiment.
However, the additional variable delay circuit 160a may have the configuration of the variable delay circuit 300 using the conventional DLL control system shown in FIG. The output terminal 11c of the VCO 111b is connected to the external clock terminals 30a and A of the variable delay circuit 300.
The input terminal 31 of the ND gate 301 is connected, and the delay output terminal 32 of the AND gate 301 is connected to the clock input terminal of the counter 112 so that the output of the AND gate 301 is supplied to the counter.

Embodiment 7 FIG. FIG. 11A is a block diagram showing an overall configuration of a variable delay circuit according to Embodiment 7 of the present invention, and FIG. 11B is a diagram showing a detailed configuration thereof.

In the figure, the same reference numerals as those in FIGS. 1 and 5 denote the same parts as in the first and fourth embodiments.
In the variable delay circuit 110 according to the first embodiment,
An additional variable delay circuit unit 170a for delaying the second is the output of VCO111b synchronous internal clock CK _SINK,
And a D flip-flop 171 which receives an output of the additional variable delay circuit 170a and the counter output C _out as inputs.
Has exactly the same circuit configuration as the variable delay circuit 140 of the fourth embodiment.

In the variable delay circuit 170, the output terminal 10b of the variable delay circuit 110 is connected to the D flip-flop 171
Connected to the D input terminal 171a of the
The output terminal 14e of the second VCDL 141b of
Connected to the T input terminal 171b of the flip-flop 171 and the Q output terminal 171c of the D flip-flop 171
Is an output terminal of the delay signal. The D flip-flop 171, as shown in FIG. 12 (b), the rising timing t ₁ ~t ₅ clock pulses applied to the T input terminal 171b, D input terminal 171a
Is configured to be the output level of the Q output terminal 171c.

Next, the operation will be described. In the following description, the period T of the internal clocks CK _PLL and CK _SINK
PLL , T _{SI NK} , set value Cs of counter 112, second V
The output Se of the delay gate selector 340a selects the CDL141b is set equal to the fifth embodiment, also the input signal S _in is its falling timing t _in is in the input trigger.

In the variable delay circuit 170 of this embodiment, the phase locked loop circuit 110a and the second VC
The O111b performs exactly the same operation as in the first embodiment, and the second VCO 111b outputs the input signal S _in
Is input (timing t _in ), the input signal S _in
In synchronization to and the period T _O of the external clock CKo 1/1
Start the occurrence of synchronous internal clock CK _SINK having a period T _SINK 0, the counter 112 starts the count operation of the synchronous internal clock CK _SINK.

When the counter value reaches the set value Cs of 5, the counter 112 outputs a counter output C.
_out (timing t _CO ). First delay time Td ₁ is a result is generated as the time from the fall timing t _in the input signal S _in to the rising timing t _CO of the counter output C _{ou t.}

At this time, the external clock terminal 41 of the additional variable delay circuit 170a and the delay input terminal 14b of the second VCDL 141b are connected to the synchronous internal clock CK _SINK
The additional variable delay circuit 170a performs the same operation as the variable delay circuit 140 of the fourth embodiment based on the synchronous internal clock CK _SINK . That is,
In the delay locked loop circuit 140a of the additional variable delay circuit section 170a, the first VCDL141a, the delay time TD _K of the delayed feedback output D _FD (i.e. output DG _K of delay gates B _K of the final stage) is synchronized so that the period T _SINK of the internal clock CK _SINK, controlled by the delay time control signal DTcont.

Further, the second VCDL 141b also has a delay time control signal D like the first VCDL 141a.
The Tcont, the output DG of the delay gates B _K of the last stage
The delay time TD _K of _K is such that the period T _SINK partial synchronization internal clock CK _SINK, the delay time of the delay gates in each stage is set, further by that selector 340a, the delay gates B ₃ of the third-stage output DG ₃ is selected, which is output to the delay output terminal 14e as the selector output Se _2. Here, this selector output Se ₂ is supplied to the _second VCD
Output DG of the delay gate B ₃ of the third stage in L141b
Because it is _3, the delay time TDe for the synchronous internal clock CK _SINK has a 3 / k times the period T _SINK.

The counter output C _out is supplied to the D input terminal 171a of the flip-flop 171. The delay output DO of the additional variable delay circuit 170a, which is the selector output Se, is supplied to the T input terminal 171b of the flip-flop 171. Is done. This D flip-flop 171
Is the rise timing of the clock applied to T input terminal, the input level applied to the D input terminal, which is configured to be the output level of the Q output terminal, the counter output C _out of the generation timing t _At the first rising timing t _se of the delay synchronous internal clock which is the selector output Se after _CO , the flip-flop 1
The 71 of the Q output terminal 171c, the final delayed output DO ₂ is output.

As a result, also in the present variable delay circuit 170, the total delay time Td generated with respect to the input signal S _in is determined by the delay time Td ₁ of the main part of the variable delay circuit 170 and the additional variable delay circuit 170a. Delay time T
d ₂ .

As described above, in the seventh embodiment, similarly to the sixth embodiment, the input timing of the input signal S _in which is set with reference to the period T _O of the external clock CKo and is randomly input is determined as the generation start point. Delay time Td
Are obtained, and the following effect is obtained in addition to the effect that the delay time can be set finely with the resolution of the delay time Td as the time width T _O / k (n / M).

That is, the first delay time Td ₁ is adjusted by adjusting the set value Cs of the counter 112 so that the synchronous internal clock C
The period T _SINK of K _SINK it is possible to arbitrarily set as a variable unit, by changing the delay gates selected by the selector 340a in the second VCDL141b additional variable delay circuit section 170a, a second delay time Td ₂ can be set more finely with the delay time of one delay gate (that is, 1 / k times the period T _SINK ) as a variable unit.

The counter output C _out for determining the _first delay period Td ₁ is supplied to the D flip-flop 171, and the flip-flop 171 outputs a second delay time Td _{2 with} respect to the synchronous internal clock CK _SINK . Since the level of the counter output C _out at the rising timing t _se of the delayed selector output Se is output, the total time Td (= Td ₁ + T) of the first and second delay times is output.
d ₂ ) is the counter output C where some variation is expected
Regardless of _out , it is determined by the synchronous internal clock CK _SINK . Therefore, the total delay time Td
There is also an effect that the precision of the image can be improved.

In the seventh embodiment, the additional variable delay circuit 170a is replaced with the variable delay circuit 140 in the fourth embodiment.
However, the additional variable delay circuit 170a may use the configuration of the variable delay circuit 300 using the conventional DLL control system shown in FIG. The output terminal 11c of the VCO 111b is connected to the external clock terminals 30a and A of the variable delay circuit 300.
The input terminal 31 of the ND gate 301 is connected, and the delay output terminal 32 of the AND gate 301 is connected to the T input terminal 171b of the flip-flop 171b.

[0127]

As described above, according to the variable delay circuit of the present invention (claim 1), the variable delay circuit has the first oscillator constituting the phase locked loop (PLL) control system, and the oscillator is connected to the PLL.
The first internal clock, which is an oscillation output, is controlled by an oscillation control signal generated by the control system, and the divided clock is synchronized with the external clock and has a cycle that is a predetermined multiple of the external clock. In addition to the phase lock loop circuit, the PLL includes a second oscillator that generates a second internal clock synchronized with the input signal based on the oscillation control signal.
Since the output of the counter for counting the second internal clock is output as a delay signal with respect to the input signal, the internal clock counting by the counter is started based on the input signal. And the second counted by the counter.
The cycle of the internal clock is based on the cycle of the external clock by the oscillation control signal. Thereby, the magnitude of the delay time can be set based on the cycle of the external clock. In addition, the delay start timing of the input signal, that is, the reference timing of the delay time generation is set to the input timing of the randomly input input signal. There is an effect that can be.

In the above counter, the set value can be changed by the set value control signal.
There is also an effect that the size of the delay time can be set freely.

According to the present invention (claim 2), in the variable delay circuit according to claim 1, the semiconductor circuit forming the first oscillator and the semiconductor circuit forming the second oscillator are different from each other. Since the oscillators are arranged adjacent to each other on the substrate, the waveform of the oscillation control signal input to each oscillator can be made as equal as possible in terms of the layout of the oscillator. Further, since the semiconductor circuits forming both oscillators are adjacent to each other, it is possible to suppress the variation in the characteristics of the semiconductor elements forming each semiconductor circuit in the manufacturing process. This has the effect of reducing the difference between the oscillation frequencies of the first and second oscillators and reducing the deviation of the delay time based on the period of the external clock from the design value.

According to the present invention (Claim 3), Claim 1
In the variable delay circuit described above, a plurality of gate circuits constituting the first oscillator and a plurality of gate circuits constituting the second oscillator are alternately arranged on a semiconductor substrate. The waveform of the input oscillation control signal is
The layout of the oscillators can be made almost equal, and the variation in the characteristics of the gate circuits that constitute both oscillators due to the manufacturing process is almost eliminated between the two oscillators. Can be small.

As a result, the difference between the oscillation frequencies of the two oscillators is made very small, and the deviation of the delay time from the design value with respect to the period of the external clock can be further reduced.

According to the variable delay circuit of the present invention (claim 4), there is provided the first delay circuit constituting the delay lock loop (DLL) control system, and the delay circuit is generated by the DLL control system. In addition to a delay lock loop circuit controlled by a delay time control signal to make its delay output synchronized with an external clock, a second delay circuit for delaying an input signal by a predetermined time based on the delay time control signal is provided. , The DLL above
Since the input signal is provided independently of the control system, the input signal is directly delayed by the second delay circuit, and the magnitude of the delay time in the second delay circuit is controlled by the delay time control signal. This is based on the clock cycle. Thus, the magnitude of the delay time can be set with reference to the cycle of the external clock, and the reference timing of the delay time can be set as the input timing of the input signal input independently of the external clock. effective.

Since the second delay circuit has a plurality of delay gates connected in series, the number of delay gate stages for delaying an input signal can be set by a delay stage number control signal. Also, there is an effect that the magnitude of the delay time can be freely set.

According to the present invention (claim 5), claim 1
In the variable delay circuit described above, a delay locked loop (DL
L) a first delay circuit constituting a control system, the delay circuit being controlled by a delay time control signal generated by the DLL control system, and the delay output being converted to the first or second internal clock; A second delay circuit for delaying the counter output by a predetermined time based on the delay time control signal.
Since it is provided independently of the LL control system, the magnitude of the delay time can be set based on the period of the external clock, and the delay start timing of the input signal can be set at the input of the input signal which is randomly input. In addition to the effect of being able to be a timing, the delay time is generated by a two-stage delay processing for the input signal, and the resolution of the delay time for the input signal is increased, and the delay time is reduced.
From the minimum delay time limited by the resolution to the maximum,
There is an effect that it is possible to set finely over a range up to about the cycle of the external clock.

According to the present invention (claim 6), claim 1
In the variable delay circuit described above, a delay locked loop (DL
L) A delay lock having a first delay circuit constituting a control system, wherein the first delay circuit is controlled by a delay time control signal generated by a DLL control system, and a delay output thereof is synchronized with an external clock. An additional variable delay circuit unit having a loop circuit and a second delay circuit independent of the DLL control system, which delays the second internal clock for a predetermined time based on the delay time control signal; Since the output of the circuit unit is counted by the counter, the magnitude of the delay time can be set based on the cycle of the external clock, and the delay start timing of the input signal is
In addition to the effect that the input timing of the input signal that is randomly input can be set, the delay time is generated by the two-stage delay processing for the input signal as described above, and the resolution of the delay time for the input signal can be improved. There is an effect that the delay time can be set finely by increasing the delay time.

According to the present invention (claim 7), claim 1
In the variable delay circuit described above, a delay locked loop (DL
L) A delay lock having a first delay circuit constituting a control system, wherein the first delay circuit is controlled by a delay time control signal generated by a DLL control system, and a delay output thereof is synchronized with an external clock. A loop circuit, and delaying the second internal clock for a predetermined time based on the delay time control signal;
Since an additional variable delay circuit having a second delay circuit independent of the DLL control system is provided, the magnitude of the delay time can be set based on the cycle of the external clock.
In addition, in addition to the effect that the delay start timing of the input signal can be set to the input timing of the input signal that is randomly input, the delay time is generated by the two-stage delay processing for the input signal as described above. Thus, there is an effect that the resolution of the delay time with respect to the input signal is increased and the delay time can be set finely.

Further, the output of the additional variable delay circuit, that is, the delayed version of the second internal clock, and the counter output based on the cycle of the second internal clock are input, and the counter output is used as the counter output. Since the flip-flop that outputs the final delay signal at the timing of the output of the additional variable delay circuit after the generation timing is provided, the total delay time in the second-stage delay processing is independent of the counter output with variation. , The second
Is determined by the cycle of the internal clock, and therefore, there is an effect that the accuracy of the total delay time can be improved.

[Brief description of the drawings]

FIG. 1 shows the overall configuration of a variable delay circuit according to a first embodiment of the present invention (FIG. 1A) and the configuration of its VCO (FIG. 1B).
FIG.

FIG. 2 is a diagram showing a timing chart of the variable delay circuit according to the first embodiment.

3A and 3B are a circuit diagram (FIG. 3A) and a plan view (FIG. 3B) showing a pattern layout of a variable delay circuit according to a second embodiment of the present invention.

FIGS. 4A and 4B are a circuit diagram (FIG. 4A) and a plan view (FIG. 4B) showing a pattern layout of a variable delay circuit according to a third embodiment of the present invention.

FIG. 5 is a diagram showing the overall configuration of a variable delay circuit according to a fourth embodiment of the present invention (FIG. 5A) and its VCDL configuration (FIG. 5B).

FIG. 6 is a diagram showing a timing chart of the variable delay circuit according to the fourth embodiment.

FIG. 7 is a diagram showing a schematic configuration (FIG. 7A) and a specific circuit configuration (FIG. 7B) of a variable delay circuit according to a fifth embodiment of the present invention.

FIG. 8 is a diagram showing a timing chart of the variable delay circuit according to the fifth embodiment.

FIG. 9 is a diagram showing a schematic configuration (FIG. 9A) and a specific circuit configuration (FIG. 9B) of a variable delay circuit according to a sixth embodiment of the present invention.

FIG. 10 is a diagram showing a timing chart of the variable delay circuit according to the sixth embodiment.

FIG. 11 is a schematic configuration (FIG. 11 (a)) and a specific circuit configuration (FIG. 10 (b)) of a variable delay circuit according to a seventh embodiment of the present invention.
FIG.

12 is a diagram showing a timing chart of the variable delay circuit according to the seventh embodiment (FIG. 12A) and a timing chart of the flip-flop thereof (FIG. 12B).

FIG. 13 is a diagram showing a configuration of a conventional delay circuit including a delay gate (FIG. 13A), a timing chart thereof (FIG. 13B), and an application example thereof (FIG. 13C).

FIG. 14 is a schematic configuration of a conventional variable delay circuit using a PLL control system (FIG. 14A) and a timing chart (FIG. 14B).
FIG.

FIG. 15 is a block diagram of the variable delay circuit (FIG. 15A)
) And the configuration of the VCO used for this (FIG. 3B).

FIG. 16 is a block diagram of a variable delay circuit using a conventional DLL control system (FIG. 16A) and a VCDL used for the same;
(B) of FIG.

17 is a diagram showing a timing chart of the variable delay circuit shown in FIG.

[Explanation of symbols]

10a external clock terminal, 10b, 14e delay output terminal, 11a oscillation frequency adjustment input terminal, 11b reset input terminal, 11c VCO output terminal, 14a gate delay adjustment terminal, 14b, 112b delay input terminal, 1
4c Delay feedback terminal, 14d, 112a Delay control terminal, 110, 140, 150, 160, 170
Variable delay circuit, 110a phase locked loop circuit, 1
10b oscillator control means, 111a, 111b first,
Second voltage controlled oscillator (VCO1, VCO2), 112
Counter, 140a delay lock loop circuit, 140
b delay circuit control means, 141a, 141b first and second voltage control delay circuits (VCDL1, VCDL2), 1
50a, 150b First and second variable delay circuits, 16
0a, 170a Additional variable delay circuit unit, 171 D flip-flop, 171a D input terminal, 171b T input terminal, 171c Q input terminal, 210, 310 phase comparator, 220, 320 charge pump, 230, 3
30 loop filter, 340a selector, A ₀ N
OR gate, A _{1 to} A _2n , B _{1 to} B _k delay gates, C
_out counter output, CDcont set value control signal, CK
o External clock, CK _PLL PLL internal clock,
CK _SINK synchronous internal clock, D _FB delayed feedback output, DTcont delay time control signals, DScont delay stages control signal, DO, DO ₂ delayed output, OScont oscillation control signal, PD phase comparison output, S _in the input signal.

Claims (7)

[Claims] 1. A method according to claim 1, further comprising the step of:
A first oscillator for generating an internal clock, and an oscillation frequency of the first oscillator based on the external clock and the frequency-divided clock of the first internal clock, the oscillation control signal being used to make the phases coincide. A phase locked loop circuit having oscillator control means for controlling the first internal clock, wherein the first internal clock has a frequency-divided clock that is synchronized with the external clock and has a cycle that is a predetermined multiple of the external clock; A second signal synchronized with the input signal, having a period twice as long as the external clock based on the oscillation control signal output from the oscillator control means during a period from the input timing to the next input timing. A second oscillator for generating an internal clock; counting the second internal clock; and generating a counter output when the count value reaches a set value. To with, the variable delay circuit, characterized in that a changeable counter by setting value control signal set value, outputs the counter output as a delay signal to the input signal. 2. The variable delay circuit according to claim 1, wherein each of the first and second oscillators comprises a semiconductor circuit having a plurality of semiconductor elements formed on a semiconductor substrate as constituent elements. A variable delay circuit, wherein a semiconductor circuit forming the first oscillator and a semiconductor circuit forming the second oscillator are arranged adjacent to each other on the semiconductor substrate. 3. The variable delay circuit according to claim 1, wherein each of the first and second oscillators includes a plurality of loop-connected gate circuits each including a semiconductor element formed on a semiconductor substrate as a constituent element. A plurality of gate circuits constituting the first oscillator; and a second gate circuit constituting the second oscillator.
A plurality of gate circuits constituting said oscillator are alternately arranged on said semiconductor substrate. 4. A first delay circuit having a plurality of stages of delay gates connected in series and delaying an external clock for a predetermined time based on a delay time control signal for setting a delay time of each stage delay gate. Delay circuit control means for receiving the external clock and the output of the first delay circuit, and controlling the delay time of each delay gate in the first delay circuit by the delay time control signal so that their phases match. A delay lock loop circuit that synchronizes the output of the first delay circuit with the external clock; and a delay gate having a plurality of stages connected in series. A second delay circuit capable of sequentially delaying and outputting the set number of stages based on the delay time control signal output from the means, and changing the set number of stages by the delay stage number control signal; The provided variable delay circuit for output of said second delay circuit and outputs the delayed signal to the input signal. 5. The variable delay circuit according to claim 1, further comprising a plurality of stages of delay gates connected in series, wherein the synchronous internal clock is used to set a delay time of each stage delay gate. A first delay circuit that delays by a predetermined time based on the first and second internal clocks and the output of the first delay circuit, and controls the delay time control signal so that their phases match. A delay lock loop including delay circuit control means for controlling a delay time of each delay gate in the first delay circuit, wherein an output of the first delay circuit is synchronized with the first or second internal clock; A delay circuit having a plurality of stages connected in series. The counter outputs are sequentially output by the delay gates for a set number of stages based on a delay time control signal output from the delay circuit control means. A second delay circuit that can output the extended delay and change the set number of stages by a delay stage number control signal. The second delay circuit outputs the output of the second delay circuit to the counter output that is a delay signal for the input signal. A variable delay circuit for outputting a delayed final delay signal. 6. The variable delay circuit according to claim 1, wherein the counter is connected between the second oscillator and the counter to delay a second internal clock output from the second oscillator. An additional variable delay circuit unit that supplies the second internal clock to the second internal clock and a delay time of the delay gate of each stage. A first delay circuit for delaying a predetermined time based on a delay time control signal to be set, and a delay circuit for receiving the second internal clock and the output of the first delay circuit so that their phases match. A delay lock loop including delay circuit control means for controlling a delay time of each delay gate in the first delay circuit by a signal, wherein an output of the first delay circuit is synchronized with the second internal clock. Circuit and A delay gates of stages connected in sequence, the second
Based on the delay time control signal output from the delay circuit control means, and sequentially outputs the internal clocks by the delay gates corresponding to the set number of stages, and the set number of stages can be changed by the delay stage number control signal. A second delay circuit, wherein the counter is configured to count an output of the second delay circuit. 7. The variable delay circuit according to claim 1, further comprising: an additional variable delay circuit for delaying a second internal clock synchronized with the input signal, which is an output of the second oscillator. A flip-flop having an input of an output of a circuit section and the output of the counter as inputs; and the additional variable delay circuit section having a plurality of stages of delay gates connected in series. A first delay circuit for delaying a predetermined time based on a delay time control signal for setting a delay time of a delay gate of a stage, and receiving the second internal clock and the output of the first delay circuit; And delay circuit control means for controlling the delay time of each delay gate in the first delay circuit by the delay time control signal so that the output of the first delay circuit is equal to the second internal clock. same A delay locked loop circuit to which the, a delay gates of a plurality of stages connected in series, the second
, Based on the delay time control signal output from the delay circuit control means, and sequentially outputs the same number of delays by the delay gates for the set number of stages, and the set number of stages can be changed by the delay stage number control signal. A second delay circuit, wherein the flip-flop outputs the counter output, which is a delay signal to the input signal, as a final delay output at an output timing of the second delay circuit after its generation timing. A variable delay circuit having a configuration.