DE19732142A1 - Variable delay circuit - Google Patents

Abstract

The delay circuit has a phase locked loop (PLL) circuit (110a) with first (111a) and second (111b) oscillators, and a counter (112). The first oscillator generates a first internal clock signal in phase with an external clock signal, but having a period which is a multiple of the external clock period. The second oscillator receives an input signal synchronised with the input signal, and having a period which is a multiple of the external clock signal (Cko) period. The counter counts the second internal clock signal and generates an output signal when the count reaches a defined value. The counter output is a delayed signal in relation to the input signal.

Description

 The present invention relates to a varia ble delay circuit and especially on a scarf tion structure in which a period of an external clock signal as a reference for a delay time and an input time of any trigger signal as a delay Start time for a signal is used.

A delay circuit has a large variety of implementation options. Fig. 13 (a) shows, for example, a simple structure of a delay circuit 50 , which consists of a plurality of serially connected delay gates or gates C ₁ to C _x be. When an input signal S _{in is} input in the delay circuit 50 at the input terminal 51 a, the input signal S _in is delayed by a predetermined time period Td as shown in FIG. 13 (b) and output as a delay output signal S _out at the output terminal 51 b. In other words, the basic delay time in this delay circuit 50 consists, for example, of a delay time t _p d of a respective delay gate, such as an inverter, one using the delay time t _p d of a single delay gate or element as a unit delay time Delay time Td obtained, which results from the multiple times the delay times t _p d (Td = t _p d × X). In general, the delay time of a respective delay element or gate is in a range from 10 to 100 ps. Assuming that the delay time is 100 ps, a delay time of approximately 1 ns is obtained by connecting 10 delay elements or gates in series.

However, when a plurality of delay circuits 50 are used to generate a plurality of delay signals, the delay times of the corresponding delay circuits 50 vary due to changes in the characteristics of the delay elements or gates used therein.

In the event that, for example, a large number of delay circuits 50 a ₁ to 50 a _{n are installed} in an electronic circuit 5 such that a required signal S ₁ in the respective delay circuits for generating a large number of delay output signals SD ₁ to SD _n is delayed, the desired delay time can not be reached or set according to the number of delay elements or gates in the respective delay circuits 50 a ₁ to 50 a _n , since there are deviations under the respective components, that is, changes in the characteristics of the Components of the delay elements or gates are present in the respective delay circuits.

For this reason, a variable or adjustable Delay circuit designed with a desired Delay time based on the duration of a ba clock, such as an external clock signal, can be obtained. More specifically, you get a delay time that is n / M times as long as the duration of the external clock signal (n and M are both natural numbers len).

Fig. 14 (a) shows a block diagram showing an example of the construction of such a variable delay circuit, while Fig. 15 (a) shows a block diagram showing a structure of a phased control (hereinafter, PLL, phased -locked loop, designated) of the structure described above.

Numeral 200 denotes a conventional delay circuit using a PLL control system. This variable delay circuit 200 consists of a PLL circuit 201 with a voltage-controlled oscillator 240 (hereinafter referred to as VCO), which generates an internal clock signal CK _PLL with a predetermined period of time in accordance with an oscillator control signal OS _CONT . The PLL circuit 201 regulates the oscillator or oscillation frequency of the internal clock signal by the PLL control system, while a counter 202 counts the oscillator output signal (internal clock signal) CK _{PLL of} the VCO 240 and generates a counter output signal S _out when the count value a set point or set point Cs he reaches (that is, the number to be counted from the start of counting until the generation of the counter output signal), the set point Cs can be varied or changed by a set point control signal CD _cont .

Referring to FIG. 15 (a) is the above-described PLL circuit 201 of: an oscillator control device 201 a, which receives the external clock signal CK _o and the internal clock signal CK _PLL, and the oscillation frequency of the VCO 240 corresponding to the oscillator control signal SO _cont controls such that the phases of these clocks are aligned with one another. Furthermore, this circuit 201 has an n / M frequency divider 250 , which carries out an n / M frequency division (in this case 1/8 frequency division) on the output signal CK _{PLL of} the VCO 240 , so that the internal clock signal CK _PLL described above also is synchronized with the external clock signal CK _o and has a time period T _PLL which is a multiple (in this case 1/8) as long as the time period T _o .

The oscillator control device 201 a described above consists of a phase comparator or comparator 210 which compares the phase of the external clock signal CK _o and the phase of the divided output signal CK _{DM of} the n / M frequency divider with one another and a signal PD (phase comparison Output signal) which contains the information on the phase difference, which indicates how long the phase of one of these clock signals is delayed with respect to the phase of the other clock signal or this leads. Furthermore, the control device 201 a has a charge pump 220 , which converts the phase comparison output signal PD into a voltage V _PD , and a control filter 230 , which pulls out the DC components of the output signal of the charge pump 220 and outputs it as an oscillator control signal OS _cont .

More specifically, the phase comparator 210 has a circuit structure in which the phase-leading and phase-lagging pulses are output, the phase-leading and phase-lagging pulses having a pulse width corresponding to the leading and lagging phases between the external clock signal CK _o and the divided output signal CK _DM exhibit. In this case, the charge pump 220 has a circuit structure in which a capacitor is charged in accordance with the pulse width of the phase leading pulse, while the capacitor is discharged in accordance with the pulse width of the phase lagging pulse. The control filter 230 is constructed such that it receives the voltage across the capacitor, a signal obtained by averaging the voltage changes based on the phase-leading and phase-lagging pulses.

Referring to FIG. 15 (b) is the voltage-controlled Os zillator 240 of 2n + 1 stages of delay elements or -gattern annularly connected to one another and each having a _cont by the oscillator control signal OS adjustable delay time. The delay time setting connections of the delay elements or gates of the respective stages A ₁ to A _{2n + 1} are connected together to form an oscillator frequency setting input connection 24 a, to which the oscillator control signal OS _{cont is} applied. If in this case a delay time of a delay element or gate has the value t _pd in one stage, the oscillator frequency F of the VCO is 240

F = 1/2 t _pd (2n + 1).

Thus, the VCO 240 can set its oscillator frequency by setting the delay time t _pd for each delay element by the oscillator control signal OS _cont .

In FIGS. 14 (a) and 15 (a), the reference designate sign 20 a, 20 b, 21 a and 21 b an input terminal for an external clock signal, a delay Ausgangsan circuit, zögerungs- a delay input terminal and an Ver Control connection of the variable delay circuit 200 . Reference numeral 20 c denotes an output terminal for an internal clock signal of the PLL circuit 201 , reference numeral 24 b an output terminal for an internal clock signal of the VCO 240 , while reference numerals 21 c and 21 d each represent the input terminals for the internal and external clock signal of counter 202 denote.

Next, the operation will be briefly described with reference to Fig. 14 (b).

In the variable delay circuit 200 , by counting the internal clock signal CK _PLL generated in the PLL circuit 201 by means of the counter 202, the delay time Td is generated, which is an integral multiple (in this case four times) of the time period T _{PLL of} the internal clock signal CK _PLL .

More specifically, as shown in FIG. 15 (a), during phase-out of the external clock signal CK _o at the input terminal 20 a, the phase comparison between the external clock signal CK _o and the divided clock signal CK _{DM is performed} in the phase comparator 210 , the resultant phase comparison output signal PD in the charge pump 220 converted to the voltage V _PD and the voltage V _PD via the control filter 230 to the oscillator frequency setting input terminal 24 a of the VCO 240 supplied as an oscillator control signal OS _cont .

In the VCO 240 , the delay time for each delay element or gate t _pd corresponding to the oscillator control signal OS _cont for generating the internal clock signal CK _PLL with the time period T _PLL corresponding to the resulting delay time T _PLL (= 1 / F = 2t _pd (2n + 1)). In the n / M frequency divider 250 of the latter stage, the n / M frequency division is carried out on the internal clock signal CK _PLL . In this case, n / M is 8. The clock signal CKDM divided with respect to the internal clock signal CK _PLL is supplied together with the external clock signal CK _{o to} the phase comparator 210 , in which the phase comparison is carried out between these clock signals.

In the variable delay circuit 200 , this operation is repeated until the PLL control system becomes stable, ie the phase and frequency of the external clock signal CK _o coincides with the phase and frequency of the internal clock signal CKDM, so that the internal clock signal CK _{PLL is} output in synchronism with the external clock signal CK _o at the output terminal 24 b for the internal clock signal of the VCO 240 .

At this time, a control signal has been CD _cont for the set point of the delay control terminal 21 b of the counter 202 is supplied and set in this case, according to the signal of the value 4 for the set point Cs, which the to be counted number for a period between the count start of the internal clock signal CK _PLL and the generation of the counter output signal corresponds. Furthermore, the internal clock signal CK _PLL and the external clock signal CK _o is the respective clock signal input terminals 21 c and 21 d respectively supplied in counter 202nd

Then, when an input signal S _in the delay input terminal 21 is supplied to a of the counter 202 during the above-described state, the counter 202 starts counting of the internal clock signal CK _PLL in synchronization with the external clock signal CK _o, wherein the period n / M times is as long as that of the external clock signal at the rise time t _{0 of} the first external clock signal CK _o after the input time t _{in of} the input signal S _in , while the counter 202 outputs an output signal S _out as a delay output signal with respect to the input signal S _in generated when the counter reaches a set point Cs (at time t _out ). After the generation of the counter output signal S _out , a reset is carried _out after a predetermined reset time T _cr .

The delay time Td is generated based on the rising timing t _{0 of} the external clock signal CK _o after the timing t _in at which the input signal S _in is applied as a trigger signal, as shown in Fig. 14 (b).

In the variable or adjustable delay circuit 200 having the structure described above, a longer delay time than the delay time t _{pd of} a respective delay element or gate can be obtained in a simple manner, since the delay time Td corresponds to the set point Cs for the counter 202 can be set, which counts the internal clock signal Ck _PLL output by the VCO 240 . In the delay circuit 50 shown in Fig. 13 (a), which has series-connected delay elements, for example, 100 series-connected delay elements or gates are required to obtain a delay time of 10 ns when the delay time of a single delay element is 100 ps is. On the other hand, in the above-described variable delay circuit 200, the delay time Td can be set as the smallest unit with the time period T _{PLL of} the internal clock signal CK _PLL , in which only the set point Cs for the counter 202 changes in accordance with the set point control signal CD _cont becomes. More specifically, in a case in which GaAs is used as the material for the circuit components, the frequency of the internal clock signal CK _{PLL can be set} to 1 GHz, provided the frequency of the external clock signal CK _{o is} approximately 100 MHz. Accordingly, the set point Cs of the counter 202 in the variable delay circuit 200 is set to 10 to obtain the delay time of 10 ns.

In the state described above, a sufficient electrical power is required in the delay circuit 50 to control 100 delay elements or gates, it being difficult to obtain a delay time due to the deviations in the properties or characteristics of the corresponding delay elements, which is exactly 100 times as long as the unit delay time t _pd . On the other hand, in the variable delay circuit 200 due to the regulation of the VCO 240 via the PLL control system, the frequency of the internal clock signal CK _PLL corresponds to a predetermined multiple of the frequency of the external clock signal CK _o regardless of the deviations in the characteristics of the components of the VCO 240 , so that the delay time Td can be set on the basis of the time period T _{0 of} the external clock signal CK _o . In the variable delay circuit 200 , therefore, a longer delay time than the delay time of the respective delay element can be controlled in accordance with the control signal CD _cont as a function of the set point Cs with improved accuracy.

Next, another structure of a conventional one Chen variable delay circuit described.

Fig. 16 (a) shows a block diagram showing a circuit construction of a variable delay circuit that uses delay control (hereinafter referred to as DLL, delay-locked loop). In the figure, reference numeral 300 denotes a conventional delay circuit using a DLL control. The variable delay circuit 300 has a voltage-controlled delay line 340 (VCDL) which delays the external clock signal CK _o by a predetermined time interval in accordance with the delay time control signal DT _cont ; a delay circuit control device 300 b, which receives the external clock signal CK _o and a feedback output signal D _FB , which is one of the output signals of the delay circuit 340 , and controls the delay circuit 340 such that the phases of these clock signals are matched to one another; and an AND gate 301 that the delay output signal Se of the delay circuit 340 and the input signal S _in receives as an input signal and outputs a delay output signal S _o with respect to the input signal S _in . A DLL circuit 300 a, which consists of the delay circuit 340 and the control device 300 b, synchronizes the output clock signal of the delay circuit 340 with the external clock signal CK _o .

The DLL circuit 300 a consists of a phase comparator 310 , which carries out a phase comparison between the external clock signal CK _o and the feedback output signal D _FB and which outputs a phase difference information (phase comparison output signal) PD, which indicates to what extent the phase of one clock signal leads the phase of the other clock signal; a charge pump 320 that converts the phase comparison output signal PD into the voltage V _PD ; and a control filter 330 that extracts the DC component of the output signal of the charge pump 320 to output as the delay time control signal DT _cont . Here, the phase comparator 310 , the charge pump 320 and the control filter 330 have the same structure as the corresponding elements in the variable delay circuit 200 according to FIG. 14.

The voltage-controlled delay line 340 (hereinafter referred to as VCDL) consists of delay elements or gates B ₁ to B _k according to FIG. 16 (a), which are serially connected to one another and each have a delay time that can be set by the delay time control signal DT _cont , and a selector 340 a, which selects one of the input signals of the respective delay elements in accordance with a delay stage number control signal DS _cont , in order to then output it. The delay time setting connections of the respective delay elements B ₁ to B _k are connected together to form a gate delay setting connection 34 a, to which the delay time control signal DT _{cont is} applied. If a delay time per delay gate t _pd , the delay time Td between the input time of the signal at the delay input signal terminal 34 b and the output time of the signal at the delay feedback terminal 34 is c Td = k × t _pd .

In FIGS. 16 (a) and 16 (b), the reference denote signs 34 d and 34 e a delay control terminal and a delay input terminal of the VCDL 340, while the reference numerals 31 and 32 each having a delay, a gear connection and a delay Denote output terminal of variable delay circuit 300 .

In the VCDL 340 may be a variable region from the selector 340 a modified delay time that the time intervals rule Zvi ie, the total delay time TD _k of the VCDL 340 represent alternate end delay elements or gridset (see FIG. 17) can be adjusted by the Entering the signal at the delay input terminal 34 b and outputting the signal at the delay feedback terminal 34 c is set in accordance with the delay time control signal DT _cont . Accordingly, by setting the total delay time of the corresponding delay elements to a value of the time duration T _{0 of} the internal clock signal CK _o, the delay time Td set by the selector 340 a on the basis of the time duration T _{0 of} the external clock signal CK _o Value set, that is, an integral multiple of the value (T ₀ / k) obtained by dividing the time period or period T ₀ by the total number of stages k of the delay elements or gate. The resolution of the delay time Td is equal to the delay time t _pd for each of the delay element or gate.

The operation will next be described with reference to FIG. 17.

In the variable delay circuit 300 with the DLL control system in the stable state, the clock signal from the external clock signal CK _{o is} generated by a period delayed as a delay feedback output signal D _FB , while in the VCDL 340 of the delay circuit 300 a the delayed clock signal is generated DG ₃ , ie the external clock signal CK _o delayed by the delay time TD _{e in} accordance with the delay stage control signal DS _cont , is selected from the output signals DG ₁ to DG _{k of} the delay elements in the k stages to use it as a selector output signal Se for delay - Output port 34 e to output. Under the circumstances described above, the input signal S is supplied _to the delay input terminal 31 of the AND gate 301 , in which the logic product (AND) between the input signal S _in and the selector output signal Se as the delay output signal S _out at the delay output terminal 32 is issued.

Thus, in the state in which the DLL control system is stable, the phase comparison between the external clock signal CK _o and the internal clock signal (delay feedback signal) V _{PD is} carried out in the phase comparator 310 , the resulting phase delay output signal PD in the Charge pump 320 is converted into the voltage V _PD and the voltage output signal V _PD via the Regelfil ter 330 as a delay time control signal DT _cont the delay time control signal input terminal 34 a of the VCDL 340 is supplied.

In the VCDL 340 , a unit delay time t _{pd of a} respective delay element or gate is set in accordance with the delay time control signal DT _cont , and by the total delay time TD _K , which represents the unit delay time multiplied by the number of delay elements , Delayed internal clock signal DG _k generated as a delay feedback output signal D _FB . The internal clock signal D _FB is supplied together with the external clock signal CK _{o to} the phase comparator 310 , in which the phase comparison between the clock signals is carried out.

In the variable delay circuit 300 , this operation is repeated until the DLL control system becomes stable, ie until the phase of the internal clock signal D _FB coincides with the phase of the external clock signal CK _o , so that the delay clock signal Se (selector output signal) the VCDL 340 is output in synchronism with the external clock signal CK _o at the delay output terminal 34 e.

Then, when an input signal S _in at the input terminal 31 of the AND gate 301 is present under this condition, the logical product between the input signal S _in and the selector output signal Se as the delay output signal S _out from the delay output terminal 32 of the AND gate 301 is output.

The delay time Td generated at this time is not based on the time t _in at which the input signal S _in is present as a trigger signal, but on the rise time t _{0 of} the external clock signal immediately after the time described above.

In the variable delay circuit 300 with such a DLL control system, the delay time can be changed in a simple manner, since the number of delay stages in the VCDL 340 is set by the delay stage number control signal DS _cont , which controls the selection device 340 a. Furthermore, the VCDL 340 is controlled by the DLL control system and the phase of the delay feedback output signal D _FB can be set independently of the deviation or change in the characteristics of the components of the VCDL 340 by setting the total delay time TD _{k of} the respective delay elements a time interval T _{0 of} the external clock signal CK _o corresponding time interval with which the phase of the external clock signal is brought into agreement or adapted. As a result, the delay time Td can be set on the basis of the time period or period T _{0 of} the external clock signal CK _o . In the variable delay circuit 300 , the delay time Td, which represents an integral multiple of a unit delay time, is obtained with certainty from the selection device 340 a, the time interval or the time period being used as the unit delay time, the 1 / k times is as long as the time period of the external clock signal CK _o .

Since the unit delay time in the variable delay circuit 300 is also based on the delay time t _{pd of} a respective delay element or gate and in particular the time is between 10 and 100 ps, the variable delay circuit 300 is particularly suitable for the generation of short delay times Compared to the variable delay circuit according to the circuit 200 , which uses the PLL control system, in which the unit delay time is almost equal to the time period or period T _PLL (1 ns) of the internal clock signal CK _PLL .

Incidentally, it should be noted that there is a case where the delay time based on the rise time point t _{in of} the input signal S _{in is} required as the delay time Td described above. In other words, there is a case where a delay circuit is required in which the measurement of the delay time starts immediately after the input signal S _{in is} input, thereby generating a delay signal with respect to the input signal S _in .

In the variable delay circuits 200 and 300 using the above-described PLL and DLL control systems, however _, the phases of the internal clock signals CK _PLL are used to generate the delay time Td based on the period T _{0 of} the external clock signal CK _o and D _FB each compared with the external clock signal CK _{o in} order to lock the phases of the respective internal clock signals onto the external clock signal CK _o or to bring them into a fixed relationship to one another. Even if the input signal S _in any of the variable delay circuits is input as an input trigger signal for generating a delay time, in the variable delay circuits described above, the delay signal S _out with respect to the input signal S _{in is} not dependent on the input timing t _in An input signal S _in , but depending on the rising (or falling) edge t _{0 of} the external clock signal CK _{o is} generated. In other words, the variable delay circuits 200 and 300 described _above can generate the delay time Td only in response to the external clock signal CK _o , but cannot produce the delay time Td based on the input signal S _in which, like the delay circuit 50 shown in FIG. 13 any time is entered.

In summary, it can be stated that, due to the conventional variable delay circuits 200 and 300, a constant delay time is not based on the input time t _{in of} the input signal S _in as a trigger signal but on the basis of the rising (or falling) edge t _{0 of} the external clock signal CK _o , which is not related to the input time t _in , is generated, and the delay time cannot be obtained using an arbitrary or random input signal as a trigger signal.

The invention is therefore based on the object to create variable delay circuit in which the Ver delay time based on a period of an external NEN clock signal and the time of generation of the delays time can be set, d. H. the delay The starting time of the input signal can be changed by an on time of entry of any input signal can be set.

According to a first partial aspect of the present invention a variable delay circuit consists of a variable delay circuit with: a PLL circuit with a first oscillator for generating a first in tern clock signal corresponding to a predetermined period an oscillator control signal and an oscillator Control device for controlling an oscillation frequency of the  first oscillator according to the oscillator control signal based on an external clock signal and a ge shared clock signal of the first internal clock signal where through an adjustment between a phase of the external Clock signal and the phase of the divided clock signal of the er most internal clock signal is reached, the divided Clock signal is synchronous to the external clock signal and a Period that is a multiple of the period of the external is a clock signal; a second oscillator for receiving of an input signal during a time interval between between the input time of the input signal and a Input time of a next input signal, and at Generate a second internal clock signal accordingly the oscillator control signal, which is the output signal of the Oscillator control device, the second internal clock signal is synchronous to the input signal and a Period that is a multiple of the period of the external is a clock signal; and a counter for counting the two th internal clock signal and to generate a counter Output signal when the counter reaches a set point is sufficient, the set point being one from the set point Control signal is variable value and the counter Output signal as a delay signal with respect to the on output signal is output.

In the variable delay circuit with a derar structure, the counter output signal is a delay output signal with respect to the input signal. There The counting of the internal clock signal begins here Counter depending on the input signal, while the Pe period of the second internal clock signal, the is counted by the counter on the period of time external clock signal based. As a result, the length of the Delay time based on the period of the external Clock signal and the delay start time are provided, d. H. the reference time for generation the delay time can be the same as that  Input time of the input signal are brought wel ches is entered randomly. Because the counter is beyond is constructed such that the set point by an on position control signal can be changed, the Län the delay time can be set as required.

According to a second aspect of the present invention have in the variable delay circuit according to the first part, the first and second oscillators each have a semiconductor circuit with a plurality of Semiconductor elements that as a semiconductor substrate Components are formed, and the first Oszilla gate semiconductor circuit and the second Semiconductor circuit representing oscillator side by side are arranged on the semiconductor substrate.

Therefore, the respective waveforms of the Os zillator control signals that the first and second Os zillator be fed, in so far as he similar be witnessed when this allows the layout of the oscillators light. Since the two half representing the oscillators conductor circuits are arranged adjacent to each other, can also fluctuations or deviations of the Characteristics of the respective half semiconductor elements representing conductor circuits Be reduced due to manufacturing processes. For that follow the difference in the oscillation frequency between the first and second oscillators reduced, whereby there is a minor error between that on the period of external clock signal based delay time and desired delay time results.

According to a third aspect of the present invention have in the variable delay circuit according to the first part, the first and second oscillators has a variety of gate circuits that loop are fen-shaped and each semiconductor elements be  that sit as ingredients on a semiconductor substrate are formed, which represent the first oscillator lend variety of gate circuits and the second A variety of gate circuits representing the oscillator are arranged alternately on the semiconductor substrate.

This layout or arrangement of the first and two ten oscillators allows the waveforms the oscillator signal input to the respective oscillators le are almost the same, causing fluctuations in the character teristics of the respective oscillators Reduce gate circuits due to process fluctuations be fluctuated in the characteristics between the oscillators become quite small. The Un difference of the oscillator frequency between the first and second oscillator is therefore significantly reduced where by itself a further reduced error between the on the period of the external clock signal based delays time and the desired delay time.

According to a fourth aspect of the present invention a variable delay circuit consists of a variable delay circuit with a DLL circuit with a first delay circuit, which a variety of Has stages of delay elements to delay an external clock signal by a predetermined time interval vall corresponding to a delay time control signal, wel ches a delay time of the delay element in each Level, are connected in series; and a delay circuit controller for receiving conditions of the external clock signal and the output signal in the first delay circuit and for controlling a delay time of a respective delay element in the first Delay circuit according to the delay time Control signal so that between the phase of the external clock signals and the phase of the output signal of the first delay a phase adjustment takes place, the  Output signal of the first delay circuit synchronously to the external clock signal; and a second delay circuit with a variety of series with each other connected stages from delay elements to step indicate delaying an input signal by some of the delays elements according to a set level number, causing the signal to correspond to a delay Time control signal, which is the output signal of the delays circuit control device is output , the set number of steps using a Delay stage number control signal can be changed can; the output signal of the second delay circuit as a delay signal with respect to the input signal is output.

The input signal is delayed by the second circuit therefore delayed directly while the length of the Delay time of the second delay circuit on the Period of the external clock signal corresponding to the delay time control signal based. As a result, the length the delay time based on the period of the ex tern clock signal can be set during the reference time for the generation of the delay time to one same value as the input time of the input signal can be brought that independently of the internal Taktsi gnal is entered.

Since the second delay circuit is also a Variety of delay connected in series structure or gates and is constructed in such a way that the number of stages of the delay elements for delaying the input signals according to a delay according to need step number control signal can be set the length of the delay time can be freely set.

According to a fifth aspect of the present invention There is a variable delay circuit after  first partial aspect further from a DLL circuit with a first delay circuit, which is a variety of serial interconnected stages of delay elements for Delay the synchronous internal clock signal by one correct time interval corresponding to a delay time Control signal which has a delay time of Delay element sets in each stage, and one Delay circuit controller for receiving the first or second internal clock signal and the output signals of the first delay circuit, and for control a delay time of a respective delay element in the first delay circuit corresponding to the delay gerungszeit control signal, so that between the phase of he most or second internal clock signal and the phase of the Output signal of the first delay circuit a Pha Sen adaption takes place, the output signal of the first Delay circuit is in synchronism with the external clock signal; and a second delay circuit with a plurality of serially connected stages of delays links to gradually delay an input signals around some of the delay elements corresponding to ei set number of steps, which corresponds to the signal chend a delay time control signal, which the off output signal of the delay circuit control device represents, is output, the set levels number by a delay stage number control signal is changeable; and wherein the output signal of the second Delay circuit as a delay signal with respect to the input signal is output.

Therefore, the length of the delay time on the Basis of the duration or period of the external clock gnals can be set and the delay start time of the input signal to the same value be brought in as the time of entry of the randomly given input signal. Because the delay time further through two delay steps for the input signal he  is generated, the resolution of the delay time increases for the input signal, making the delay time even more precise within a wide range from a minimum, that is limited by the resolution, up to a maxi mum, which is identical to the period or duration of the external Clock signal, can be set.

According to a sixth aspect of the present invention There is a variable delay circuit according to the first partial aspect also from a variable auxiliary delay circuit section between the second Oszil lator and the counter is switched to delay one second internal clock signal, which is the output signal represents the second oscillator and as a clock signal Meter is fed; the variable auxiliary delay circuit section from a DLL circuit with a first delay circuit, which is a variety of serial interconnected stages of delay elements for Delaying the second internal clock signal by one has a correct time interval, whereby the clock signal corresponding to a delay time control signal which a delay time of the delay element in each sets level, is output, and a delay gating circuit control device, the second internal clock signal and the output signal of the first delay receiving circuit and a delay time of one respective delay element in the first delay circuit according to the delay time control signal controls such that between the phase of the second internal Clock signal and the phase of the output signal of the first Delay circuit is a phase adjustment, wherein the output signal of the first delay circuit synchronously to the second internal clock signal; and a second ver Delay circuit consists of a variety of serial interconnected stages of delay elements for gradually delaying the second internal clock signal some of the delay elements correspond to one  has the number of steps, which corresponds to the Delay time control signal, which is the output signal of the delay circuit controller that Clock signal is output, the set levels Change number by a delay stage number control signal is derbar; and the counter is constructed such that he the output signal of the second delay circuit counts.

Therefore, the length of the delay time on the Based on the period of the external clock signal and a delay start time of the input i gnals can be brought to the same value as the one transition time of an input signal that is random or be is entered randomly. Because a delay time about that with two delay steps in relation to an on is generated, the resolution of the increases Delay time with respect to the input signal, whereby a highly precise setting of the delay time is realized becomes.

According to a seventh aspect of the present invention There is a variable delay circuit after first partial aspect also from a variable auxiliary delay circuit section for delaying the second inter NEN clock signal, which is the output signal of the second Os represents zillators and is synchronous to the input signal; and a flip-flop, which the output signal of the varia blen auxiliary delay circuit section and the counter receives output signal as input signals; where the va riable auxiliary delay circuit section from one DLL circuit with a first delay circuit, the one Variety of stages of Delay elements for delaying the second internal Clock signal corresponding to a predetermined time interval a delay time control signal which the Delay time of the delay element in one  each level and a delay scarf device control device for receiving the second internal Clock signal and the output signal of the first delays circuit, and for controlling a delay time of the respective delay element in the first delay circuit according to the delay time Control signal so that between the phase of the second inter NEN clock signal and the phase of the output signal of the er most delay circuit a phase adjustment takes place, the output signal of the first delay circuit is in synchronism with the second internal clock signal; and one second delay circuit exists with a variety of serially connected stages of delays links to gradually delay the second in ent clock signal around some of the delay elements ent according to a set number of steps, which ent speaking a delay time control signal which the Output signal of the delay circuit control device represents the clock signal is output, the on number of stages by a delay number of stages Control signal is variable, and the flip-flop Counter output signal, which is a delay signal in Represents the input signal as a final one Delay output signal at the time of output of the second Delay circuit after the generation time of the Outputs counter signal.

Therefore, the length of the delay time on the Based on the period of the external clock signal during the delay start time of the on can be brought to an equal value like the random input of an input goose signals. Since the delay time is further reduced by two ver generated delay steps with respect to the input signal the resolution of the delay time in Regarding the input signal, creating a highly accurate on position of the delay time is realized.  

Furthermore, the total delay time in the second ver delay step regardless of the uneven counter output signal can be set, resulting in a verb Accuracy for the entire delay time gives.

The invention is based on execution examples with reference to the drawing be wrote.

Show it:

Fig. 1 (a) an overall configuration of a variable circuit according to a first tarry approximately exporting approximately invention, and Fig. 1 (b) is a diagram showing a configuration of a VCO of the variable delay circuit according to Fig. 1 (a),

Fig. 2 is a temporal representation of the variable deferrers delay circuit according to the first embodiment,

Fig. 3 (a) and 3 (b) are respectively a circuit diagram and a plan view illustrating a pattern of a circuitry layout, or va ables delay circuit according to a second embodiment OF INVENTION to the invention,

Fig. 4 (a) and 4 (b) are respectively a circuit diagram and a plan view illustrating a pattern of a circuitry layout, or va ables delay circuit according to a third embodiment OF INVENTION to the invention,

Fig. 5 (a) is a circuit diagram illustrating an overall configuration of a variable delay circuit according to a fourth OF INVENTION to the invention embodiment, and Fig. 5 (b) is a diagram circuit, the VCDL of the variable delay in FIG. 5 (a),

Figure 6 play. A timing signal representation of the variable delay circuit according to the fourth Ausführungsbei,

Fig. 7 (a) is a diagram va ables delay circuit according to a fifth embodiment approximately example illustrates schematically, and Fig. 7 (b) is a diagram showing construction of a specific example of Schaltungsauf according to Fig. 7 (a) illustrates a configuration of a,

Figure 8 play. A timing signal representation of the variable delay circuit according to the fifth Ausführungsbei,

Figure 9 (a), that a circuit configuration of a variable delay circuit according to a sixth embodiment of the invention schematically represents a circuit diagram represent., And Fig. 9 (b) is a diagram (a) illustrates a specific example of the circuit configuration of FIG. 9,

Fig. 10 play a temporal signal representation of the variable delay circuit according to the sixth Ausführungsbei,

Fig. 11 (a) is a schematic representation of a circuit construction of a variable delay circuit according to a seventh embodiment of the invention and

Fig. 11 (b) is a diagram (a) illustrates a specific example of the circuit construction of FIG. 11,

Fig. 12 (a) is a timing signal diagram of a va ables delay circuit according to a seventh exporting approximately example and FIG. 12 (b) is a time Signaldarstel development of a flip-flop of the variable delay circuit according to the seventh embodiment,

Fig. 13 (a) construction of a conventional tarry circuit incorporating delay elements, Fig. 13 (b) an associated time signal representation and Fig. 13 (c) an associated application example,

Fig. 14 (a) is a circuit diagram illustrating a structure of the conventional forth variable delay circuit having a PLL control system schematically, and FIG. 14 (b) since a corresponding time signal representation,

Fig. 15 (a) is a block diagram of the conventional varia ble delay circuit, and Fig. 15 (b) is a circuit diagram illustrating a configuration of the conventional variable delay circuit deferrers used VCO,

Fig. 16 (a) is a block diagram of a conventional va ables delay circuit with a DLL control system and

Fig. 16 (b) is a circuit diagram illustrating a structure of the VCDL used in the forth conventional variable delay circuit, and

FIG. 17 shows a temporal signal representation of the variable delay circuit according to FIG. 16 (a).

Embodiment 1

The Fig. 1 (a) shows a block diagram according to ei is a circuit diagram of a variable delay circuit nem first embodiment of the invention. In the figure, the same reference numerals as in FIGS. 14 (a) and 15 (a) denote the same or corresponding elements as in the conventional variable delay circuit 200 . Reference numeral 110 denotes a variable delay circuit with a PLL control system according to a first embodiment. The variable delay circuit 110 has a PLL circuit 110 a which, for generating an internal clock signal CK _PLL for the PLL with an accordingly an oscillator control signal OS _cont predetermined period, a first voltage controlled oscillator (VCO1) 111 a and an oscillator Control device 110 b for controlling an oscillation frequency of a first oscillator 111 a by means of the oscillator control signal OS _cont according to an external clock signal CK _o and the internal clock signal CK _PLL for the PLL, so that the phases of these clock signals CK _o and CK _{PLL to} one another are adapted and the internal clock signal CK _PLL for the PLL is synchronous with the external signal CK _o and has a period which is a multiple of the period of the external clock signal.

The variable delay circuit 110 also has a second voltage-controlled oscillator (VCO2) for receiving an input signal S _in and for generating a synchronous internal clock signal (second internal clock signal) CK _SINK during a time interval between the input time of the input signal and the input time of the next input signal , which is synchronous with the input signal S _in and has a period that is a multiple of the period of the external clock signal CK _o be, corresponding to the oscillator control signal OS _CONT , which represents the output signal of the oscillator control device 110 b. Furthermore, the variable delay circuit has a counter 112 for counting the synchronous internal clock signal CK _SINK and for generating a counter output signal C _out when the count value reaches a set point, the set point being changeable or variable via a set point control signal CD _cont . In the circuit 110 , the counter output signal C _{out is} output from the counter as a delay signal with respect to the input signal S _in .

The oscillator control device 110 b, like the oscillator control device 201 a in the conventional variable delay circuit 200, has a phase comparator or phase comparator 210 , a charge pump circuit 220 and a control filter 230 . In the first and second oscillators or resonant circuits 111 a and 111 b, the start and end of the oscillation operation can be controlled in accordance with the external signals.

Fig. 1 (b) shows a detailed circuit construction of the first voltage controlled oscillator 111 a (hereinafter referred to as the first VCO), which corresponds to the oscillator 240 in the conventional variable delay circuit 200 except for the fact that the delay element or gate Ver A _{2n + 1} in the last stage is replaced by a NOR gate A ₀ . In this structure, the delay control terminals to a vibration frequency The alternate input terminal 11 are of approximately tarry members A ₁ -A _2n connected in common sam each other in the first to 2n-th stages to form a. The output of the delay element A _2n in the 2n-th stage is connected to one of the inputs of the NOR gate A ₀ . The output of the NOR gate A ₀ is connected to the further input of the delay element A1 in the first stage. The further input of the NOR gate A ₀ is connected to a reset input terminal 11 b. The second voltage-controlled oscillator 111 b (hereinafter referred to as the second VCO) has the same structure as the first VCO 111 a, which is why the specific structure of the second VCO 111 b is not shown here. In Fig. 1 (a), reference numeral 10 a denotes an external clock terminal, reference numeral 10 b denotes a delay output terminal, and reference numeral 11 c denotes a VCO output terminal.

In the first and second VCO 111 a and 111 b with the structure described above, the oscillator output signal is set to L and no vibration is carried out when the signal applied to the reset input terminal 11 b is H. Conversely, if the circuit 11 b on reset Eingangsan supplied signal has the L level, the vibration is simultaneously excited. At this time, the first and second VCOs 111 a and 111 b output an internal clock signal CK _PLL for the PLL and a synchronous internal clock signal CK _SINK , the clock signals CK _SINK and CK _PLL having an oscillation _sequence corresponding to the oscillator control signal OS _cont exhibit.

So that the first VCO 111 a oscillates at any time, signals with L level are consequently continuously fed to the reset input terminal 11 b of the first VCO 111 a. The reset input terminal 11 b of the second VCO 111 b who is used as a reference for the delay time input signals S _in such that the oscillation begins with the falling time or the falling edge t _{in of} the input signal S _in , ie at the moment, when the input signal S _{in changes} from H to L. Since the oscillator control signal OS _cont , which is output from the oscillator control device 110 b, both the oscillation frequency setting connection 11 a of the first VCO 111 a and the second VCO 111 b is supplied, the first and second VCOs 111 a and 111 b always the same vibration frequency. The internal clock signal CK _PLL for the PLL is fed to the n / M frequency divider 250 as the output signal of the first VCO 111 a, while the synchronous internal clock signal CK _{SINK is} fed to the counter 112 as the output signal of the second VCO 111 b.

The counter 112 is constructed such that it receives the input signal S _in with the synchronous internal clock signal CK _SINK and starts counting the internal clock signal CK _SINK at the input time t _in of the input signal S _in . The counter 112 has the same construction as the counter 202 in the conventional variable delay circuit 200 , in which a control signal CD _cont for a set point for setting the set point C _s on the counter is supplied to the delay control terminal 112 and after Generation of the counter output signal C _out after a reset time T _cr a reset is carried out.

Thus, the variable delay circuit 110 generates the delay time Td by counting the synchronous internal clock signal CK _sink by means of the counter 112 .

The operation will next be described with reference to FIG. 2.

In the variable delay circuit 110 described above, the PLL circuit 110 A operates in the same manner as in the conventional variable delay circuit 200 . In other words, according to FIG. 2, in the state in which the external clock signal CK _{o is} input at the connection 10 a, this external clock signal CK _o and the divided clock signal CK _{DM are} fed together to the phase comparator 210 .

The phase comparison output signal PD is supplied as the phase difference between the clock signals as the oscillator control signal OS _cont via the charge pump 220 and the re gel filter 230 to the oscillation frequency setting connection 11 a of the first VCO 111 a. Since the signal level at the reset input terminal 11 b of the first VCO 111 a at that time is low, the internal clock signal CK _PLL for the PLL with the period T _PLL (T _PLL = T _0/10) accordingly the oscillator Control signal OS _cont output. In the next stage, an n / M frequency division for the clock signal CK _{PLL is} carried out in the n / M frequency divider 250 (in this case, n / M = 10) in order to supply the clock signal to the phase comparator 210 .

The phase comparator 210 , the charge pump 220 , the control filter 230 , the first VCO 111 a and the n / M frequency divider 250 represent the feedback control system (PLL control system) for a signal in which the internal clock signal CK _PLL with the external clock signal CK _{o is} synchronized. By repeating the control operation of the first VCO 111 a using the phase comparison output signal PD until the PLL control system becomes stable, the internal clock signal CK _PLL as the oscillator output signal of the first VCO 111 a can be synchronized with the external clock signal CK _o .

The oscillator control signal OS _cont is the vibra tion frequency setting input terminal 11 a of the second VCO 111 b in the same manner as in the first VCO 111 a leads. Since in the second VCO 111 b the input signal S is supplied _in the reset input terminal 11 b, there is no oscillation during the time in which the input signal S _{in is} at level H, which is why the signal level of the output terminal 11 c is on L lies.

When the input signal S _{in changes} from H to L at time t _in , ie when the input trigger signal is fed to the reset input terminal 11 b, the oscillation or oscillation begins, the input signal S _in , ie the one which is precisely synchronized with the input trigger signal te internal clock signal CK _SINK , is present at the VCO output terminal 11 c. In addition, the input signal S _{in is} also applied to the delay input terminal 112 b of the counter 112 , which starts the counting or the counting operation of the synchronous internal clock signal CK _SINK at time t _in when the input trigger signal is generated. The counting process is carried out in accordance with the control signal CD _cont for the set point which is supplied to the delay control terminal 112 a of the counter 112 . In other words, the counter 112 outputs the counter output signal C _out as a delay signal with respect to the input signal S _in at time t _out when the count value of the internal clock signal CK _{SINK reaches} the set point Cs (in this case, CS = 5) _Setpoint control signal CD _cont reached. A fixed reset time T _{cr is} set in the counter 112 and after generation of the counter output signal the counter is reset after the end or the end of the reset time T _cr (time t _cr ). In FIG. 2 is t _sr the reset timing of the input signal S _in (rise time) again and is set to the moment which is a certain period of time T _sr before the input trigger signal t _in (descent at the time of a crossing signal).

As described above, in the first exemplary embodiment, in addition to the PLL circuit 110 a, in which the oscillator control signal OS _{cont is} generated by the PLL control system with the first VCO 111 a, the second VCO 111 b is independent of the PLL control system provided, the second VCO 111 b is constructed such that the oscillation or oscillation corresponding to the oscillator control signal OS _cont begins when an input signal S _in is present, and the synchronous internal clock signal CK _SINK , which is the oscillator output signal of the second VCO 111 b represents and is synchronous to the input signal S _in, is counted in the counter 112 , where the counter output signal C _{out is} output as a delay signal with respect to the input signal S _in . Therefore, the reference point or reference point for the delay time Td (delay start time) can be set to the same value as the input time (rising time or falling edge) T _{in of} the input signal S _in regardless of the external clock signal CK _o .

Since the control of the second VCO 111 b is carried out by the oscillator control signal OS _cont generated in the PLL control system, the period or time period T _{SINK of} the synchronous internal clock signal CK _SINK , which represents the oscillator output signal of the VCO 111 b, represents a multiple of the period T _{0 of} the external clock signal CK _o (for example 1/10 times) as an internal clock signal CK _PLL for the PLL. Therefore, the delay time Td, which is generated by counting the synchronous internal clock signal CK _SINK , is based on the period T _{0 of} the external clock signal CK _o and is (T _0/10 ) × 5 in the exemplary embodiment described above.

In addition, since the counter 112 is designed to have a set point C _s that can be changed by the set point control signal CD _cont , there is a possibility that the length of the delay time Td after Be may by changing the period T _{SINK of} the synchronous inter NEN clock signal CK _SINK (T = _0/10) can be adjusted in th minimum Einheitswer (resolution of the delay time Td).

Embodiment 2

FIGS. 3 (a) and 3 (b) show diagrams for He purification of a variable delay circuit according to a second embodiment of the invention. The variable delay circuit according to the second embodiment has the same circuit structure as in the first embodiment, wherein, according to FIG. 3 (a), the first and second VCOs 111 a and 111 b each have 2n delay elements or gates A ₁ to A _2n and one Have NOR gate A ₀ as in the first exemplary embodiment.

According to Fig. 3 (b) are made in the variable tarry approximate circuit according to the second embodiment, the respective gates of gate circuits 3 a _0, each having a plurality of Halbleiterele elements have to 3a _2n and 3b ₀ to 3a _2n 2 as components. The semiconductor elements are formed on a semiconductor substrate 1 , which is a semiconductor chip or component. The gate circuits 3 a ₀ to _2n 3a, a semiconductor circuit 3111 illustrate a VCO according to the first a, while the Gat terschaltungen 3 b = ₀ to _2n 3b a semiconductor circuit according to pose 3 b b of the second VCO 111th The semiconductor circuits 3 a and 3 b are arranged adjacent to one another on the semiconductor substrate 1 .

Next, the working and functioning will be wrote.

In the first embodiment, by controlling the second VCO 111 b, which generates the synchronous internal clock signal CK _{Sink in} synchronization with the output signal S _in , and the first VCO 111 a, which generates the internal clock signal CK _PLL for the PLL in synchronization with the external clock signal CK _o Use of the single oscillator control signal OS _cont generates, the frequency of the synchronous internal clock signal CK _SINK adapted to the internal clock signal CK _PLL for the PLL or angegli Chen, whereby the length of the delay time Td of the delay signal with respect to the input signal S _{in the} same size as the period T _{0 of} the external clock signal CK _o is set.

In this case, two conditions must be met for the adjustment of the oscillation frequency between the first VCO 111 a and the second VCO 111 b: first, a common signal must be supplied to the oscillation frequency setting input connection 11 a of the first and second VCO 111 a and 111 b will; and secondly, the gates representing the first VCO 111 a must have the same properties or characteristics as the gates that build the second VCO 111 b.

Since in the second exemplary embodiment the semiconductor circuit 3 a serving as the first VCO 111 a and the semiconductor circuit 3 b serving as the second VCO 111 b are arranged on the semiconductor substrate 1 in such a way that their layout patterns are arranged in close proximity to one another, the oscillation frequency input terminals 11 a of the respective VCOs 111 a and 111 b in close proximity to the substrate, which is why the curve waveforms of the jewei time VCOs 111 a and 111 b supplied oscillator Steuersi gnale OS _cont in a same shape brought together who can. Since the semiconductor circuits 3 a and 3 b, each serving as VCO 111 a and 111 b, are also arranged adjacent to one another, the fluctuations in the characteristics or properties of the delay elements or gate and the NOR gate can be found in the respective Semiconductor circuits occur due to manufac turing processes can be reduced, whereby similar properties or characteristics are formed for the gates of the two VCOs 111 a and 111 b.

Accordingly, in the second embodiment, the difference between the oscillation frequency of the first VCO 111 a and the oscillation frequency of the second VCO 111 b can be reduced, thereby changing between the delay time Td based on the period of the external clock signal CK _o and the desired one -Delay time results in a smaller error.

The further effects of the second exemplary embodiment are obviously identical to those of the first exemplary embodiment, according to which the length of the delay time Td can be set on the basis of the period T _{0 of} the external clock signal CK _o , during the point in time serving as a reference point for the generation of the delay time, that is, the delay start time for the input signal can be set to the same value as the input time t _{in of} the input signal S _in , which is supplied due or arbitrarily.

Embodiment 3

FIGS. 4 (a) and (b) show diagrams for Erläute tion of a variable delay circuit according to a third embodiment of the present invention. The variable delay circuit according to the third embodiment has an identical construction to the circuit construction according to the first embodiment. According to Fig. 4 (a) besit 111 zen the first and second VCOs a and 111 b are each 2 delay members or gridset A ₁ to A _2n and a NOR gate A ₀ as in the first embodiment, while the gate A ₀ to A _2n are connected in a loop. Further, according to possess Fig. 4 (b), the first VCO 111 a representative gate A ₀ to A _2n gate circuits 3 a ₀ to 3 _2n, where the gate circuits as their constituents each consist of egg ner plurality of semiconductor elements 2 parts. The second VCO 111 b representing Gat ter A ₀ to A _2n consist of gate circuits 3 b ₀ to 3b _2n , the gate circuits having a plurality of semiconductor elements 2 as their components. The semiconductor elements 2 are formed on a semiconductor chip or chip representing semiconductor substrate 1 .

Furthermore, according to the third embodiment, the gate circuits 3 a ₀ to 3 a _2n representing the first VCO 111 a and the gate circuits 3 b ₀ to 3 b _2n representing the second VCO 111 b are alternately in a line between a supply line side 6 a with a high potential and a supply line side 6 b arranged with low potential on the semiconductor substrate 1 .

Next, the working and functioning will be wrote.

Also in the third embodiment, to align the vibration frequencies of the first and second VCOs 111 a and 111 b, the conditions described above must be met, after which the same signals must be applied to the vibration frequency setting input terminals 11 a of the respective VCOs and Gates of the respective VCOs 111 a and 111 b have almost the same characteristics or properties.

Since in the third exemplary embodiment the gate circuits 3 a ₀ to 3 a _2n representing the first VCO 111 a and the gate circuits 3 b ₀ to 3 b _2n representing the second VCO 111 b are arranged alternately on the semiconductor substrate, there are the oscillation frequency setting input connections 11 a of the respective VCOs 111 a and 111 b in the immediate vicinity, which is why the curve waveforms of the oscillator control signals OS _cont supplied to the respective VCOs 111 a and 111 b are very similar.

Since the respective gate circuits of the two VCOs 111 a and 111 b are arranged such that the gates of the same level are arranged adjacent to one another, the gate circuits of the two VCOs 111 a and 111 b can furthermore have almost the same properties without adverse effects due to To show deviations in processing between the two VCOs 111 a and 111 b that occur during the manufacturing process.

Since the respective gates of the two VCOs 111 a and 111 b are also arranged in a line, the electrical voltage supply is supplied to the gates of the respective VCOs from the same supply lines 6 a and 6 b, which results in almost the same operation of the respective gates .

Consequently, in the third embodiment, the errors of the oscillation frequencies between the two VCOs 111 a and 111 b are so small that the delay time Td generated by the variable delay circuit on the basis of the period T _{0 of} the external clock signal CK _o can have almost the same value how the desired or design value.

Embodiment 4

The Fig. 5 (a) shows a block diagram illustrating a circuit configuration of a variable delay circuit accelerator as a fourth embodiment according to the invention. In the figure, the same reference numerals as in FIG. 16 denote the same or corresponding parts of the conventional variable delay circuit 300 , the reference numeral 140 denoting a variable delay circuit with a DLL control system according to the fourth embodiment. The variable delay circuit 140 has a DLL circuit 140 a with a first voltage-controlled delay circuit (hereinafter referred to as the first VCDL) 141 a, which delays an external clock signal CK _o by a predetermined time interval in accordance with a delay time control signal DT _cont , and a delay circuit - Control device 140 b, which receives the external clock signal CK _o and a delay feedback output signal D _FB from the first VCDL 141 a, and controls the first VCDL 141 a in accordance with the delay time control signal DT _cont such that the phases of these signals CK _o and D _FB are matched to one another, the delay feedback output signal D _{FB of} the first VCDL 141 a being synchronous with the external clock signal CK _o .

The variable delay circuit 140 also has a second voltage-controlled delay circuit 141 b (hereinafter referred to as second VCDL), which delays an input signal S _in accordance with a delay time control signal DT _cont that is output from the delay circuit control device 140 b and that Output signal DO of the second VCDL 141 b as a delay signal with respect to the input signal S _in .

The delay circuit control device 140 b like the delay circuit control device 300 b in the conventional variable delay circuit 300 has a phase comparator 310 , a charge pump 320 and a control filter 330 . Moreover possess shown in FIG. 5 (b), the respective VCDLs 141 a and 141 b of the same construction as the conventional VCDL 340th The VCDLs 141 a and 141 b described above each have delay gates B ₁ , B ₂ , B ₃ ,. . ., B _k in the k stages, which are connected to one another in series and each have a gate delay time which can be set by means of the delay time control signal DT _cont . A selection device 340 a selects one of the input signals of the delay elements or gates in the respective stages in accordance with the delay stage control signal D _Scont1 or DS _cont2 and outputs it as an output signal. The delay time setting connections of the delay elements B ₁ to B _k in the respective stages are connected together, whereby a gate delay setting connection 14 a is formed, to which the delay time control signal DT _{cont is} applied. To simplify, in the description of the fourth embodiment, reference numeral 14 b denotes the delay input terminal of VCDLs 141 a and 141 b, to which the external clock signal CK _o and the input signal S _are each input, reference numeral 14 c denotes egg NEN delay feedback terminal from which the delay feedback output signal D _{FB is} output, the reference numeral 14 d indicates the delay control terminals at which the delay stage control signals DS _cont1 and DS _{cont2 are} input, and reference _numeral 14 e denotes a delay output terminal at which a selection output signal Se is output. In FIGS. 5 (a) and 5 (b) the first and second VCDLs 141 a and 141 b as VCDL1 and VCDL2 be distinguished.

The operation will be described next.

The DLL circuit 140 a of the variable delay circuit operates in the same way as the DLL circuit 300 a of the conventional variable delay circuit 300 .

In other words, is processing in the variable delay scarf 140 delayed by one period with respect to the external clock signal CK _o clock signal as a delay feedback output signal D _FB in the DLL circuit 140 a he witnesses when the DLL control system in is in a stable state. More specifically, in the above-described state, a phase comparison between the external clock signal CK _o and the internal clock signal (delay feedback signal) D _{FB is} carried out in the phase comparison 310 and the resulting phase comparison output signal PD in the charge pump 320 is converted into the voltage V _PD . This output voltage V _PD is supplied as the delay time control signal DT _cont via the control filter 330 to the gate delay setting connection 14 a of the most VCDL 141 a.

In the first VCDL 141 a, the unit delay time of a respective delay element is set in accordance with the delay time control signal DT _cont , where the internal clock signal DG _k with a delay equal to the total value of the respective delay times of the delay elements as a delay feedback output signal D _{FB is} generated. At the same time, the internal delay clock signals DG ₁ to DG _k , which represent the external clock signals CK _o delayed by corresponding time intervals TD ₁ to TD _k (TD _k = t _pd × k), are generated by the delay elements B ₁ to B _k issued in the respective stages. Then the internal clock signal DG _k is supplied as a delay feedback output signal D _FB together with the external clock signal CK _{o to} the phase comparator 310 by performing a phase comparison between these clock signals.

Then the above-described procedure is repeated until the DLL control system becomes stable, ie the phase 37623 00070 552 001000280000000200012000285913751200040 0002019732142 00004 37504 of the external clock signal CK _{o is} "classified" or latched with the internal clock signal DG _k . Thus, the delay feedback output signal D _FB , which has the same delay except for a period T _{0 of} the external clock signal CK _o , is output at the delay feedback terminal 14 c of the VCDL 141 a.

At this time, the delay control signal DT _{cont is} supplied to the second delay circuit 141 b, in which the unit delay time t _{pd of} a respective delay element or gate B ₁ to B _{k is set} to the unit delay time of the first delay circuit 141 a becomes. In this state, this input signal S is _in step by step to the respective delay elements B ₁ to B _k of the delay circuit 141 b through the unitary delay time per delay element or gridset deferrers Gert, if the reference for the delay time, the designating input signal S _in the delay -Input terminal 14 b of the second delay circuit 141 b is present. Thereupon, the output signal of the delay element in the stage, the number of stages of which corresponds to the delay stage number control signal DS _cont , is selected via the selection device 340 a. In this case, from the selector 340 a, the output signal DG _{3 of} the delay circuit of the B _{3 is selected} in the third stage, from which the gate output signal DG ₃ (output signal Se ₂ ) as the delay output signal DO in relation to the input signal S _in is output to the delay output terminal 14 e.

The delay time Td obtained at this time, that is, the time interval between the rise time t _{in of} the input signal S _in and the rise time t _{out of} the selection output signal Se ₂ , is the same as the delay time TD _{3 of} the output signal DG ₃ of Delay element B ₃ in the third stage of the first delay circuit 141 a.

Since, as described above, in the fourth exemplary embodiment, the second VCDL 141 b for delaying the input signal S _{in is provided} independently of the DLL control system in addition to the DLL circuit 140 a, in which the delay time control signal DT _cont corresponds to the external clock signal CK _{o is contained} by the DLL control system with the first VCDL 141 a, the second VCDL 141 b is controlled by the delay time control signal DT _cont and the reference point (delay start time) of the delay time Td can be set to a value, which can be set to the same size as the input time (descent time) t _{in of} the input signal S _in independently of the external clock signal CK _o , the delay time Td can be based on the period T _{0 of} the external clock signal CK _{o in} accordance with the delay time control signal DT _cont he will be _fathered .

Since the second VCDL 141 b further comprise the delay elements B ₁ to B _k , which are connected to one another in a plurality of series of stages and each have controllable gate delay times and the selection device 340 a, which is one of the output signals of the respective delay gates DG ₁ to DG _{k is selected in} accordance with the delay stage control signal DS _cont , the delay time Td can be set with a delay time t _pd acting as a unit variable for each delay gate.

Embodiment 5

Fig. 7 (a) shows a block diagram showing a whole structure of a variable delay circuit according to a fifth embodiment of the present invention, while Fig. 7 (b) shows an associated detailed view.

In the figure, reference numeral 150 denotes a variable delay circuit having first and second variable delay circuit sections 150 a and 150 b, wherein the first variable delay circuit section 150 a has the same circuit structure as the variable delay circuit 110 according to the first embodiment and the second variable delay circuit section 150 b has the same circuit structure as the variable delay circuit 140 according to the second embodiment.

The variable delay circuit 150 has such a structure that the delay output terminal 10 b of the first variable delay circuit section 150 a is connected to the delay input terminal 14 b of the second variable delay circuit section 150 b, while the output terminal 11 c the second VCO 111 b of the first variable delay circuit section 150 a is connected to the external clock signal terminal 41 of the second variable delay circuit section 150 b. The output signal of the second VCDL 141 b in the second variable delay circuit section 150 b is output as the last delay signal DO ₂ , which is obtained by delaying a counter output signal C _out , which represents a delayed signal with respect to the input signal S _in .

The operation will next be described with reference to FIG. 8.

The description is based on the following assumption: the period T _{PLL of} the internal clock signal CK _PLL and the period T _{SINK of} the internal clock signal CK _SINK both have 1/10 the length of the period T _{0 of} the external clock signal CK _o ; set point Cs of counter 112 is 5; the output signal of the delay element selected by the selection device 340 a of the second VCDL 141 b is the output signal DG _{3 of} the gate in the third stage; and the descent time t _{in of} the input signal S _in serves as an input trigger signal.

First, the first variable delay line section 150 a scarf leads on the basis of the external Taktsi gnals _o CK and the input signal S _in the same operation as the variable delay circuit 110 according to the first embodiment. More specifically, the PLL circuit 110 a receives the external clock signal CK _o and the divided clock signal CK _DM , which is the divided output signal of the first VCO 111 , the phases of the internal clock signal CK _PLL for the PLL, which is the output signal of the first VCO 111 a represents, and the external clock signal CK _o are adapted to each other by the PLL control system. Input terminal upon application of the input signal S _in delay A to 11 b of the first variable delay TIC portion 150 a (time t _in) begins this to stand the second VCO 111 b with the generation of the synchronous internal clock signal CK _SINK, which synchronously to the input signal S _in , while the counter 112 starts simultaneously with the counting of the synchronous internal clock signal CK _SINK . The operation of oscillating the clock signal in synchronism with the input signal S _in in the second VCO 111 b is continued until the reset time t _{sr of} the next input signal S _in comes (rise time immediately before the fall time).

The counter 112 then generates the counter output signal C _out when the counter reaches a set point Cs of 5 (time t _co ). Accordingly, the first delay time Td _{1 is} generated as a time interval between the descent time t _{in of} the input signal S _in and the rise time t _{co of} the counter output signal C _out .

At this time, the synchronous internal clock signal CK _SINK , which is the oscillator output signal of the second VCO 111 b, is applied to the input terminal 41 of the second variable delay circuit section 150 b, the counter output signal C _{out to} the delay input terminal 14 b second VCDL 141 b, and corresponding to the synchronous internal clock signal CK _SINK and the counter output signal C _out, this variable delay circuit section 150 b performs the same operation as that of the variable delay circuit 140 according to the fourth embodiment. More specifically, the DLL circuit 140 a of the variable delay circuit section 150 b controls the first VCDL 141 a in accordance with the delay time control signal DT _cont such that the value of the delay time TD _{K of} the delay feedback output signal D _FB ( ie the output signal DG _{K of} the delay element B _K in the last stage) assumes the same value as the period T _{SINK of} the synchronous internal clock signal CK _SINK .

In addition, if the counter output signal C _{out of} the delay input terminal 14 b of the second VCDL 141 b is fed, then the time from the input time t _co to the delay time TD ₃ corresponding to the total delay time of 3 delay elements (ie the output signal DG _{3 of} the Delay element B ₃ in the third stage, which is selected by the selector 340 a) as the last or final delay signal DO ₂ at the delay output terminal 14 e.

Since in the second VCDL 141 b the delay time of the delay element in each stage is set in an identical manner to that in the first VCDL 141 a by the delay time control signal DT _cont , the second delay time is Td ₂ , which is the time interval between the generation of the counter output signal C _out and the generation of the final delay signal DO ₂ represents 3 / k times the period T _{SINK of} the synchronous internal clock signal CK _SINK .

Consequently, in the variable delay circuit 150, the total delay time Td generated as a function of the input signal S _in results from the sum of the delay time Td _{1 of} the first variable delay circuit section 150 a and the delay time Td _{2 of} the second variable delay circuit section 150 b .

Thus, since the fifth embodiment is a combination of the variable delay circuit 110 according to the first embodiment with the variable delay circuit 140 according to the fourth embodiment, the length of the delay time Td can be set based on the period T _{0 of} the external clock signal CK _o are, wherein the reference time for generating the delay time can be set to the same value as the input time t _{in of} the input signal S _in , which is input at random, as is also the case in the first and fourth exemplary embodiments, whereby the receives the following effect.

More specifically, the synchronous internal clock signal CK _SINK with the period T _{SINK is} counted in the first variable delay circuit section 150 a using the PLL control system, which is n / M times (more precisely 1/10) the period T ₀ of the external clock CK _o , where is generated by the delay time Td ₁ , which is a predetermined multiple of the period T _SINK (more precisely 5 times). In the second variable delay circuit section 150 b is using the DLL control system, in which the reference delay time represents the 1 / k times the period T _{SINK of} the synchronous internal clock signal CK _SINK (ie a delay time of a respective delay element) Delay time Td _{2 is} generated identically to a predetermined multiple of the unit delay time (more specifically 3 times).

Therefore, in the first variable delay circuit section 150 a, the resolution of the delay time Td to 1 / (n / M) times the period T _{0 of} the external clock signal CK _o and in the second variable delay circuit section 150 b, the resolution of the delay time Td be improved to a value which is 1 / k times the resolution of the first variable delay circuit section 150 a (ie T ₀ / k (n / M)). Accordingly, in the variable delay circuit 150, the resolution of the delay time Td can have the time interval T ₀ / k (n / M), where, with this time interval as the smallest unit, a delay time can be set with the interval which corresponds approximately to the period T _{0 of} the external clock signal as a maximum.

While in the fifth exemplary embodiment the synchronous internal clock signal CK _SINK in the first variable delay circuit section 150 b is fed to the external clock terminal 41 of the second variable delay circuit section 150 , the internal clock signal CK _PLL for the PLL in the first variable delay circuit section 150 a the external clock terminal 41 are supplied, whereby one obtains the same effects and effects as in the fifth embodiment.

Embodiment 6

Fig. 9 (a) shows a block diagram showing a whole structure of a variable delay circuit according to a sixth embodiment of the present invention, while Fig. 9 (b) shows an associated detailed view.

In the figures, reference numerals already given in FIGS . 1 (a) and 1 (b) and FIGS. 5 (a) and 5 (b) designate the same or corresponding parts as in the first and fourth exemplary embodiments. Numeral 160 be distinguished a variable delay circuit, the construction of the In the variable delay circuit 110 has, according to the he sten embodiment and further includes an auxiliary variable delay circuit section 160 a has, between the second VCO 111 b and the counter 112 is disposed and the output signal of the second VCO 111 b delayed ver forwarded to the counter 112 . The variable auxiliary delay circuit section 160 a has an identical circuit structure as the variable delay circuit 140 according to the fourth embodiment.

The variable delay circuit 160 has such a structure that the output terminal 11 c of the second VCO 111 b is connected to the external clock terminal 41 of the variable auxiliary delay circuit section 160 a and the delay input terminal 14 b of the second VCDL 141 b, while the output terminal 14 e of the second VCDL 141 b is connected to the clock input terminal of the counter 112 in such a way that the output signal of the second VCDL 141 b is fed to the counter 112 .

The operation will next be described with reference to FIG. 10.

In the following description, the respective periods T _PLL and T _{SINK of} the internal clock signals CK _PLL and CK _SINK , the set point Cs for the counter 112 and the output signal of the delay element selected by the selection device 340 a of the second VCDL 141 b correspond to the respective values in fifth exemplary embodiment, the descent time t _{in of} the input signal S _in serving as an input trigger signal.

In the variable delay circuit 160 according to this embodiment, the PLL circuit 110 a and the second VCO 111 b perform the same operation as in the first embodiment. When the input signal S _{in is} input (time t _in ), the second VCO 111 b begins with the generation of the synchronous internal clock signal CK _SINK syn chron to the input signal S _in , the period T _SINK 1/10 of the period T _{0 of} the external clock signal CK _o , and the counter 112 starts counting the input clock signal simultaneously.

Consequently, the synchronous internal clock signal CK _SINK is the external clock terminal supplied to b 41 of the variable Hilfsverzöge approximate circuit section 160 a and the Verzögerungsein input terminal 14 b of the second VCDL 141, wherein according to the synchronous internal clock signal CK _SINK the auxiliary variable delay circuit section 160 a the same Performs operation like the variable delay circuit 140 according to the fourth embodiment. Ge is said more precisely in the DLL circuit 140 a of the auxiliary variable delay circuit section 160 a the first VCDL 141 a from the delay time control signal DT _cont such ge controls that the value of the length of the delay time TD _k of the delay feedback output signal D _FB (More precisely, the output signal DG _{K of} the delay element B _K in the last stage) has the same value as the period T _{SINK of} the synchronous internal clock signal CK _SINK .

In the second VCDL 141 b, as in the first VCDL 141 a, a delay time of the delay element or gate is set in each stage in accordance with the delay time control signal DT _cont such that the value of the delay time TD _{k of} the output signal DG _{K of} the delay The control element B _K in the last stage has the same value as the period T _{SINK of} the synchronous internal clock signal CK _SINK , the output signal DG _{3 of} the delay element B _{3 being selected} in the third stage by the selection device 340 a in order to Selection output signal Se to be output at the delay output terminal 15 e. In this case, since the selection output signal Se is the output signal DG _{3 of} the delay element B _{3 of} the third stage of the second VCDL 141 b, the delay time TD _e (Td ₂ ) with respect to the synchronous internal clock signal CK _{SINK is} 3 / k times the value of the period T _{SINK of} the synchronous internal clock signal CK _SINK .

Since the counter 112 begins its counting at the input time point t _{in of} the input signal S _in , the delay clock signal corresponding to the selection output signal Se is counted immediately and the counter output signal C _{out is} generated when the count value is one Setting point Cs of 5 is sufficient (time t _CO ). Therefore, a further delay time Td _{1 is} generated as a time interval between the time of generation of the selection output signal Se corresponding to the input signal S _in (time t _se ) and the rise time t _{CO of} the counter output signal C _out .

Consequently corresponds circuit in this variable delay 160, the input signal S _in corresponding tal delay time Td of the sum of the delay time Td ₂ of the auxiliary variable delay circuit section 160 a and the delay time Td ₁ of the main part of the varia ble delay circuit 160th

Consequently, according to this sixth exemplary embodiment, the length of the delay time Td can be set using the period T _{0 of} the external clock signal CK _o as a reference, and the reference time for generating the delay time can be set to the same value as the input Time t _in an input signal S _in , which is entered randomly, as is also the case in the fifth embodiment. In addition to the effects described above, the time interval t ₀ / k (n / M) is used as a resolution of the delay time Td, with this time interval being the minimum or smallest unit, the delay time can be set so precisely that the maximum interval is almost is equal to the period T _{0 of} the external clock signal.

Further, in the sixth embodiment under Ver the period CK _SINK internal clock signal CK _SINK as a unit interval of the synchronous internal Taktsi gnal CK _SINK synchronism can twist of 1 / k times the value of the syn-synchronous given time Inter Valls to the input signal S _in is delayed by a beliebi ges time interval , since the _selector 140 a can be controlled by the delay stage number control signal DS _cont2 in the second VCDL 141 b.

Furthermore, since the Ver delay output signal with respect to the input signal finally receives as a counter output signal, are the Fluctuations in the delay time less than with fifth embodiment in which the counter Output signal is processed.  

While in the sixth embodiment, the variable auxiliary delay circuit section 160 a has an identical structure to the variable delay circuit 140 according to the fourth embodiment, the structure of the conventional variable delay circuit 300 using the DLL control system according to FIG. 16 for the variable auxiliary delay circuit section can also 160 a can be used. In this case, the output terminal 11 c of the second VCO 111 b is connected to the external clock terminal 30 a and the input terminal 31 of the AND gate 301 , while the delay output terminal 32 of the AND gate 301 with the clock input terminal of the counter 112 is connected in such a way that the output signal of the AND gate 301 is supplied to the counter.

Embodiment 7

Fig. 11 (a) shows a block diagram showing a whole structure of a variable delay circuit according to a seventh embodiment of the present invention, while Fig. 11 (b) shows an associated detailed view.

In the figures, the same reference numerals as in FIGS. 1 (a) and 1 (b) and FIGS. 5 (a) and 5 (b) designate the same parts, with FIGS. 1 (a) and 1 (b) and Figs. 5 (a) and 5 (b) illustrate the structure according to the first and fourth embodiments. Reference numeral 170 denotes a variable delay circuit which has the structure of the variable delay circuit 110 according to the first exemplary embodiment and also a variable auxiliary delay circuit section 170 a for delaying a synchronous internal clock signal CK _SINK , which represents the output signal of the second VCO 111 b, and a D flip-flop 171 , which receives the output signal of the variable auxiliary delay circuit section 170 a and the counter output signal C _out . The variable auxiliary delay circuit section 170 a has the same structure as the variable delay circuit 140 according to the fourth embodiment.

In the variable delay circuit 170 , the output terminal 10 b of the variable delay circuit 110 is connected to a D input terminal 171 a of the D flip-flop 171 , while the output terminal 14 e of the second VCDL 141 b of the variable auxiliary delay circuit section 170 a with the T. -Input terminal 171 b of the D flip-flop 171 is connected. The Q output terminal 171 c of the D flip-flop 171 is used as an output terminal for the delay signals. The D flip-flop 171 is constructed in such a way that the input level present at the D input terminal 171 a at the rising times or rising edges t ₁ to t _{5 of} the clock pulses present at the T input terminal 171 b have the same value as the output level on Q output connector 171 c.

The operation will be described next.

In the following description, the corresponding periods T _PLL and T _{SINK of} the internal clock signals CK _PLL and CK _SINK , the set point Cs for the counter 112 and the output signal Se of the delay element selected by the selection device 240 a of the second VCDL 141 b are identical to the respective values and signals according to the fifth embodiment, the descending time or the falling edge t _{in of} the input signal S _in serves as an input trigger signal.

Also in the variable delay circuit 170 according to this embodiment, the PLL circuit 110 a and the second VCO 111 b perform the same operation as in the first embodiment, wherein in the second VCO 111 b with the input of an input signal S _in (at time t _in ) the generation of a synchronous internal clock signal CK _SINK takes place, which is synchronous with the external clock signal CK _o and has a period T _SINK which is one tenth of a period T _{0 of} the external clock signal C ₀ , the counter 112 simultaneously counting the synchronous internal clock signal CK _SINK begins.

The counter 112 then generates a counter output signal C _out when the count value reaches a set point Cs of 5 (time t _CO ). As a result, the first delay time Td _{1 is} generated as a time interval between the descent time point t _in or the falling edge of the input signal S _in and the rise time t _CO or the rising edge of the counter output signal C _out .

At this time, the synchronous internal Taktsi gnal CK _SINK is the external clock terminal of the auxiliary variable delay circuit section 170 a and the tarry approximately input terminal 14 b of the second VCDL supplied 41,141 b, wherein in accordance with the synchronous internal clock signal CK _SINK the auxiliary variable delay circuit section 170 a operates in the same way as the variable delay circuit 140 according to the fourth embodiment. The DLL circuit 140 a of the variable auxiliary delay circuit section 170 a controls the first VCDL 141 a accordingly in accordance with a delay time control signal DT _cont such that the value of the delay time TD _k of the delay feedback output signal D _FB (ie the off gear signal DG _{K of} the delay element B _k in the last stage) has the same value as the period T _{SINK of} the synchronous internal clock signal CK _SINK .

In the second VCDL 141 b, as in the first VCDL 141 a, a delay time of the delay element in a respective stage is set in accordance with the delay time control signal DT _cont such that the value of the delay time TD _{K of} the output signal DG _{K of} the delay element B _{K of} the last stage has the same value as the period T _{SINK of} the synchronous internal clock signal CK _SINK , wherein the selection device 340 a selects the output signal DG _{3 of} the delay element B ₃ in the third stage in order to use it as the selection output signal Se ₂ to output at the delay output terminal 14 e. Since the selection output signal Se _{2 is} the output signal DG _{3 of} the delay element B _{3 of} the third stage in the second VCDL 141 b, the delay time TD _e corresponding to the synchronous internal clock signal C _{SINK has} a 3 / k times the value of the period T. _{SINK of} the synchronous internal clock signal CK _SINK .

Then, the counter output signal C _{out is} supplied to the D input terminal 171 a of the flip-flop 171 , while the delay output signal DO of the variable auxiliary delay circuit section 170 a, which corresponds to the selection output signal Se, the T input terminal 171 b of the Flip-flops 171 is supplied. Since flip-flop 171 is constructed such that the D-input terminal 171 a supplied input signal level at the rise-time or at the rising edge of b at the T input terminal 171 anlie constricting clock signal having the same value as the off input signal level at the Q Output terminal, the final delay output signal D _{2 is} output at the Q output terminal 171 c of the flip-flop 171 at the first rising time t _se or on the first rising edge of the delayed synchronous internal clock signal, which the selection output signal Se after generation corresponds to the counter output signal C _out .

Accordingly resulting circuit in the variable delay 170, the in respect to an input signal S witnessed _in he total delay Td from the sum of tarry delay time Td ₁ of the main part of the variable tarry approximate circuit 170 and the delay time Td ₂ of the varia ble auxiliary delay circuit section 170 a .

Thus, in the seventh embodiment, the length of the delay time Td can be set based on the period T _{0 of} the external clock signal CK _o , thereby obtaining the delay time Td whose generation start point is the input timing of the input signal S _in which is input at random. The exact setting of the delay time is realized using the resolution of the delay time with the time interval T ₀ / k (n / M) as in the sixth exemplary embodiment. In addition to the effects described above, the following effects are also obtained.

More specifically, the setting of the set point Cs for the counter 112 enables the delay time Td ₁ to be set as needed using the period T _{SINK of} the synchronous internal clock signal CK _SINK as a variable unit. By changing the delay element selected by the selection device 340 a in the second VCDL 141 b of the variable auxiliary delay circuit section 170 a, the second delay time Td ₂ can be set even more precisely using a delay time of a single delay element as a variable unit (ie the time interval is 1 / k times as long as the period T _SINK described above).

Furthermore, the counter output signal C _out , which defines the first delay time Td _{1, is} fed to the D flip-flop 171 , from which it is at the level of the counter output signal C _out at the rising time t _se or the rising edge of the selection output signal Se, which is delayed by the second delay time Td ₂ with respect to the synchronous internal clock signal CK _SINK . The total delay time Td, which results from the sum of the first and second delay times (= Td ₁ + Td ₂ ), is therefore determined by the synchronous internal clock signal CK _SINK independently of the counter output signal C _out , which very likely varies or changes, thereby improving the accuracy of the total delay time Td.

While in the seventh embodiment, the variable auxiliary delay circuit section 170a has the same structure as the variable delay circuit 140 according to the fourth embodiment, the structure of the conventional variable delay circuit 300 using the DLL control system shown in FIG. 16 can also be for the variable auxiliary delay circuit section 170 a can be used. In this case, the output terminal 11 c of the second VCO is connected to the external clock terminal 30 a of the variable delay circuit 300 and the input terminal 31 of the AND gate 301 , while the delay output terminal 32 of the AND gate 301 to the T input terminal 171 b of the flip-flop 170 is connected.

A variable delay circuit consists of a PLL circuit, with a first oscillator as a component of a PLL control system for controlling the first oscillator according to an oscillator control signal which is used to generate egg nes internal clock signal generated by the PLL control system is, the first internal clock signal with the divided Signal is synchronous to the external clock signal and a variety represents the period of the external clock signal; and a second oscillator, which is independent of the PLL control system stem a second internal clock signal synchronous to the input signal generated according to the oscillator control signal; and a counter that counts the second internal clock signal and the output signal as a delay signal with respect to outputs the input signal. In the variable delay circuit is the counter output signal as a delay signal in relation to the input signal. For that then the counter starts counting the internal clock gnals using the input signal as a reference, where the period of the second internal counted by the counter Clock signal on the period of the external clock signal ba  siert. Therefore, based on the period of the exter NEN clock signal, the length of the delay time and the Delay start time can be set, i. H. of the Reference time for the generation of the delay time can be set to the same value as the input Time of the input signal that entered randomly becomes. Furthermore, the counter is constructed such that the on set point changed by a set point control signal can be, reducing the length of the delay time after Demand can be set.

Claims (7)

1. Variable delay circuit ( 110 ) with:
a PLL circuit ( 110 a) with a first oscillator ( 111 a) for generating a first internal clock signal (CK _PLL ) with a predetermined period corresponding to an oscillator control signal (OS _cont ) and an oscillator control device ( 110 b) for control a vibration frequency of the first oscillator ( 111 a) corresponding to the oscillator control signal (OS _cont ) on the basis of an external clock signal (CK _o ) and a divided clock signal (CKDM) of the first internal clock signal (CK _PLL ), thereby ei ne Adaptation between a phase of the external clock signal (CK _o ) and the phase of the divided clock signal (CK _DM ) of the first internal clock signal (CK _PLL ) is achieved, wherein the divided clock signal (CKDM) is synchronous with the external clock signal (CK _o ) and has a period that is a multiple of the period of the external clock signal (CK _o );
a second oscillator ( 111 b) for receiving an input signal (S _in ) during a time interval between the input time of the input signal (S _in ) and an input time of a next input signal, and for generating a second internal clock signal (CK _SINK ) corresponding to the oscillator control signal (OS _cont ), which represents the output signal of the oscillator control device ( 110 b), the second internal clock signal (CK _SINK ) being synchronous with the input signal (S _in ) and having a period that is a multiple is the period of the external clock signal (CK _o ); and
a counter ( 112 ) for counting the second internal clock signal (CK _SINK ) and for generating a counter output signal (C _out ) when the counter reaches a set point, the set point being a value that can be changed by the set point control signal (CD _cont ) and that Counter output signal (C _out ) is output as a delay signal with respect to the input signal (S _in ). 2. Variable delay circuit according to claim 1, characterized in that the first and second oscillator ( 111 a, 111 b) each have a semiconductor circuit ( 3 a, 3 b) with a plurality of semiconductor elements ( 2 ) on a semiconductor substrate ( 1 ) are designed as constituents, and the semiconductor circuit ( 3 a) representing the first oscillator ( 111 a) and the semiconductor circuit ( 3 b) representing the second oscillator ( 111 b) are arranged next to one another on the semiconductor substrate ( 1 ). 3. Variable delay circuit according to claim 1, characterized in that the first and second oscillator ( 111 a, 111 b) each have a plurality of gate circuits ( 3 a ₀ - 3 a _2n , 3 b ₀ - 3 b _2n ) which are schleifenför mig connected and be seated in each semiconductor elements (2), which are designed as components on a semiconductor substrate (1), wherein the first oscillator (111 a) performing plurality of gate circuits (3 a ₀ - 3 _as a _2n) and the plurality of gate circuits ( 3 b ₀ - 3 b _2n ) representing the second oscillator ( 111 b) are arranged alternately on the semiconductor substrate. 4. Variable delay circuit ( 140 ) with:
a DLL circuit ( 140 a) with a first delay circuit ( 141 a), which has a plurality of stages of delay elements (B ₁ -B _K ) corresponding to delaying an external clock signal (CK _o ) by a predetermined time interval a delay time control signal (DT _cont ), which sets a delay time of the delay element in each stage, are connected in series with one another; and a delay circuit control device ( 140 b) for receiving the external clock signal (CK _o ) and the output signal in the first delay circuit ( 141 a) and for controlling a delay time of a respective delay element in the first delay circuit ( 141 a) accordingly delay time control signal (DT _cont), so that (a 141) a phase adjustment is made between the phase of the exter NEN clock signal (CK _o) and the phase of the output signal of the first delay circuit, said output of said first delay circuit (141 a) in synchronism with the external clock signal (CK _o ); and
a second delay circuit ( 141 b) with a plurality of series-connected stages of delay elements (B ₁ -B _K ) for gradually delaying an input signal (S _in ) by some of the delay elements of (B ₁ -B _K ) in accordance with a set number of stages, whereby the signal corresponding to a delay time control signal (DT _cont ), which is the output signal of the delay circuit control device ( 140 b), is output, the set number of stages can be changed by means of a delay stage number control signal (DS _cont ) ; in which
the output signal of the second delay circuit ( 141 b) is output as a delay signal with respect to the input signal (S _in ). 5. Variable delay circuit ( 150 ) according to Pa tent Claim 1, characterized by
a DLL circuit ( 140 a) with a first delay circuit ( 141 a) which has a plurality of series-connected stages of delay elements for delaying the synchronous internal clock signal (CK _SINK ) by a predetermined time interval in accordance with a delay time control signal ( DT _cont ), which sets a delay time of the delay element in each stage, and a delay circuit control device ( 140 b) for receiving the first or second internal clock signal (CK _PLL , CK _SINK ) and the output signal of the first delay circuit ( 141 a), and for controlling a delay time of a respective delay element in the first delay circuit ( 141 a) corresponding to the delay time control signal (DT _cont ), so that between the phase of the first or second internal clock signal (CK _PLL , CK _SINK ) and the phase of the output signal of the first delay circuit ( 141 a) a phase adaptation Assung takes place, the output signal of the first delay circuit ( 141 a) is synchronous to the external clock signal (CK _o ); and
a second delay circuit ( 141 b) with a plurality of serially connected stages of delay elements for the step-by-step delaying of an input signal (S _in ) by some of the delay elements corresponding to a set number of stages, whereby the signal corresponding to a delay time control signal (DT _cont ) which represents the output signal of the delay circuit control device ( 140 ), the set number of _{stages being} changeable by a delay stage number control signal (DS _cont ); and where at
the output signal of the second delay circuit ( 141 b) is output as a delay signal with respect to the input signal (S _in ). 6. Variable delay circuit ( 160 ) according to claim 1 with:
a variable auxiliary delay circuit section ( 160 a), which is connected between the second oscillator ( 111 b) and the counter ( 112 ) for delaying a second internal clock signal (CK _SINK ), which represents the output signal of the second oscillator ( 111 b) and is supplied to the counter ( 112 ) as a clock signal;
the variable auxiliary delay circuit section ( 160 a) consisting of:
a DLL circuit ( 140 a) with a first delay circuit ( 141 a), which has a plurality of serially connected stages of delay elements for delaying the second internal clock signal (CK _SINK ) by a predetermined time interval, whereby the clock signal corresponds to a Delay time control signal (DT _cont ), which sets a delay time of the delay element in a respective stage, is output, and has a delay circuit control device ( 140 b) which has the second internal clock signal (CK _SINK ) and the output signal of the first delay circuit ( 141 a) receives and controls a delay time of a respective delay element in the first delay circuit ( 141 a) in accordance with the delay time control signal (DT _cont ) such that between the phase of the second internal clock signal (CK _cont ) and the phase of the output signal of the first Delay circuit ( 141 a) a Pha s Adaptation takes place, the output signal of the first delay circuit ( 141 a) being synchronous with the second internal clock signal (CK _SINK ); and
a second delay circuit ( 141 b), which has a plurality of serially connected stages of delay elements for gradually delaying the second internal clock signal (CK _SINK ) by some of the delay elements according to a set number of stages, whereby according to the delay time control signal ( DT _cont ), which represents the output signal of the delay circuit control device ( 140 b), the clock signal is output, the set number of stages being changeable by a delay stage number control signal (DS _cont ); and where
the counter ( 112 ) is constructed such that it counts the output signal from the second delay circuit ( 141 b). 7. Variable delay circuit ( 170 ) according to claim 1 with:
a variable auxiliary delay circuit section ( 170 a) for delaying the second internal clock signal (CK _SINK ), which represents the output signal of the second oscillator ( 111 b) and is synchronous with the input signal (S _in ); and
a flip-flop ( 171 ) which receives the output signal of the variable auxiliary delay circuit section ( 170 a) and the counter output signal (C _out ) as input signals; the variable auxiliary delay circuit section ( 170 a) consisting of:
a DLL circuit ( 140 a) with a first delay circuit ( 141 a), which has a plurality of series-connected stages of delay elements for delaying the second internal clock signal (CK _SINK ) by a predetermined time interval in accordance with a delay time control signal (DT _cont ), which sets the delay time of the delay element in a respective stage, and a delay circuit control device ( 140 b) for receiving the second internal clock signal (CK _SINK ) and the output signal of the first delay circuit ( 141 a), and to control a delay time of a respective delay element in the first delay circuit ( 141 a) in accordance with the delay time control signal (DT _cont ), so that between the phase of the second internal clock signal and the phase of the output signal of the first delay circuit ( 141 a) a phase adjustment takes place, the output signal of the e rsten delay circuit ( 141 a) is synchronous with the second internal clock signal (CK _SINK ); and
a second delay circuit ( 141 b) consists of a plurality of serially connected stages of delay elements for gradually delaying the second internal clock signal (CK _SINK ) by some of the delay elements in accordance with a set number of stages, whereby in accordance with a delay time control signal (DT _cont ) , which represents the output signal of the delay circuit control device ( 140 b), the clock signal is output, the set number of stages being variable by a delay stage number control signal (DS _cont ), and wherein
the flip-flop ( 171 ) the counter output signal (C _out ), which represents a delay signal with respect to the input signal (S _in ), as a final delay output signal (DO ₂ ) at the time of output of the second delay circuit ( 141 b) after Output time of the counter output signal (C _out ) outputs.