JPH0115177B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a phase locked loop (Phase Locked Loop) in a local oscillator of a heterodyne receiver, particularly a variable frequency band multiplexing superheterodyne receiver.
This invention relates to a heterodyne receiver that performs frequency conversion using a local oscillator of a synthesizer (hereinafter referred to as PLL).

Generally, the reception frequency of a superheterodyne receiver is set by changing the frequency of the local oscillator, but in order to improve frequency stability and finely adjust the reception frequency, there is a method of mixing the frequency of the local oscillator at multiple locations. is taken.

For example, a superheterodyne receiver that uses a PLL synthesizer as a conventional local oscillator has the first
The configuration of the frequency conversion section as shown in the figure is adopted. That is, in FIG. 1, the high frequency signal input from the high frequency input terminal 1 is mixed with the output frequency _L1 of the first local oscillator 3 by the first mixer 2, converted to the first intermediate frequency i1, and then converted to the first intermediate frequency _i1 . 4 will be appropriately amplified. The first intermediate frequency signal of frequency _i1 amplified by the intermediate frequency amplifier 4 is mixed with the output frequency _L2 of the second local oscillator 6 by the second mixer 5 to produce a second intermediate frequency signal.
_i2 and output to the intermediate frequency output terminal 7. A PLL synthesizer is used for the first local oscillator 3 that inputs the output frequency _L1 to the first mixer 2, and the output frequency of this first local oscillator 3 is
By changing _L1 , the reception frequency is set. The second local oscillator 6 that inputs the frequency _L2 to the second mixer 5 is, for example, a crystal controlled oscillator, and the frequency _L2 is fixed.

The first local oscillator 3 receives two input signals: a reference oscillator 8 that oscillates at a reference frequency of ₀ , an input signal with a reference frequency of ₀ input from the reference oscillator 8, and an input signal input from a variable frequency divider to be described later. a phase detector 9 that outputs a DC voltage corresponding to the phase difference between
and a low-pass filter 10 that extracts only low frequency components of the DC voltage output from the phase detector 9.
Using the DC voltage obtained by the low-pass filter 10 as a control voltage, a voltage-controlled oscillator 11 whose output frequency changes in accordance with the control voltage, and an output frequency _L1 oscillated by the voltage-controlled oscillator 11 at an arbitrary frequency division ratio. It consists of a variable frequency divider 12 that divides the frequency into N (N is an integer value) and inputs the frequency-divided signal to the phase detector 9. Frequency divider 12
This constitutes a PLL. When the PLL is locked, _L1 = _N.0 (1) holds true.

Also, since the relationship between the output frequency _L1 of the first local oscillator 3 and the receiving frequency is = _L1 ± _i1 ...(2), the receiving frequency is = N・₀ from equations (1) and (2). ± _i1 ...(3)

As can be seen from equation (3), when changing the receiving frequency, it is sufficient to change the frequency division ratio N, but at that time, the receiving frequency changes at intervals (steps) of the oscillation frequency ₀ of the reference oscillator 8. Therefore, if the reception frequency is to be changed minutely, the oscillation frequency ₀ of the reference oscillator 8 must be lowered. When the oscillation frequency ₀ of the reference oscillator 8 is lowered, the time constant of the integrator that constitutes the low-pass filter 10 must be increased in order to maintain stable phase synchronization, and as a result, when the frequency is switched, the frequency becomes lower. The drawback is that it takes a long time to stabilize and the response is poor.

SUMMARY OF THE INVENTION The present invention aims to solve the above-mentioned drawbacks, and aims to provide a heterodyne receiving device that can obtain minute changes in reception frequency without lowering the oscillation frequency of a reference oscillator in a local oscillator. Therefore, the heterodyne receiver of the present invention uses a phase-locked loop synthesizer as a local oscillator, and is equipped with a variable frequency divider with variable division ratios N and M so that the frequency changes in different steps. a plurality of local oscillators using a phase-locked loop synthesizer, and each frequency division ratio N of each of the variable frequency dividers provided in the phase-locked loop synthesizer,
and a controller for individually controlling the frequency of each local oscillator so that the step change in the receiving frequency is equal to the difference in step frequency between the local oscillators, by simultaneously changing the respective local oscillators, and using a high reference frequency. It is characterized by being able to obtain minute changes in the receiving frequency. This will be explained below with reference to FIG.

FIG. 2 shows the circuit configuration of an embodiment of the frequency conversion section in the heterodyne receiver of the present invention. In the figure, numerals 1, 2, 4, 5, and 7 correspond to those in FIG. 13 is a first local oscillator which is a variable frequency oscillator; 14 is a second local oscillator which is a variable frequency oscillator; 15 is a controller which makes the output frequencies of the first local oscillator 13 and the second local oscillator 14 variable; 30.
8 is a reference oscillator which oscillates at a reference frequency ₀₁ ; 309 is a phase detector; 310 is a low-pass filter; 311 is a voltage controlled oscillator; 312 is a variable frequency divider; 408 is a reference oscillator which oscillates at a reference frequency ₀₂ ( ₀₂ , ₀₁ ), 409 is a phase detector, 410 is a low pass filter, and 411 is a voltage controlled oscillator.

The first local oscillator 13 and the second local oscillator 14 have the same configuration as the first local oscillator 3 shown in FIG.
A PLL synthesizer is used.

Now, the frequency division ratio of the variable frequency divider 312 in the first local oscillator 13 is N, the frequency division ratio of the variable frequency divider 412 in the second local oscillator 14 is M (both N and M are integer values),
Assuming that the output frequency of the first local oscillator 13 _{is L1} and the output frequency of the second local oscillator 14 is _L2 , when each PLL is locked, _L1 = N・₀₁ ...(4) _L2 = M・₀₂ ...( 5) holds true.

Furthermore, there is a relationship between the second intermediate frequency _i2 output to the intermediate frequency output terminal 7 and the reception frequency input to the high frequency input terminal 1 as follows: = _L1 ± _L2 ± _i2 (optional double sign)...(6) be.

For example, when the relationship is = _L1 + _L2 + _i2 , the formula
Substituting (4) and (5), we get =N・₀₁ +M・₀₂ + _i2 ……(7).

By the control signal from the controller 15, the frequency division ratio N of the variable frequency divider 312 is changed by 1 step up to n steps, N, N+1, N+2, . . . , N
+n, and at the same time change the frequency division ratio of the variable frequency divider 412 one step at a time to correspond to the frequency division ratio of the variable frequency divider 312 to M, M-1,
The frequency division ratio is changed like M-2, . . . , M-n. The reception frequency _o when the frequency division ratio changes up to n steps is _o = (N + n) ₀₁ + (M - n) ₀₂ + _i2 (8).

When the frequency division ratio of the variable frequency dividers 312 and 412 is changed by 1 step up to n steps by the control signal from the controller 15, the change width Δ _o of the receiving frequency is calculated from equations (7) and (8) as Δ _o = _o - = n ( ₀₁ - ₀₂ ) ... (9), and the change width Δ of the reception frequency per step is determined by the reference frequency ₀₁ of the first local oscillator 13 and the second local oscillator 13.
It is determined by the difference from the reference frequency ₀₂ of the local oscillator 14,
Reference frequency ₀₁ of each reference oscillator 308, 408,
A frequency lower than ₀₂ is obtained. That is, the reception frequency can be changed at frequency intervals lower than the reference frequencies ₀₁ and ₀₂ of each reference oscillator 308 and 408.

Similarly, in equation (6), for example = _L1 − _L2 + _i2
In the case of the relationship, the frequency division ratios of the variable frequency dividers 312 and 412 are N and N according to the control signal from the controller 15.
+1, N+2, ..., N+n, whereas M, M+1, M+2, ..., M+
It can be changed as n. The range of change Δ _o in the reception frequency when changed up to n steps is expressed by equation (9), and the same result as explained above can be obtained.
The same holds true for other relationships in equation (6).

In this way, the reference frequency of the first local oscillator 13
₀₁ and the reference frequency ₀₂ of the second local oscillator 14 and the direction of change in the frequency division ratio of the variable frequency divider 312, 412, the reference oscillator 308,
The reception frequency can be changed at frequency intervals lower than the respective reference frequencies ₀₁ and ₀₂ of 408.

As explained above, according to the present invention, since the output frequency of each local oscillator is individually controlled using a phase-locked loop synthesizer, it is possible to minutely change the receiving frequency. In addition, when the reception frequency is minutely changed, the reference frequency of the reference oscillator can be raised, making it possible to reduce the time constant of the integrator that makes up the low-pass filter, thereby eliminating the need to use the low frequency range of the low-pass filter. The response speed becomes faster and the time required to switch the receiving frequency can be reduced.

[Brief explanation of drawings]

FIG. 1 shows the circuit configuration of a frequency converter in a conventional heterodyne receiver, and FIG. 2 shows an embodiment of the circuit configuration of the frequency converter in the heterodyne receiver of the present invention. In the figure, 1 is a high frequency input terminal, 2 is a first mixer,
3 is a first local oscillator, 4 is an intermediate frequency amplifier, 5
is a second mixer, 6 is a second local oscillator, 7 is an intermediate frequency output terminal, 8 is a reference oscillator, 9 is a phase detector,
10 is a low pass filter, 11 is a voltage controlled oscillator, 12 is a variable frequency divider, 13 is a first local oscillator,
14 represents a second local oscillator, and 15 represents a controller.

Claims (1)

[Claims] 1 In a heterodyne receiver using a phase-locked loop synthesizer as a local oscillator: the frequency division ratios N and M are set so that the frequency changes in different steps.
a plurality of local oscillators using a phase-locked loop synthesizer each having a variable frequency divider; and each frequency division ratio N, M of each of the variable frequency dividers provided in the phase-locked loop synthesizer; A controller for controlling the frequency of each local oscillator individually so that the step change in the received frequency is equal to the difference in step frequency between the local oscillators. Device.