JPH0314826Y2 - - Google Patents

Description

[Detailed Description of the Invention] (Field of Industrial Application) The present invention relates to a PLL (Phase Locked Loop) circuit that is optimal for use in receivers, transceivers, etc.

(Prior Art) In recent years, so-called PLL circuits have been used as variable frequency oscillators in receivers, transceivers, and the like.
Figure 1 shows a typical configuration example of this PLL circuit.
The oscillation signal f _V of the VCO (voltage controlled oscillator) 1 and the oscillation signal f _H of the local oscillator 2 are mixed in the mixer 3, and the mixed signal (|f _V ±f _H |) is sent to the low-pass filter 4.
Unnecessary frequencies are cut off and the signal becomes |f _V ±f _H |
The signal is input to the divider 5 as follows. The signal frequency-divided by the divider 5 is phase-compared with the reference signal generator 7 in the phase comparator 6, and the difference is passed through the low-pass filter 8 as described above.
The signal is input to the frequency control terminal 9 of the VCO 1 so that the oscillation frequency of the VCO 1 is corrected to a predetermined value.

However, this type of PLL circuit generally has a problem in that it tends to be in an unlocked state (a state in which the oscillation frequency differs from the expected one or oscillation stops).

In other words, the relationship f _V > f _H is originally maintained when the device is locked, but since the output from the low-pass filter 4 is approximately zero when the power is turned on, the oscillation frequency of VCO 1 is lower than when it is locked (normal operation). Become. Here, if the relationship between the oscillation frequency (f _V ) of VCO 1 and the oscillation frequency (f _H ) of local oscillator 2 is f _V <
At f _H , the output of divider 5 becomes f _H − f _V , but
Since the phase comparator 6 does not have a function to distinguish between the state of f _V > f _H and the state of f _H > f _V , the frequency at this abnormal time (f _H − f _V )/N (N is the frequency division ratio) is mistakenly recognized as being ahead in phase with respect to the signal from the reference signal generator 7, similar to the normal frequency (f _V - f _H )/N,
The low-pass filter 8 outputs a signal to lower the output frequency (f _V ) of the VCO 1.
However, in the event of such an abnormality, the output frequency (f _V ) from VCO 1 must be increased to correct it, so in the above state, the unlocked state is maintained and the PLL circuit does not function permanently. That will happen.

Conventionally, the output voltage of the low-pass filter 8 was set as low as possible at the band edge to prevent the above-mentioned disadvantages.
In such a system, it is easy to become unlocked due to temperature changes, and when the oscillation voltage of VCO1 is increased to stabilize it, a rectification effect occurs in the variable capacitance diode in VCO1, resulting in a C/N (carrier level). There was a problem that the noise ratio) deteriorated.

(Purpose of the invention) The present invention has been made in view of the above points, and its purpose is to provide a PLL circuit that is free from the possibility of an unlocked state occurring.

(Structure of the invention) The PLL circuit according to the invention includes a frequency mixer in the loop, and the VCO frequency is varied within a range that is either higher or lower than the frequency of the local oscillator. a voltage-controlled oscillator (VCO) configured as shown in FIG. In the PLL circuit, the PLL circuit comprises a divider that divides the frequency of the output signal of the low-pass filter, a phase comparator that compares the frequency-divided signal with the output of the reference signal generator, and a power supply that supplies each of these blocks. A delay circuit is provided between the circuit of any one of the local oscillator, voltage controlled oscillator, mixer, low-pass filter, and divider block and the power supply, and a time period is established in which the frequency relationship between the VCO frequency and the local oscillator becomes normal. The configuration is such that power is supplied to the circuits of each of the blocks.

(Example) An example of the PLL circuit according to the present invention will be described based on FIG. 2.

In the figure, A indicates the entire PLL circuit, 1 indicates the VCO,
2 is a local oscillator, 3 is a mixer, 4 and 8 are low-pass filters, 5 is a divider, 6 is a phase comparator, and 7 is a reference signal generator, which are constructed in the same way as the conventional example shown in FIG. ing. A delay circuit 10 is provided between the local oscillator 2 and the power supply P in the embodiment, and is configured to supply power to the local oscillator 2 after a predetermined period of time after the power is turned on. The delay circuit 10 is set to a sufficient delay time (time constant) so that the relationship between the oscillation frequency of the VCO 1 and the oscillation frequency of the local oscillator 2 is normal (for example, f _V > f _H ). The local oscillator 2 can be turned off until the time is reached.

That is, until the delay time is reached, the phase comparator 6
The output of is DC and low pass filter 8 is VCO
The output voltage of the phase comparator 6 has the normal polarity (negative or positive). In this state, it is still in the unlocked state, but as soon as the above time constant is reached, the local oscillator 2
The operation of PLL circuit A is started, and PLL circuit A can be brought into a lock state immediately.

Note that in the embodiment, the operation of the local oscillator 2 is delayed, but this is not limited to this example.
A similar effect can be obtained even if the power supply to any one of the VCO 1, mixer 3, low-pass filter 4, and divider 5 is delayed.

(Effect of the invention) According to the PLL circuit according to the invention, the local oscillator, voltage controlled oscillator, mixer,
Since a delay circuit is provided that supplies power to the circuitry of either the low-pass filter or divider block, there is no risk of an unlocked state resulting from an inversion of the frequency relationship within the PLL. A stable oscillation signal can be obtained.

Moreover, since it can be forcibly set to the desired state, it will not be adversely affected by changes in semiconductor characteristics due to temperature changes, and even if the VCO output is set high, the C/N ratio will be reduced. It has excellent effects such as no risk of deterioration.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing a conventional PLL circuit.
FIG. 2 is a block diagram showing an embodiment of the PLL circuit according to the present invention. 1: VCO, 2: Local oscillator, 3: Mixer,
4: Low-pass filter, 5: Divider, 6: Phase comparator, 7: Reference signal generator, 8: Low-pass filter, 10: Delay circuit.

Claims (1)

[Claims for Utility Model Registration] A frequency mixer is included in the loop, and
A voltage controlled oscillator (VCO) in which the VCO frequency is variable within a range that is either higher or lower than the local oscillator frequency.
a mixer that mixes the oscillation signal of the voltage controlled oscillator and the oscillation signal of the local oscillator; a low-pass filter that cuts unnecessary frequencies in the output signal of the mixer; and a divider that divides the frequency of the output signal of the low-pass filter. In the PLL circuit, which consists of a phase comparator that compares the frequency-divided signal with the output of the reference signal generator, and a power supply that supplies each of these blocks, the local oscillator, voltage-controlled oscillator, mixer, and low-pass filter and a delay circuit is provided between the circuit of any block of the divider and the power supply,
A PLL circuit characterized in that the PLL circuit is configured to supply power to the circuits of each of the blocks after a time when the frequency relationship between the VCO frequency and the local oscillator becomes normal.