GB2331643A

GB2331643A - Local oscillator arrangement

Info

Publication number: GB2331643A
Application number: GB9724656A
Authority: GB
Inventors: Anthony David Newton
Original assignee: Motorola Inc
Current assignee: Motorola Solutions Inc
Priority date: 1997-11-22
Filing date: 1997-11-22
Publication date: 1999-05-26
Also published as: GB9724656D0

Abstract

A local oscillator arrangement (100) comprises a voltage controlled oscillator (1) incorporated in a phase locked loop circuit having a signal frequency input (4), a frequency locked loop circuit including a reference crystal oscillator (10) and operable to control the frequency of the voltage controlled oscillator (1) and a feedback loop (18) within the frequency locked loop circuit to adjust the reference crystal oscillator frequency and phase so as to resolve the conflict imposed on oscillator (1) to lock on to one of a transmission signal Fs received (at 4) and the crystal oscillator (9,10) output. The phase locked loop includes a wideband filter (3) to reduce the noise of the controlled oscillator and the frequency lock loop assists in pulling the oscillator (1) to lock. The output of the oscillator (1) may be suitably combined in a superheterodyne or direct conversion mixer arrangements.

Description

2331643 LOCAL OSCrLLATOR ARRANGEMENT

Field of the Invention

The present invention relates to local oscillators for television receivers and more particularly to such local oscillators that can be manufactured as integrated circuits.

Background of Invention

The general problem with which the present invention is concerned is that of being able to manufacture a local oscillator which will, in operation, give adequate performance whilst generating relatively low noise level and at the same time being amenable to manufacture as an integrated circuit.

It is known to obtain good noise performance by using high Q (Quality Factor) resonance circuits, such as an LIC (inductance) resonator,quartz crystals or other high Q resonators, usually with a high Q varicap resonator diode for tuning the frequency.

However, such oscillators if integrated on a chip would not provide an adequate performance in terms of all the required parameters, such as noise performance, stability and frequency range. For example, an on-chip oscillator with off-chip tuning components, may still have problems at higher frequencies due to parasitic resonances of the bond wires and package leads.

Generally speaking it is easier to fabricate an R/C type oscillator on a chip than an LIC type oscillator and therefore where integration is a priority, an RIC based oscillator, such as a zing oscillator, would be more attractive to employ. However, R/C type oscillators generate a relatively high noise level compared with an LIC type oscillator and this is particularly significant when the local oscillator is to be used in a T.V. receiver or tuner.

2 The present invention is therefore concerned with the problem of providing an integrated local oscillator arrangement which has a satisfactory noise performance.

Summary of Invention

According to the present invention, there is provided a local oscillator arrangement as claimed in claim 1.

Thus, the present invention provides a voltage controlled local oscillator, typically but not exclusively for a tuner for a television receiver, comprising a voltage controlled oscillator in a frequency locked loop (FLL) circuit together with a phased locked loop (PLL) circuit which operates to reduce the voltage controlled oscillator noise in the spectral region on either side of the carrier frequency to a distance given by the loop filter.

Thus, the present invention can provide an integrated local oscillator without the need for external tuning circuits.

It is well known that putting a WO (voltage control oscillator) in a frequency synthesiser loop, where its output frequency is controlled by the filtered output of a frequency comparator, which compares a division of the WO's frequency with a stable reference frequency (e.g. produced by crystal oscillator), improves the WO's spectral noise performance on both sides of its operating frequency up to, but not exceeding, a frequency deviation given by the reference frequency.

Unfortunately, the reference frequency needs to be low to give adequate frequency resolution (step size) and this prevents noise reduction over a useful spectrum. Another limitation is the filter bandwidth is often very low.

The present invention overcomes these problems by using the transmitted signal itself as the reference signaL In other words, the system now contains 3 two reference frequencies, a low frequency crystal for the FLL circuit and the signal itself for the PLL circuit.

The present invention is particularly useful with a variety of receivers such as superhet, direct conversion (i.e. zero IF) or so-called non-zero (i.e. dose to but not equal to zero) receivers where the local oscillators' phase noise or jitter is often a limiting factor on the overall system performance.

Brief Description of the Drawings

How the invention may be carried out will now be described, by way of example only, and with reference to the accompanying drawings in which:

Figure 1 illustrates the invention incorporated in a superhet receiver; Figure 2 illustrates the invention incorporated in a non-zero IF receiver; and Figure 3 illustrates the invention incorporated in a direct conversion or zero IF receiver.

Detailed Description of the Drawings

The circuit 100 shown in figure 1 is made up essentially of two circuits labelled A and B respectively.

Circuit A is the circuit according to a preferred embodiment of the present invention and is in turn made up of sub-circuits A1 and A2.

Circuit B is a standard single sideband mixer circuit.

Circuit A wiR now be described.

4 Circuit Al comprises a four stage ring voltage controlled oscillator 1 which although it is ideal from a number of points of view, nevertheless has the disadvantage that it is relatively noisy.

The oscillator 1 is in circuit with a multiplier 2, which preferably comprises a Gilbert cell and a wide band filter 3 (greater than 6 Mhz). An incoming signal (SIGNAL) which in the preferred embodiment is the transmitted signal of the T.V. system, is coupled to input at 4. The use of the transmitted signal as an input signal to the circuit Al is instead of, as in the prior art, using an input from a "clean" oscillator.

Thus, circuit Al uses the transmitted signal as a reference and is locked to that signal- This contrasts with prior art approaches for "cleaning up" a ring oscillator (i.e. as far as its noise is concerned) which employ a standard synthesiser circuit using a clean crystal. However, such prior art circuits whilst they are suitable for relatively narrow bandwidth incoming signals, e.g. radio, they are not suitable for the relatively wide bandwidth signals such as TY. signals.

The role of the Gilbert cell 2 will now be described.

There are basically two types of phase detector which can be used in a phase locked loop. The first type detects the edges of signals and the second type detects the phase of signals. The Gilbert cell is of the second type and is frequency independent. It is therefore not affected adversely by spikes in the signal as would an edge detecting frequency dependent device. It is for this reason that it is employed in circuit Al.

However, the Gilbert cell does have the disadvantage that it is not good at pulling an oscillator into lock because if it is too far oTthe frequency, it operates as if it is in open circuit.

Circuit A1 comprises essentially a noisy voltage controlled oscillator 1 in a phase locked loop circuit. The action of this loop is to reduce the noise of the voltage controlled oscillator 1 in the spectral region on either side of the carrier frequency to a distance much greater than the FIL reference frequency which would be the crystal (9) frequency divided by counter 8 (probably 41MHz -i- 16 = 25Okhz).

To overcome the Gilbert cells inability to pull the loop A1 into fequency lock, a frequency locked loop A2 is added.

The synthesiser circuit A2 uses a programmable divider 6 to divide a frequency output from the oscillator 1 which frequency output is then compared in a comparator 7 (which is a phase detector which is frequency and edge sensitive) with a reference frequency from a quartz crystal oscillator 10 via another divider 8.

The output from the comparator 7 is fed to an adder 16 via a low pass filter 11 (200 Hz or less).

The voltage controlled oscillator 10 is fed by a reference crystal 9.

Thus, the circuit A2, as so far described, consists essentially of a standard synthesiser loop made up of items 6 to 11 inclusive.

The frequency of the voltage controlled oscillator 1 is controlled by the output from the low pass filter 11 via the adder 16 which also has an input from the wide band filter 3.

A conflict will arise between circuits A1 and A2 as so far described. This is because the circuit A2 will be trying to set the voltage controlled oscillator 1 frequency to a value set by the reference crystal 9, whereas the circuit A1 will 1 1 6 be trying to phase lock the voltage controlled oscillator 1 to the incoming signal at input 4 which would normally be of a somewhat different frequency. In order to resolve this conflict, a further refinement to circuit A2 is provided whereby the frequency of the reference quartz oscillator 10 can be adjusted.

This is achieved by providing a feedback loop, including a further filter 18, to the oscillator 10. The function of this feedback loop is to control the loop 6 to 11, described earlier when it attempts to overcome the loop 1 to 3.

TheCiTCUitrysofardescribed provides an oscillator 1 operating at the same frequency as the incoming signal- Whilst this is suitable for direct conversion receivers (described in more detail in relation to figure 3) it is not suitable where a standard superhet receiver is employed in a TY. timer. This is because the incoming TY. signals have vestigial sideband signals and direct conversion would give noise or unwanted interference from the adjacent channel.

Thus, in order to transform the oscillator 1 operating at the incoming signal frequency to a local oscillator operating at the incoming signal frequency plus or minus the desired IF frequency (normally 38.9 MHz but it could be less), a standard single sideband mixer circuit B is employed.

This consists essentially of two multipliers 12 and 13, each of which comprises a Gilbert cell, which are driven in quadrature by the local oscillator 1 and also in quadrature by an oscillator 14 running at twice the required IF frequency and connected to the two multipliers 12 and 13 via a divider 15.

The outputs from the multipliers 12 and 13 are added at an adder 17 the output of which provides the lower sideband which is connected at output 5 to the standard superhet mixer (not shown).

To summarise, the embodiment shown in figure 1 comprises a wideband width phase locked loop to reduce the spectral noise of a voltage controlled oscillator 7 and lock-in is assured by a frequency synthesiser loop in which the phase and frequency conflict between the two loops are resolved by a modification of a crystal reference oscillator by means of feedback from the synthesiser frequency detector. The resultant "cleaned up" oscillator signal is then transformed to a desired frequency by means of a single sideband mixer.

Referring now to figure 2, circuit 200 illustrates the application of an embodiment of the present invention to a so-called non-zero IF I/Q mixer.

In this embodiment those items which correspond to items in figure 1 have been given the same reference numeral, plus the number one hundred.

In particular figure 2 includes the same circuits Al, A2 and B of figure 1.

The only additional items in the circuit are dividers 19 and 20 and multipliers 21 and 22, the reasons for their inclusion being now described.

In the circuit 200, the ring oscillator 10 1 is run at twice the signal frequency in order to allow later division by 2 for easy quadrature signal generation, whereas in the circuit 100 of figure 1, it is run at the same frequency as the signal frequency. FQ ridying requires local oscillator signals at 90' to each other (Le in quadrature). Divider 20 is a convenient way to obtain quadrature signals but requires a drive at twice the frequency and therefore the preceding frequencies are doubled.

Thus, the output from the ring oscillator 101 is divided by two by divider 19 before it drives the fast loop phase detector 102,103 and slow frequency synthesiser loop 106 to 111 and 118.

The twice signal frequency is then used with a twice IF frequency generator to produce a lower sideband at twice the signal minus twice the IF frequency, this resultant then being divided by two by divider 20 to supply quadrature drives to two multipliers 21,22. Briefly, the operation is as follows.

8 The inputs to the Gilbert cells 112 and 113 from the ring oscillator 101 are at a frequency of twice the signal frequency but 900 out of phase with one another.

The control oscillator 114 operates at four times the IEF frequency so that the output from the divider 115 provides signals to the Gilbert cells 112 and 113 which are at twice the IEF frequency but 90 out of phase with one another.

The output from the adder 117 is a lower sideband frequency which is equal to twice the signal frequency minus twice the IF frequency.

The outputs from the divider 20 to the Gilbert cells 21 and 22 each has a frequency of the signal frequency minus the reference frequency and the outputs from the Gilbert cells 21 and 22 are both equal to the IEF frequency but are 90 out of phase with one another.

Referring now to figure 3, circuit 300 illustrates the application of an embodiment of the present invention to a so-called zero IF receiver, otherwise known as a direct conversion receiver.

Again, items which are equivalent to those already shown in figure 1 have been given the same reference numerals plus the number two hundred and in particular the circuit 300 of figure 3 consists essentially of the circuits A1 and A2 of figure 1.

Because the output from the ring oscillator 201 is to be used with a direct conversionlzero IF receiver, there is no need for the circuit B of figure 1.

In figure 3, the outputs from the Gilbert cells 212 and 213 are indicated as being in quadrature phase at Q and in phase at I respectively.

9 The circuit of the present invention is particularly designed to be manufactured as an integrated circuit.

Although the inclusion of ring oscillator 1, 101, 201 in the circuit would appear to add complication, from an integrated circuit point of view it is easier to produce than an LC type of oscillator and in fact the latter type of oscillator cannot be produced as an integrated circuit in respect of certain applications.

In summary, a system is proposed which uses a wide bandwidth phase locked loop A.1 to reduce the spectral noise of a WO local oscillator 1. Lock-in is ensured by a frequency locked loop circuit A2 in which phase and frequency conflicts between the two loops are resolved by the modification of the crystal reference oscillator of the frequency locked loop circuit by feedback from the loops' frequency detector. The resultant "cleaned up" oscillator signal is substantially independent of the oscillator noise. It may then be transformed to a desired frequency, if necessary.

Claims

1. A local oscillator arrangement comprises:

a) a voltage controlled oscillator incorporated in a phase locked loop circuit having a signal frequency input; b) a ftequency locked loop circuit including a reference crystal oscillator and operable to control the frequency of the voltage controlled oscillator; c) a feedback loop within the frequency locked loop circuit to adjust the reference crystal oscillator to a frequency and phase such that the output from the frequency locked loop agrees with the phase locked loop circuit.

2. A local oscillator arrangement as claimed in Claim 1 in combination with a single sideband mixer circuit comprising a fixed frequency oscillator, a divider circuit to provide quadrature outputs from the fixed frequency oscillator at a required IF frequency to input to two balanced multipliers followed by an adding circuit.

A local oscillator arrangement as claimed in Claim 2 in combination with a further divider circuit coupled to an output of the said adding circuit, the second divider circuit having two outputs to two balanced quadrature multipliers.

A local oscillator arrangement as claimed in Claim 2 in combination with a superhet tuner.

5. A local oscillator arrangement as claimed in Claim 3 in combination with a non-zero IF tuner.

11 6.

A local oscillator arrangement as claimed in Claim 1 in combination with a zero IF/direct conversion tuner.

7.

A local oscillator arrangement as claimed in any previous claim in which the voltage controlled oscillator is a ring oscillator.

8.

A local oscillator arrangement as claimed in any previous claim in which the frequency locked loop circuit includes a Gilbert cell.

9.

A local oscillator arrangement as claimed in any previous claim and formed as an integrated circuit.

10. A tuner for a television receiver incorporating a local oscillator arrangement as claimed in any previous claim.

11. A local oscillator circuit substantially as hereinbefore described with reference to and as shown in any one of figures 1 to 3 of the accompanying drawings.