JPS60193720U - PLL circuit - Google Patents

PLL circuit

Info

Publication number
JPS60193720U
JPS60193720U JP8185984U JP8185984U JPS60193720U JP S60193720 U JPS60193720 U JP S60193720U JP 8185984 U JP8185984 U JP 8185984U JP 8185984 U JP8185984 U JP 8185984U JP S60193720 U JPS60193720 U JP S60193720U
Authority
JP
Japan
Prior art keywords
frequency
pll circuit
local oscillator
loop
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8185984U
Other languages
Japanese (ja)
Other versions
JPH0314826Y2 (en
Inventor
米倉　晴一郎
Original Assignee
株式会社ケンウッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社ケンウッド filed Critical 株式会社ケンウッド
Priority to JP8185984U priority Critical patent/JPS60193720U/en
Publication of JPS60193720U publication Critical patent/JPS60193720U/en
Application granted granted Critical
Publication of JPH0314826Y2 publication Critical patent/JPH0314826Y2/ja
Granted legal-status Critical Current

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のＰＬＬ回路を示すブロック図、第２図は
本考案に係るＰＬＬ回路の実施例を示すブロック図であ
る。 １　：ＶＣｏ、　２　：局部発振器、３：ミクサ、４：
ローパスフィルタ、５：デバイダ、６：位相比較器、７
：基準信号発生部、８：ローパスフィルタ、１０：遅延
回路。FIG. 1 is a block diagram showing a conventional PLL circuit, and FIG. 2 is a block diagram showing an embodiment of the PLL circuit according to the present invention. 1: VCo, 2: Local oscillator, 3: Mixer, 4:
Low-pass filter, 5: Divider, 6: Phase comparator, 7
: reference signal generator, 8: low-pass filter, 10: delay circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ループ内に周波数混合器が含まれていると共にＶＣＯ周
波数が局部発振器の周波数に対して高いか低いかのいず
れか一方の範囲内において可変されるようになっている
ＰＬＬ回路において、上記ＶＣＣ周波数と局部発振器と
の周波数関係が正規となる時間をおいて、局部発振器等
、ループを構成するいずれかのブロックの回路へ電源を
供給するようになっている遅延回路を備えていることを
特徴とするＰＬＬ回路。In a PLL circuit in which a frequency mixer is included in the loop and the VCO frequency is varied within a range of either higher or lower than the local oscillator frequency, the VCC frequency and It is characterized by comprising a delay circuit configured to supply power to the circuit of one of the blocks constituting the loop, such as the local oscillator, after a period of time when the frequency relationship with the local oscillator becomes normal. PLL circuit.
JP8185984U 1984-06-04 1984-06-04 PLL circuit Granted JPS60193720U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8185984U JPS60193720U (en) 1984-06-04 1984-06-04 PLL circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8185984U JPS60193720U (en) 1984-06-04 1984-06-04 PLL circuit

Publications (2)

Publication Number Publication Date
JPS60193720U true JPS60193720U (en) 1985-12-23
JPH0314826Y2 JPH0314826Y2 (en) 1991-04-02

Family

ID=30629038

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8185984U Granted JPS60193720U (en) 1984-06-04 1984-06-04 PLL circuit

Country Status (1)

Country Link
JP (1) JPS60193720U (en)

Also Published As

Publication number Publication date
JPH0314826Y2 (en) 1991-04-02

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