JPS5849285U - timer clock circuit - Google Patents

timer clock circuit

Info

Publication number
JPS5849285U
JPS5849285U JP14515481U JP14515481U JPS5849285U JP S5849285 U JPS5849285 U JP S5849285U JP 14515481 U JP14515481 U JP 14515481U JP 14515481 U JP14515481 U JP 14515481U JP S5849285 U JPS5849285 U JP S5849285U
Authority
JP
Japan
Prior art keywords
frequency
clock circuit
timer clock
phase comparator
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14515481U
Other languages
Japanese (ja)
Inventor
森　省二
Original Assignee
株式会社東芝
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社東芝 filed Critical 株式会社東芝
Priority to JP14515481U priority Critical patent/JPS5849285U/en
Publication of JPS5849285U publication Critical patent/JPS5849285U/en
Pending legal-status Critical Current

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  • Electric Clocks (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のタイマー・クロック回路を示す構成図、
第２図はこの考案の一実施例を示す構成図である。 １６・・・位相比較器、１７・・・電圧制御発振器、１
８・・・分周器。Figure 1 is a configuration diagram showing a conventional timer/clock circuit.
FIG. 2 is a block diagram showing an embodiment of this invention. 16... Phase comparator, 17... Voltage controlled oscillator, 1
8... Frequency divider.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 第１、第２の異なる周波数の信号が一方の入力端に加え
られる位相比較器と、この位相比較器の出力に応じて発
振周波数が制御される発振器であって、前記第１、第２
の周波数の最小公倍数の整数倍の周波数が設定され、こ
の発振周波数を前記位相比較器の他方の入力端にも加え
る電圧制御発振器と、この電圧制御発振器の出力を上記
最小公倍数の整数分の−に分周して基準信号を得る分周
回路とを具備したことを特徴とするタイマー・クロック
回路。a phase comparator to which first and second signals of different frequencies are applied to one input terminal; and an oscillator whose oscillation frequency is controlled according to the output of the phase comparator, the first and second signals having different frequencies.
A voltage controlled oscillator is set with a frequency that is an integer multiple of the least common multiple of the frequency, and this oscillation frequency is also applied to the other input terminal of the phase comparator, and the output of this voltage controlled oscillator is set to a frequency that is an integer multiple of the least common multiple of the frequency. What is claimed is: 1. A timer clock circuit comprising: a frequency dividing circuit that divides the frequency into a reference signal to obtain a reference signal.
JP14515481U 1981-09-30 1981-09-30 timer clock circuit Pending JPS5849285U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14515481U JPS5849285U (en) 1981-09-30 1981-09-30 timer clock circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14515481U JPS5849285U (en) 1981-09-30 1981-09-30 timer clock circuit

Publications (1)

Publication Number Publication Date
JPS5849285U true JPS5849285U (en) 1983-04-02

Family

ID=29938096

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14515481U Pending JPS5849285U (en) 1981-09-30 1981-09-30 timer clock circuit

Country Status (1)

Country Link
JP (1) JPS5849285U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62180104U (en) * 1986-05-08 1987-11-16

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62180104U (en) * 1986-05-08 1987-11-16

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