JPS59104636U - frequency synthesizer - Google Patents
frequency synthesizerInfo
- Publication number
- JPS59104636U JPS59104636U JP20220282U JP20220282U JPS59104636U JP S59104636 U JPS59104636 U JP S59104636U JP 20220282 U JP20220282 U JP 20220282U JP 20220282 U JP20220282 U JP 20220282U JP S59104636 U JPS59104636 U JP S59104636U
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- frequency divider
- variable frequency
- reset
- output signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の一例を示す周波数シンセサイザのブロッ
ク図、第２図は本考案に係る一実施例を示す周波数シン
セサイザのブロック図である。
１・・・発振器、２・・・位相比較器、３・・・低域フ
ィルタ、４・・・電圧制御発振器、５・・・ミクサ、６
Ａ・・・制−両回路、７・・・可変分周器、１０・・・
遅延回路。FIG. 1 is a block diagram of a frequency synthesizer showing a conventional example, and FIG. 2 is a block diagram of a frequency synthesizer showing an embodiment of the present invention. 1... Oscillator, 2... Phase comparator, 3... Low pass filter, 4... Voltage controlled oscillator, 5... Mixer, 6
A... Control circuit, 7... Variable frequency divider, 10...
delay circuit.
Claims (1)
ーカル信号により差分の周波数に変換するミクサと、こ
のミクサの出力信号を分周して位相比較器に入力とする
可変分周器を有し、前記位相比較器にて発振器からの基
準信号と前記可変分周器の出力信号との位相を比較して
その位相差に基いて前記電圧制御発振器の出力周波数を
制御するように構成された位相同期ループを具備した周
５ 波数シンセサイザにおいて、前記可変分周器
のリセット入力に遅延回路を設け、前記制御回路により
ローカル信号を切替えた際に前記遅延回路によって前記
可変分周器を一定時間だけリセットしたのち、該分周器
のリセットを解除するようにしたことを特徴とする周波
数シンセサイザ。It has a mixer that converts the output signal of the voltage controlled oscillator into a differential frequency using a local signal sent from the control circuit, and a variable frequency divider that divides the frequency of the output signal of this mixer and inputs it to the phase comparator, Phase synchronization configured to compare the phases of the reference signal from the oscillator and the output signal of the variable frequency divider in the phase comparator and control the output frequency of the voltage controlled oscillator based on the phase difference. In the frequency 5 wave number synthesizer equipped with a loop, a delay circuit is provided at the reset input of the variable frequency divider, and when the local signal is switched by the control circuit, the variable frequency divider is reset by the delay circuit for a certain period of time. A frequency synthesizer characterized in that the reset of the frequency divider is released later.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20220282U JPS59104636U (en) | 1982-12-28 | 1982-12-28 | frequency synthesizer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20220282U JPS59104636U (en) | 1982-12-28 | 1982-12-28 | frequency synthesizer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59104636U true JPS59104636U (en) | 1984-07-14 |
Family
ID=30427680
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20220282U Pending JPS59104636U (en) | 1982-12-28 | 1982-12-28 | frequency synthesizer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59104636U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7601016B2 (en) | 2007-03-26 | 2009-10-13 | Funai Electric Co., Ltd. | Connector substrate and speaker input terminal connection structure |
-
1982
- 1982-12-28 JP JP20220282U patent/JPS59104636U/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7601016B2 (en) | 2007-03-26 | 2009-10-13 | Funai Electric Co., Ltd. | Connector substrate and speaker input terminal connection structure |
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