JPS61109236U - - Google Patents
Info
- Publication number
- JPS61109236U JPS61109236U JP19413184U JP19413184U JPS61109236U JP S61109236 U JPS61109236 U JP S61109236U JP 19413184 U JP19413184 U JP 19413184U JP 19413184 U JP19413184 U JP 19413184U JP S61109236 U JPS61109236 U JP S61109236U
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- frequency divider
- comparator
- controlled oscillator
- voltage controlled
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
第1図はPLL回路の一般例を示すブロツク図
、第2図は本考案との比較における従来例のブロ
ツク図、第3図は従来例の信号のタイミングチヤ
ート、第4図は本考案に係る信号のタイミングチ
ヤート、第5図は本考案の一実施例を示すブロツ
ク図である。
11……分周器、12……コンパレータ、13
……ローパスフイルタ、14……電圧制御発振器
、15……ラツチ回路、11′……分周器。
Fig. 1 is a block diagram showing a general example of a PLL circuit, Fig. 2 is a block diagram of a conventional example in comparison with the present invention, Fig. 3 is a signal timing chart of the conventional example, and Fig. 4 is a diagram related to the present invention. FIG. 5 is a block diagram showing an embodiment of the present invention. 11... Frequency divider, 12... Comparator, 13
...Low pass filter, 14...Voltage controlled oscillator, 15...Latch circuit, 11'... Frequency divider.
Claims (1)
し、その出力をコンパレータで基準周波数と位相
比較するようにしたものにおいて、上記コンパレ
ータと分周器との間にラツチ回路を設け、また上
記電圧制御発振器の周波数を1/M分周する分周
器を具備し、上記分周器の1/M分周した周波数
を上記ラツチ回路のクロツク入力としたことを特
徴とするPLL回路。 The frequency of the voltage controlled oscillator is divided by 1/N by a frequency divider, and the output thereof is phase-compared with a reference frequency by a comparator, and a latch circuit is provided between the comparator and the frequency divider, and A PLL circuit comprising a frequency divider that divides the frequency of the voltage controlled oscillator by 1/M, and the frequency obtained by dividing the frequency of the frequency divider by 1/M is used as a clock input of the latch circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1984194131U JPH0422575Y2 (en) | 1984-12-20 | 1984-12-20 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1984194131U JPH0422575Y2 (en) | 1984-12-20 | 1984-12-20 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS61109236U true JPS61109236U (en) | 1986-07-10 |
JPH0422575Y2 JPH0422575Y2 (en) | 1992-05-25 |
Family
ID=30751568
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1984194131U Expired JPH0422575Y2 (en) | 1984-12-20 | 1984-12-20 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0422575Y2 (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6032838U (en) * | 1983-08-12 | 1985-03-06 | 横河電機株式会社 | PLL circuit |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6032838B2 (en) * | 1978-10-31 | 1985-07-30 | 松下電器産業株式会社 | Dynamic beat generation circuit for electronic metronome |
-
1984
- 1984-12-20 JP JP1984194131U patent/JPH0422575Y2/ja not_active Expired
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6032838U (en) * | 1983-08-12 | 1985-03-06 | 横河電機株式会社 | PLL circuit |
Also Published As
Publication number | Publication date |
---|---|
JPH0422575Y2 (en) | 1992-05-25 |
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