JPH01177616U - - Google Patents
Info
- Publication number
- JPH01177616U JPH01177616U JP7253888U JP7253888U JPH01177616U JP H01177616 U JPH01177616 U JP H01177616U JP 7253888 U JP7253888 U JP 7253888U JP 7253888 U JP7253888 U JP 7253888U JP H01177616 U JPH01177616 U JP H01177616U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- frequency
- signal
- phase difference
- difference detection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010355 oscillation Effects 0.000 claims description 5
- 238000001514 detection method Methods 0.000 claims description 4
- 230000001360 synchronised effect Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
第１図は本考案による同期発振回路の一実施例
を示すブロツク図、第２図は従来回路を示すブロ
ツク図である。
２……位相差検出回路、３……ループフイルタ
回路、４……電圧制御型発振回路、１０……分周
回路、１１……分周比設定回路。
FIG. 1 is a block diagram showing an embodiment of a synchronous oscillation circuit according to the present invention, and FIG. 2 is a block diagram showing a conventional circuit. 2... Phase difference detection circuit, 3... Loop filter circuit, 4... Voltage controlled oscillation circuit, 10... Frequency dividing circuit, 11... Frequency division ratio setting circuit.
Claims (1)
を位相差検出回路によつて検出し、この位相差検
出信号をループフイルタ回路を介して直流信号に
変換して電圧制御型発振回路に与え、出力発振信
号を形成すると共に、この出力発振信号を上記分
周回路によつて分周して上記位相差検出回路にフ
イードバツクする同期発振回路において、 上記分周回路として可変分周回路を用いると共
に、 上記ループフイルタ回路からの直流信号を入力
し、上記入力信号の周波数成分に拘らず、上記電
圧制御型発振回路に対する直流信号が一定値をと
るように上記分周回路の分周比を制御する分周比
設定回路を設けたことを特徴とする同期発振回路
。[Claims for Utility Model Registration] The phase difference between the input signal and the frequency-divided signal from the frequency divider circuit is detected by a phase difference detection circuit, and this phase difference detection signal is converted into a DC signal via a loop filter circuit. In the synchronous oscillation circuit, the frequency of the output oscillation signal is divided by the frequency dividing circuit and fed back to the phase difference detection circuit. A variable frequency divider circuit is used as the circuit, and the DC signal from the loop filter circuit is input, and the DC signal to the voltage controlled oscillator circuit is set to a constant value regardless of the frequency component of the input signal. A synchronous oscillation circuit comprising a frequency division ratio setting circuit for controlling a frequency division ratio of a frequency circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7253888U JPH01177616U (en) | 1988-05-31 | 1988-05-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7253888U JPH01177616U (en) | 1988-05-31 | 1988-05-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01177616U true JPH01177616U (en) | 1989-12-19 |
Family
ID=31297698
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7253888U Pending JPH01177616U (en) | 1988-05-31 | 1988-05-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01177616U (en) |
-
1988
- 1988-05-31 JP JP7253888U patent/JPH01177616U/ja active Pending