JPS63140742U - - Google Patents

Info

Publication number
JPS63140742U
JPS63140742U JP3195387U JP3195387U JPS63140742U JP S63140742 U JPS63140742 U JP S63140742U JP 3195387 U JP3195387 U JP 3195387U JP 3195387 U JP3195387 U JP 3195387U JP S63140742 U JPS63140742 U JP S63140742U
Authority
JP
Japan
Prior art keywords
output
voltage
intermediate frequency
circuit
frequency signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3195387U
Other languages
Japanese (ja)
Other versions
JPH0546360Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987031953U priority Critical patent/JPH0546360Y2/ja
Publication of JPS63140742U publication Critical patent/JPS63140742U/ja
Application granted granted Critical
Publication of JPH0546360Y2 publication Critical patent/JPH0546360Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Superheterodyne Receivers (AREA)
  • Noise Elimination (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例の構成を示すブロツ
ク図、第2図は本考案の一実施例の作用の説明に
供する線図、第3図は従来のアナログチユーナの
場合の作用説明に供する線図である。 1および3……混合回路、2および4……帯域
フイルタ、5……検波器、6……ローパスフイル
タ、7……電圧制御発振器、8……加算器、9…
…直流オフセツト電圧。
Fig. 1 is a block diagram showing the configuration of an embodiment of the present invention, Fig. 2 is a diagram explaining the operation of an embodiment of the invention, and Fig. 3 is an explanation of the operation in the case of a conventional analog tuner. FIG. 1 and 3...Mixing circuit, 2 and 4...Band filter, 5...Detector, 6...Low pass filter, 7...Voltage controlled oscillator, 8...Adder, 9...
...DC offset voltage.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] フロントエンドからの中間周波信号を入力する
第1混合回路と、第1混合回路の出力を選択度回
路を介して入力する第2混合回路と、フロントエ
ンドからの中間周波信号を入力とする中間周波選
択度回路と、中間周波選択度回路の出力を検波す
る検波器と、検波器の出力を入力するローパスフ
イルタと、直流バイアス電圧源の電圧とローパス
フイルタからの電圧を加算する加算器と、加算器
の出力を制御電圧とし、かつ発振出力を第1およ
び第2混合回路に供給する電圧制御発振器とを備
え、第1混合回路の出力の周波数を中間周波信号
周波数からずらし、このずらされた周波数を第2
混合回路で補償して第2混合回路の出力の周波数
を中間周波信号波数に戻すようにしたことを特徴
とするシンセサイザチユーナ。
a first mixing circuit into which the intermediate frequency signal from the front end is input; a second mixing circuit into which the output of the first mixing circuit is input via the selectivity circuit; and an intermediate frequency signal into which the intermediate frequency signal from the front end is input. A selectivity circuit, a detector that detects the output of the intermediate frequency selectivity circuit, a low-pass filter that inputs the output of the detector, an adder that adds the voltage of the DC bias voltage source and the voltage from the low-pass filter, and an adder that adds the voltage of the DC bias voltage source and the voltage from the low-pass filter. a voltage-controlled oscillator that uses the output of the device as a control voltage and supplies the oscillation output to the first and second mixing circuits; the frequency of the output of the first mixing circuit is shifted from the intermediate frequency signal frequency; the second
A synthesizer tuner characterized in that the frequency of the output of the second mixing circuit is returned to the intermediate frequency signal wave number by compensation with a mixing circuit.
JP1987031953U 1987-03-06 1987-03-06 Expired - Lifetime JPH0546360Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987031953U JPH0546360Y2 (en) 1987-03-06 1987-03-06

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987031953U JPH0546360Y2 (en) 1987-03-06 1987-03-06

Publications (2)

Publication Number Publication Date
JPS63140742U true JPS63140742U (en) 1988-09-16
JPH0546360Y2 JPH0546360Y2 (en) 1993-12-03

Family

ID=30838168

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987031953U Expired - Lifetime JPH0546360Y2 (en) 1987-03-06 1987-03-06

Country Status (1)

Country Link
JP (1) JPH0546360Y2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57155840A (en) * 1981-03-20 1982-09-27 Trio Kenwood Corp Distortion reducing circuit
JPS61256830A (en) * 1985-05-09 1986-11-14 Maspro Denkoh Corp Interference wave eliminating device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57155840A (en) * 1981-03-20 1982-09-27 Trio Kenwood Corp Distortion reducing circuit
JPS61256830A (en) * 1985-05-09 1986-11-14 Maspro Denkoh Corp Interference wave eliminating device

Also Published As

Publication number Publication date
JPH0546360Y2 (en) 1993-12-03

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