JPS62158943U - - Google Patents
Info
- Publication number
- JPS62158943U JPS62158943U JP4698986U JP4698986U JPS62158943U JP S62158943 U JPS62158943 U JP S62158943U JP 4698986 U JP4698986 U JP 4698986U JP 4698986 U JP4698986 U JP 4698986U JP S62158943 U JPS62158943 U JP S62158943U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- local oscillation
- signal
- frequency
- intermediate frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010355 oscillation Effects 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Superheterodyne Receivers (AREA)
Description
第1図は本考案によるPLLシンセサイザチユ
ーナの実施例を示す回路構成図、第2図は局部発
振回路からの出力波形を示す線図、第3図は従来
のPLLシンセサイザチユーナの回路構成図であ
る。
1…アンテナ端子、5…混合回路、6…局部発
振回路、8…プリスケーラ、20…トラツプ。
Fig. 1 is a circuit diagram showing an embodiment of a PLL synthesizer tuner according to the present invention, Fig. 2 is a diagram showing an output waveform from a local oscillation circuit, and Fig. 3 is a circuit diagram of a conventional PLL synthesizer tuner. It is. 1... Antenna terminal, 5... Mixing circuit, 6... Local oscillation circuit, 8... Prescaler, 20... Trap.
Claims (1)
る同調回路と、 同調された入力信号と局部発振回路から出力さ
れる局部発振信号とをミキシングして両信号の周
波数の差となる中間周波数の信号を出力する混合
回路と、 前記局部発振回路の周波数を制御入力に応じて
分周する回路が設けられており、 前記局部発振回路と、制御入力に応じて分周す
る回路との間に、前記中間周波数の信号のトラツ
プが設けられて成るPLLシンセサイザチユーナ
。[Claim for Utility Model Registration] A tuning circuit that tunes an input signal received from an antenna terminal, and a tuning circuit that mixes the tuned input signal and a local oscillation signal output from a local oscillation circuit to generate a difference in the frequency of both signals. a mixing circuit that outputs a signal with an intermediate frequency, and a circuit that divides the frequency of the local oscillation circuit according to a control input; the local oscillation circuit and a circuit that divides the frequency according to the control input; A PLL synthesizer tuner comprising: a trap for the intermediate frequency signal provided between the PLL synthesizer tuner and the intermediate frequency signal;
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4698986U JPS62158943U (en) | 1986-03-28 | 1986-03-28 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4698986U JPS62158943U (en) | 1986-03-28 | 1986-03-28 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62158943U true JPS62158943U (en) | 1987-10-08 |
Family
ID=30867167
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4698986U Pending JPS62158943U (en) | 1986-03-28 | 1986-03-28 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62158943U (en) |
-
1986
- 1986-03-28 JP JP4698986U patent/JPS62158943U/ja active Pending
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