JPS6444730U - - Google Patents

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Publication number
JPS6444730U
JPS6444730U JP13903387U JP13903387U JPS6444730U JP S6444730 U JPS6444730 U JP S6444730U JP 13903387 U JP13903387 U JP 13903387U JP 13903387 U JP13903387 U JP 13903387U JP S6444730 U JPS6444730 U JP S6444730U
Authority
JP
Japan
Prior art keywords
frequency
circuit
local oscillation
generates
phase comparator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13903387U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP13903387U priority Critical patent/JPS6444730U/ja
Publication of JPS6444730U publication Critical patent/JPS6444730U/ja
Pending legal-status Critical Current

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  • Superheterodyne Receivers (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案の一実施例示す周波数シンセ
サイザチユーナの回路図、第2図はこの考案に用
いられる逓信器の具体的構成を示す回路図、第3
図は第2図に示した逓信器の入出力波形図、第4
図はこの考案による他の実施例を示す回路図、第
5図は従来の周波数シンセサイザチユーナの構成
を示す回路図である。 1……周波数変換器、2……局部発振回路、3
……可変分周回路、4……位相比較器、5……基
準周波数発生回路、6……ループフイルタ、7,
8……逓信器、9……切換回路。
Fig. 1 is a circuit diagram of a frequency synthesizer tuner showing one embodiment of this invention, Fig. 2 is a circuit diagram showing a specific configuration of a transmitter used in this invention, and Fig. 3 is a circuit diagram showing a specific configuration of a transmitter used in this invention.
The figure is the input/output waveform diagram of the transmitter shown in Figure 2, and
The figure is a circuit diagram showing another embodiment of this invention, and FIG. 5 is a circuit diagram showing the configuration of a conventional frequency synthesizer tuner. 1... Frequency converter, 2... Local oscillation circuit, 3
... variable frequency divider circuit, 4 ... phase comparator, 5 ... reference frequency generation circuit, 6 ... loop filter, 7,
8... Transmitter, 9... Switching circuit.

Claims (1)

【実用新案登録請求の範囲】 チユーニング電圧に応じた周波数で発振する局
部発振回路と、受信周波数に応じた分周化で分周
する可変分周回路と、基準周波数を発生する回路
と、分周出力と基準周波数との位相を比較して誤
差分を出力する位相比較器と、位相比較器の誤差
出力からチユーニング電圧を発生する回路とを備
え、 前記局部発振回路と可変分周回路との間に周波
数逓倍器を有することを特徴とする周波数シンセ
サイザチユーナ。
[Claims for Utility Model Registration] A local oscillation circuit that oscillates at a frequency that corresponds to the tuning voltage, a variable frequency divider circuit that divides the frequency according to the received frequency, a circuit that generates a reference frequency, and a frequency divider. A phase comparator that compares the phase between the output and a reference frequency and outputs an error, and a circuit that generates a tuning voltage from the error output of the phase comparator, and is connected between the local oscillation circuit and the variable frequency divider circuit. A frequency synthesizer tuner comprising a frequency multiplier.
JP13903387U 1987-09-11 1987-09-11 Pending JPS6444730U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13903387U JPS6444730U (en) 1987-09-11 1987-09-11

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13903387U JPS6444730U (en) 1987-09-11 1987-09-11

Publications (1)

Publication Number Publication Date
JPS6444730U true JPS6444730U (en) 1989-03-17

Family

ID=31401916

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13903387U Pending JPS6444730U (en) 1987-09-11 1987-09-11

Country Status (1)

Country Link
JP (1) JPS6444730U (en)

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