JPS63187487U - - Google Patents
Info
- Publication number
- JPS63187487U JPS63187487U JP7917087U JP7917087U JPS63187487U JP S63187487 U JPS63187487 U JP S63187487U JP 7917087 U JP7917087 U JP 7917087U JP 7917087 U JP7917087 U JP 7917087U JP S63187487 U JPS63187487 U JP S63187487U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- receives
- signal
- output signal
- phase comparison
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 230000010363 phase shift Effects 0.000 claims 1
- 238000003786 synthesis reaction Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Processing Of Color Television Signals (AREA)
Description
第１図は、本考案の回路図、第２図は、第１図
の２逓倍回路の回路図である。
１……基準信号入力、２……サンプルパルス入
力、３……位相比較回路、４……ｎ逓倍電圧制御
発振器ＶＣＯ、５……２逓倍回路、６……出力端
子、７……１／２ｎ倍分周回路。
FIG. 1 is a circuit diagram of the present invention, and FIG. 2 is a circuit diagram of the doubler circuit of FIG. 1. 1...Reference signal input, 2...Sample pulse input, 3...Phase comparison circuit, 4...N multiplication voltage control oscillator VCO, 5...2 multiplication circuit, 6...Output terminal, 7...1/2n Double frequency divider circuit.
Claims (1)
入力とを有するバランスモジレータで構成された
位相比較回路と、位相比較回路の出力信号を受け
る所望のｎ（ｎ＝２，３，４）逓倍周波数の電圧
制御発振器ＶＣＯと、ＶＣＯの出力信号を受ける
位相シフト合成型２逓倍回路と、２逓倍回路の出
力信号を受ける１／２ｎ倍分周回路及び出力端子
とを具備し、前記分周回路の出力信号を前記位相
比較回路の比較信号とすることを特徴とするバー
ストコントロールオシレータ回路。 A phase comparison circuit composed of a balance modulator having a reference signal input, a comparison signal input, and a sample pulse input, and a voltage at a desired n (n=2, 3, 4) multiplication frequency that receives the output signal of the phase comparison circuit. It comprises a controlled oscillator VCO, a phase shift synthesis type doubler circuit that receives an output signal of the VCO, a 1/2n frequency divider circuit that receives an output signal of the doubler circuit, and an output terminal, and the output terminal of the frequency divider circuit. is used as a comparison signal of the phase comparison circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7917087U JPS63187487U (en) | 1987-05-25 | 1987-05-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7917087U JPS63187487U (en) | 1987-05-25 | 1987-05-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63187487U true JPS63187487U (en) | 1988-11-30 |
Family
ID=30928781
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7917087U Pending JPS63187487U (en) | 1987-05-25 | 1987-05-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63187487U (en) |
-
1987
- 1987-05-25 JP JP7917087U patent/JPS63187487U/ja active Pending