JPH0467823U - - Google Patents
Info
- Publication number
- JPH0467823U JPH0467823U JP11093290U JP11093290U JPH0467823U JP H0467823 U JPH0467823 U JP H0467823U JP 11093290 U JP11093290 U JP 11093290U JP 11093290 U JP11093290 U JP 11093290U JP H0467823 U JPH0467823 U JP H0467823U
- Authority
- JP
- Japan
- Prior art keywords
- phase
- clock pulse
- reference clock
- pll
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
第１図は本考案のＰＬＬ回路の一実施例を示す
ブロツク図、第２図はａ，ｂは本実施例における
各部の波形例を示す図、第３図は従来のＰＬＬ回
路の一例を示すブロツク図である。
１……入力端子、２……位相比較器（ＰＣＡ）
、３……リミツタ増幅器（ＬＩＭ）、４，１０…
…低域フイルタ（ＬＰＦ）、５，１１……増幅器
（ＡＭＰ）、６……電圧制御発振器（ＶＣＯ）、
７……出力端子、８……Ｎ分周回路（１／Ｎ）、
９……位相比較器（ＰＣＢ）、１２……位相変換
回路（ＰＳＨ）。
Fig. 1 is a block diagram showing an embodiment of the PLL circuit of the present invention, Fig. 2 is a diagram showing waveform examples of each part in this embodiment, and Fig. 3 is an example of a conventional PLL circuit. It is a block diagram. 1...Input terminal, 2...Phase comparator (PCA)
, 3... limiter amplifier (LIM), 4, 10...
...Low pass filter (LPF), 5, 11...Amplifier (AMP), 6...Voltage controlled oscillator (VCO),
7...Output terminal, 8...N frequency divider circuit (1/N),
9... Phase comparator (PCB), 12... Phase conversion circuit (PSH).
Claims (1)
力から作成したクロツクパルスとを比較してその
位相差を監視する位相比較器と、前記位相差に応
じて発生させた誤差電圧により前記入力基準クロ
ツクパルスの位相を前記誤差電圧に応じた位相に
変換する位相変換回路とを備え、前記位相変換さ
れたクロツクパルスを基準クロツクパルスとして
ＰＬＬループを構成することを特徴とするＰＬＬ
回路。 a phase comparator that compares an input reference clock pulse with a clock pulse created from the output of a voltage controlled oscillator and monitors the phase difference; A PLL, comprising: a phase conversion circuit that converts a phase according to a voltage; and a PLL loop is configured using the phase-converted clock pulse as a reference clock pulse.
circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11093290U JPH0467823U (en) | 1990-10-23 | 1990-10-23 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11093290U JPH0467823U (en) | 1990-10-23 | 1990-10-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0467823U true JPH0467823U (en) | 1992-06-16 |
Family
ID=31858336
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11093290U Pending JPH0467823U (en) | 1990-10-23 | 1990-10-23 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0467823U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002509415A (en) * | 1998-01-14 | 2002-03-26 | インテル・コーポレーション | Self-compensating phase detector |
-
1990
- 1990-10-23 JP JP11093290U patent/JPH0467823U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002509415A (en) * | 1998-01-14 | 2002-03-26 | インテル・コーポレーション | Self-compensating phase detector |