JPH0478828U - - Google Patents
Info
- Publication number
- JPH0478828U JPH0478828U JP12083490U JP12083490U JPH0478828U JP H0478828 U JPH0478828 U JP H0478828U JP 12083490 U JP12083490 U JP 12083490U JP 12083490 U JP12083490 U JP 12083490U JP H0478828 U JPH0478828 U JP H0478828U
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- frequency
- controlled oscillator
- converter
- low
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 1
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
第１図はこの考案の実施例のＰＬＬ回路のブロ
ツク図、第２図はＰＬＬロツク時のアツプ／ダウ
ンカウンタ７の出力変化を示す図である。
１は基準発振回路、２，３は分周器、４は位相
比較回路、５はＯＲゲート回路、６はＡＮＤゲー
ト回路、７はアツプ／ダウンカウンタ、８はデジ
タル・アナログコンバータ（ＤＡＣ）、９は低域
通過ろ波器、１０は電圧制御発振器（ＶＣＯ）、
１１は分周器である。
FIG. 1 is a block diagram of a PLL circuit according to an embodiment of this invention, and FIG. 2 is a diagram showing changes in the output of the up/down counter 7 when the PLL is locked. 1 is a reference oscillation circuit, 2 and 3 are frequency dividers, 4 is a phase comparison circuit, 5 is an OR gate circuit, 6 is an AND gate circuit, 7 is an up/down counter, 8 is a digital-to-analog converter (DAC), 9 is a low-pass filter, 10 is a voltage controlled oscillator (VCO),
11 is a frequency divider.
Claims (1)
数との位相差に比例する時間幅の進み又は遅れ位
相を示すパルス信号を出力する位相比較器と、 このパルス信号に応じて前記基準周波数よりも
充分に高い周波数のクロツク信号でアツプ／ダウ
ンするアツプ／ダウンカウンタと、 このアツプ／ダウンカウンタの出力をアナログ
信号に変換するＤ／Ａ変換器と、 このアナログ信号を比較的高いカツトオフ周波
数で低域通過ろ波して前記電圧制御発振器に帰還
する低域通過ろ波器とを備えたことを特徴とする
ＰＬＬ回路。[Claims for Utility Model Registration] A voltage-controlled oscillator that oscillates in accordance with a control voltage, and outputs a pulse signal that indicates a lead or lag phase with a time width that is proportional to the phase difference between the frequency based on this voltage-controlled oscillator and a reference frequency. an up/down counter that goes up/down with a clock signal of a frequency sufficiently higher than the reference frequency in response to this pulse signal; and a D/D converter that converts the output of this up/down counter into an analog signal. A PLL circuit comprising: an A converter; and a low-pass filter that low-pass filters the analog signal at a relatively high cutoff frequency and feeds it back to the voltage controlled oscillator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12083490U JPH0478828U (en) | 1990-11-20 | 1990-11-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12083490U JPH0478828U (en) | 1990-11-20 | 1990-11-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0478828U true JPH0478828U (en) | 1992-07-09 |
Family
ID=31868721
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12083490U Pending JPH0478828U (en) | 1990-11-20 | 1990-11-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0478828U (en) |
-
1990
- 1990-11-20 JP JP12083490U patent/JPH0478828U/ja active Pending
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