JPS6185934U - - Google Patents
Info
- Publication number
- JPS6185934U JPS6185934U JP17027384U JP17027384U JPS6185934U JP S6185934 U JPS6185934 U JP S6185934U JP 17027384 U JP17027384 U JP 17027384U JP 17027384 U JP17027384 U JP 17027384U JP S6185934 U JPS6185934 U JP S6185934U
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- controlled oscillator
- phase
- locked loop
- programmable counter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010355 oscillation Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 5
- 230000001052 transient effect Effects 0.000 description 1
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
第１図は本考案の一実施例を示す回路図、第２
図は第１図の各部波形図、第３図は従来の回路図
、第４図はＶＣＯの制御電圧の過渡応答波形図、
第５図は第３図の各部波形図である。
１……基準周波数発振器、２……位相比較器、
３……プログラマブルカウンタ、３Ａ……バツフ
ア、４……ＶＣＯ、５……チヤージポンプ、６…
…ローパスフイルタ、７……信号発生器、８……
加算器。
Figure 1 is a circuit diagram showing one embodiment of the present invention;
The figure is a waveform diagram of each part of Figure 1, Figure 3 is a conventional circuit diagram, Figure 4 is a transient response waveform diagram of the control voltage of the VCO,
FIG. 5 is a waveform diagram of each part of FIG. 3. 1... Reference frequency oscillator, 2... Phase comparator,
3...Programmable counter, 3A...Buffer, 4...VCO, 5...Charge pump, 6...
...Low pass filter, 7...Signal generator, 8...
Adder.
Claims (1)
ジポンプとローパスフイルタと電圧制御発振器と
によつて位相同期ループを構成し、前記電圧制御
発振器の出力部からプログラマブルカウンタの計
数入力部に至る経路に、該電圧制御発振器の発振
停止周波数よりも低い周波数で該電圧制御発振器
の発振出力相当の振幅よりも低く、かつ、ノイズ
レベルより高いレベルの信号を重畳させる信号発
生器を設けたことを特徴とするＰＬＬ方式の周波
数シンセサイザ。 A phase-locked loop is constituted by a programmable counter, a phase comparator, a charge pump, a low-pass filter, and a voltage-controlled oscillator, and a path from the output section of the voltage-controlled oscillator to the counting input section of the programmable counter includes a phase-locked loop of the voltage-controlled oscillator. A PLL frequency synthesizer characterized by being provided with a signal generator that superimposes a signal at a frequency lower than the oscillation stop frequency, lower than the amplitude equivalent to the oscillation output of the voltage controlled oscillator, and higher than the noise level. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17027384U JPS6185934U (en) | 1984-11-09 | 1984-11-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17027384U JPS6185934U (en) | 1984-11-09 | 1984-11-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6185934U true JPS6185934U (en) | 1986-06-05 |
Family
ID=30727981
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17027384U Pending JPS6185934U (en) | 1984-11-09 | 1984-11-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6185934U (en) |
-
1984
- 1984-11-09 JP JP17027384U patent/JPS6185934U/ja active Pending
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