JPH0228144U - - Google Patents
Info
- Publication number
- JPH0228144U JPH0228144U JP10716188U JP10716188U JPH0228144U JP H0228144 U JPH0228144 U JP H0228144U JP 10716188 U JP10716188 U JP 10716188U JP 10716188 U JP10716188 U JP 10716188U JP H0228144 U JPH0228144 U JP H0228144U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output
- pulse width
- charge pump
- switching gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001514 detection method Methods 0.000 claims description 3
- 230000010355 oscillation Effects 0.000 claims 4
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
第１図は、本考案の実施例を示すブロツク図、
第２図は、従来例を示すブロツク図である。
９……位相比較回路、１０……チヤージポンプ
回路、１１……ＬＰＦ、１２……アンロツク検出
回路、１３……副チヤージポンプ回路。
FIG. 1 is a block diagram showing an embodiment of the present invention;
FIG. 2 is a block diagram showing a conventional example. 9... Phase comparison circuit, 10... Charge pump circuit, 11... LPF, 12... Unlock detection circuit, 13... Sub charge pump circuit.
Claims (1)
バイダと、 電圧制御発振回路（ＶＣＯ）と、該ＶＣＯの発
振出力を分周するプログラマブルデイバイダと、 前記リフアレンスデイバイダの出力と前記プロ
グラマブルデイバイダの各々の出力の位相差を比
較する位相比較回路と、 該位相比較回路の出力に接続されたチヤージポ
ンプ回路と、 該チヤージポンプ回路の出力を平滑し前記ＶＣ
Ｏの制御電圧を発生するローパスフイルタ（ＬＰ
Ｆ）と、 前記位相比較回路の出力が所定のパルス幅以上
になつたことを検出してアンロツク信号を出力す
るアンロツク検出回路と、 から構成されるＰＬＬ回路において、前記アンロ
ツク検出回路は、 異なつた周波数の複数のクロツクパルスのいず
れかを選択的に出力する切り替えゲートと、 該切り替えゲートから出力されたクロツクパル
スが印加され、該クロツクパルスのパルス幅を基
準に前記位相比較回路の出力パルス幅の弁別をす
るパルス幅弁別回路から構成されることを特徴と
するＰＬＬ回路。 (2) 請求項第１項記載のＰＬＬ回路において、 前記パルス幅弁別回路は、前記切り替えゲート
の出力がクロツク入力に印加され、前記位相比較
回路の出力がＤ入力に印加されたＤフリツプフロ
ツプで構成されることを特徴とするＰＬＬ回路。 (3) 請求項第１項記載のＰＬＬ回路において、 前記位相比較回路の出力に接続された副チヤー
ジポンプ回路を設け、該副チヤージポンプ回路は
、前記パルス幅弁別回路に前記切り替えゲートが
パルス幅の短いクロツクパルスの選択出力と同時
に動作されることを特徴とするＰＬＬ回路。[Claims for Utility Model Registration] (1) A reference divider that divides the frequency of a reference oscillation signal, a voltage controlled oscillation circuit (VCO), a programmable divider that divides the oscillation output of the VCO, and the reference divider that divides the frequency of the reference oscillation signal. a phase comparison circuit that compares the phase difference between the output of the divider and the output of each of the programmable dividers; a charge pump circuit connected to the output of the phase comparison circuit; and a charge pump circuit that smoothes the output of the charge pump circuit and compares the output of the VC
A low pass filter (LP
F); and an unlock detection circuit that detects that the output of the phase comparison circuit exceeds a predetermined pulse width and outputs an unlock signal, in which the unlock detection circuit has different features. a switching gate that selectively outputs one of a plurality of clock pulses of different frequencies; and the clock pulse output from the switching gate is applied, and the output pulse width of the phase comparator circuit is discriminated based on the pulse width of the clock pulse. A PLL circuit comprising a pulse width discrimination circuit. (2) In the PLL circuit according to claim 1, the pulse width discrimination circuit is constituted by a D flip-flop in which the output of the switching gate is applied to a clock input, and the output of the phase comparison circuit is applied to a D input. A PLL circuit characterized in that: (3) The PLL circuit according to claim 1, further comprising a sub-charge pump circuit connected to the output of the phase comparator circuit, and the sub-charge pump circuit is connected to the pulse width discrimination circuit so that the switching gate has a short pulse width. A PLL circuit characterized in that it is operated simultaneously with selective output of a clock pulse.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988107161U JPH0546357Y2 (en) | 1988-08-12 | 1988-08-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988107161U JPH0546357Y2 (en) | 1988-08-12 | 1988-08-12 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0228144U true JPH0228144U (en) | 1990-02-23 |
| JPH0546357Y2 JPH0546357Y2 (en) | 1993-12-03 |
Family
ID=31341326
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988107161U Expired - Lifetime JPH0546357Y2 (en) | 1988-08-12 | 1988-08-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0546357Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04127719A (en) * | 1990-09-19 | 1992-04-28 | Nec Corp | Pll circuit |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61134125A (en) * | 1984-12-05 | 1986-06-21 | Mitsubishi Electric Corp | Lock detecting circuit of frequency synthesizer system channel selecting device |
-
1988
- 1988-08-12 JP JP1988107161U patent/JPH0546357Y2/ja not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61134125A (en) * | 1984-12-05 | 1986-06-21 | Mitsubishi Electric Corp | Lock detecting circuit of frequency synthesizer system channel selecting device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04127719A (en) * | 1990-09-19 | 1992-04-28 | Nec Corp | Pll circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0546357Y2 (en) | 1993-12-03 |
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