JPS6330021U - - Google Patents

Info

Publication number
JPS6330021U
JPS6330021U JP12116686U JP12116686U JPS6330021U JP S6330021 U JPS6330021 U JP S6330021U JP 12116686 U JP12116686 U JP 12116686U JP 12116686 U JP12116686 U JP 12116686U JP S6330021 U JPS6330021 U JP S6330021U
Authority
JP
Japan
Prior art keywords
circuit
output
shift register
pll
inputs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12116686U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP12116686U priority Critical patent/JPS6330021U/ja
Publication of JPS6330021U publication Critical patent/JPS6330021U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の実施例を示すブロツク図、第
2図及び第3図は従来例を示すブロツク図である
。 10……カウンタ、12……シフトレジスタ、
16……可変分周回路、18……基準分周回路、
19……位相比較回路、21……アンロツク検出
回路、22……切換ゲート回路。
FIG. 1 is a block diagram showing an embodiment of the present invention, and FIGS. 2 and 3 are block diagrams showing conventional examples. 10...Counter, 12...Shift register,
16...Variable frequency divider circuit, 18...Reference frequency divider circuit,
19...Phase comparison circuit, 21...Unlock detection circuit, 22...Switching gate circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 中間周波数信号を入力し所定期間そのパルスを
計数する計数回路と、該計数回路の計数データを
入力し外部にシリアル転送するシフトレジスタと
、該シフトレジスタの動作を制御する制御信号と
、2個の分周回路からの分周出力の位相比較を行
い電圧制御発振回路の発振周波数を制御するPL
L回路と、該PLL回路のアンロツク状態を検出
するアンロツク検出回路とを備えたPLL周波数
シンセサイザ用ICに於いて、前記シフトレジス
タの出力と前記アンロツク検出回路の検出出力が
印加され、前記シフトレジスタの動作を制御する
制御信号によつて制御される切換ゲート回路を設
け、該切換ゲート回路の出力が一個の外部端子を
介して出力されることを特徴とするPLL周波数
シンセサイザ用IC。
A counting circuit that inputs an intermediate frequency signal and counts its pulses for a predetermined period, a shift register that inputs the count data of the counting circuit and serially transfers it to the outside, and a control signal that controls the operation of the shift register. PL that compares the phase of the divided output from the frequency dividing circuit and controls the oscillation frequency of the voltage controlled oscillator circuit.
In a PLL frequency synthesizer IC that includes an L circuit and an unlock detection circuit that detects the unlock state of the PLL circuit, the output of the shift register and the detection output of the unlock detection circuit are applied, and the output of the shift register is applied. 1. An IC for a PLL frequency synthesizer, comprising a switching gate circuit whose operation is controlled by a control signal, and an output of the switching gate circuit is outputted through one external terminal.
JP12116686U 1986-08-07 1986-08-07 Pending JPS6330021U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12116686U JPS6330021U (en) 1986-08-07 1986-08-07

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12116686U JPS6330021U (en) 1986-08-07 1986-08-07

Publications (1)

Publication Number Publication Date
JPS6330021U true JPS6330021U (en) 1988-02-27

Family

ID=31010178

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12116686U Pending JPS6330021U (en) 1986-08-07 1986-08-07

Country Status (1)

Country Link
JP (1) JPS6330021U (en)

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