JPS6285028U - - Google Patents
Info
- Publication number
- JPS6285028U JPS6285028U JP17722485U JP17722485U JPS6285028U JP S6285028 U JPS6285028 U JP S6285028U JP 17722485 U JP17722485 U JP 17722485U JP 17722485 U JP17722485 U JP 17722485U JP S6285028 U JPS6285028 U JP S6285028U
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- clock
- frequency divider
- output signal
- clock pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010363 phase shift Effects 0.000 claims description 2
- 230000000630 rising effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 1
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Manipulation Of Pulses (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Description
第１図は本考案の実施例を示すブロツク図であ
り、第２図は第１図に示す実施例回路における各
部の動作をあらわしている動作波形図である。第
３図は移相回路に使用する積分あるいは微分回路
の従来例を示す回路図である。
２……演算増幅器、３……コンデンサ、４……
抵抗、１１……クロツク発振器、１２……第１分
周器、１３……カウンタ回路、１４……第２分周
器。
FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is an operation waveform diagram showing the operation of each part in the embodiment circuit shown in FIG. FIG. 3 is a circuit diagram showing a conventional example of an integrating or differentiating circuit used in a phase shift circuit. 2... operational amplifier, 3... capacitor, 4...
Resistor, 11... Clock oscillator, 12... First frequency divider, 13... Counter circuit, 14... Second frequency divider.
Claims (1)
発振器と、このクロツクパルスを入力してクロツ
ク周波数より低い所望の一定周波数を出力する第
１の分周器と、前記クロツク発振器からのクロツ
クパルスと第１分周器出力信号とを入力し、第１
分周器出力信号の立上り点または立下り点を起点
にして所定数のクロツクパルスをカウントするカ
ウンタ回路と、このカウンタ回路出力信号の周波
数を２分の１に分周する第２の分周器とで構成さ
れている移相回路。 a clock oscillator that oscillates a high-frequency clock pulse; a first frequency divider that receives the clock pulse and outputs a desired constant frequency lower than the clock frequency; and a clock pulse from the clock oscillator and a first frequency divider output signal. and enter the first
a counter circuit that counts a predetermined number of clock pulses starting from a rising point or a falling point of a frequency divider output signal; and a second frequency divider that divides the frequency of this counter circuit output signal by half. A phase shift circuit consisting of.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17722485U JPS6285028U (en) | 1985-11-18 | 1985-11-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17722485U JPS6285028U (en) | 1985-11-18 | 1985-11-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6285028U true JPS6285028U (en) | 1987-05-30 |
Family
ID=31118223
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17722485U Pending JPS6285028U (en) | 1985-11-18 | 1985-11-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6285028U (en) |
-
1985
- 1985-11-18 JP JP17722485U patent/JPS6285028U/ja active Pending
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