JPH0328832U - - Google Patents
Info
- Publication number
- JPH0328832U JPH0328832U JP8987789U JP8987789U JPH0328832U JP H0328832 U JPH0328832 U JP H0328832U JP 8987789 U JP8987789 U JP 8987789U JP 8987789 U JP8987789 U JP 8987789U JP H0328832 U JPH0328832 U JP H0328832U
- Authority
- JP
- Japan
- Prior art keywords
- oscillation
- pulse signal
- frequency
- oscillation circuit
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010355 oscillation Effects 0.000 claims description 13
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Manipulation Of Pulses (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
第１図は本考案の一実施例のブロツク図、第２
図は本考案の一実施例の要部の信号の波形図、第
３図は従来の一例のブロツク図である。
１……第１の発振回路、２……第２の発振回路
、３……Ｄフリツプフロツプ。
Fig. 1 is a block diagram of an embodiment of the present invention;
The figure is a waveform diagram of essential signals of an embodiment of the present invention, and FIG. 3 is a block diagram of a conventional example. 1...First oscillation circuit, 2...Second oscillation circuit, 3...D flip-flop.
Claims (1)
回路と、 前記第１の発振回路の発振パルス信号の周波数
に比し十分に小さい周波数分だけ前記第１の発振
回路の発振パルス信号の周波数とは異なる周波数
のパルス信号を発振する第２の発振回路と、 前記第２の発振回路の発振パルス信号の立ち上
がり、又は、立ち下がり時の前記第１の発振回路
の発振パルス信号レベルを保持し、該保持したレ
ベルの反転同期に応じた周波数の出力発振パルス
信号を出力する回路とを具備してなる発振器。[Claims for Utility Model Registration] A first oscillation circuit that oscillates a pulse signal of a constant frequency; and a first oscillation circuit that has a frequency that is sufficiently smaller than the frequency of the oscillation pulse signal of the first oscillation circuit. a second oscillation circuit that oscillates a pulse signal with a frequency different from the frequency of the oscillation pulse signal; and oscillation of the first oscillation circuit when the oscillation pulse signal of the second oscillation circuit rises or falls. An oscillator comprising a circuit that holds a pulse signal level and outputs an output oscillation pulse signal of a frequency corresponding to inversion synchronization of the held level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8987789U JPH0328832U (en) | 1989-07-31 | 1989-07-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8987789U JPH0328832U (en) | 1989-07-31 | 1989-07-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0328832U true JPH0328832U (en) | 1991-03-22 |
Family
ID=31639431
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8987789U Pending JPH0328832U (en) | 1989-07-31 | 1989-07-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0328832U (en) |
-
1989
- 1989-07-31 JP JP8987789U patent/JPH0328832U/ja active Pending
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