JPH01127019U - - Google Patents

Info

Publication number
JPH01127019U
JPH01127019U JP2451788U JP2451788U JPH01127019U JP H01127019 U JPH01127019 U JP H01127019U JP 2451788 U JP2451788 U JP 2451788U JP 2451788 U JP2451788 U JP 2451788U JP H01127019 U JPH01127019 U JP H01127019U
Authority
JP
Japan
Prior art keywords
output signal
circuit
oscillation circuit
level
noise removal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2451788U
Other languages
Japanese (ja)
Other versions
JPH067383Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP2451788U priority Critical patent/JPH067383Y2/en
Publication of JPH01127019U publication Critical patent/JPH01127019U/ja
Application granted granted Critical
Publication of JPH067383Y2 publication Critical patent/JPH067383Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の第1の実施例のブロツク図、
第2図は第1図に示された実施例の雑音除去回路
の一例を示す回路図、第3図は本考案の第2の実
施例のブロツク図、第4図は従来のクロツク発生
回路の一例を示すブロツク図である。 1A,1B……発振回路、2……雑音除去回路
、3……選択回路、4……分周回路、10A,1
0B……発振子、21……シフトレジスタ、22
……RSフリツプフロツプ、FF〜FF……
フリツプフロツプ、G……NORゲート、G
……ANDゲート、……インバータ。
FIG. 1 is a block diagram of the first embodiment of the present invention.
2 is a circuit diagram showing an example of the noise removal circuit of the embodiment shown in FIG. 1, FIG. 3 is a block diagram of the second embodiment of the present invention, and FIG. 4 is a circuit diagram of a conventional clock generation circuit. FIG. 2 is a block diagram showing an example. 1A, 1B...Oscillation circuit, 2...Noise removal circuit, 3...Selection circuit, 4...Frequency division circuit, 10A, 1
0B...Resonator, 21...Shift register, 22
...RS flip-flop, FF 1 ~ FF 3 ...
Flip-flop, G1 ...NOR gate, G2
...AND gate, 1 ...inverter.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 所定の周波数で発振する第1の発振回路と、こ
の第1の発振回路より十分高い周波数で発振する
第2の発振回路と、この第2の発振回路の出力信
号により前記第1の発振回路の出力信号を所定の
周期でサンプリングし、このサンプリングした隣
接する複数の信号のレベルが、共に第1のレベル
になつたとき出力信号を第1のレベルにセツトし
、共に第2のレベルになつたとき出力信号を第2
のレベルにセツトする雑音除去回路と、選択信号
により前記雑音除去回路の出力信号と前記第2の
発振回路の出力信号とを切換えて出力する選択回
路とを有することを特徴とするクロツク発生回路
A first oscillation circuit that oscillates at a predetermined frequency, a second oscillation circuit that oscillates at a sufficiently higher frequency than the first oscillation circuit, and an output signal of the second oscillation circuit that causes the first oscillation circuit to oscillate. The output signal is sampled at a predetermined period, and when the levels of a plurality of sampled adjacent signals both reach the first level, the output signal is set to the first level, and the output signal is set to the second level. When the output signal is the second
1. A clock generation circuit comprising: a noise removal circuit that sets the output signal to the level of the noise removal circuit; and a selection circuit that selects and outputs the output signal of the noise removal circuit and the output signal of the second oscillation circuit according to a selection signal.
JP2451788U 1988-02-25 1988-02-25 Clock generator Expired - Lifetime JPH067383Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2451788U JPH067383Y2 (en) 1988-02-25 1988-02-25 Clock generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2451788U JPH067383Y2 (en) 1988-02-25 1988-02-25 Clock generator

Publications (2)

Publication Number Publication Date
JPH01127019U true JPH01127019U (en) 1989-08-30
JPH067383Y2 JPH067383Y2 (en) 1994-02-23

Family

ID=31244430

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2451788U Expired - Lifetime JPH067383Y2 (en) 1988-02-25 1988-02-25 Clock generator

Country Status (1)

Country Link
JP (1) JPH067383Y2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0553677A (en) * 1991-08-26 1993-03-05 Nec Corp Oscillation circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0553677A (en) * 1991-08-26 1993-03-05 Nec Corp Oscillation circuit

Also Published As

Publication number Publication date
JPH067383Y2 (en) 1994-02-23

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