JPH0221823U

JPH0221823U -

Info

Publication number: JPH0221823U
Application number: JP9228288U
Authority: JP
Priority date: 1988-07-11
Filing date: 1988-07-11
Publication date: 1990-02-14

Description

[Brief explanation of drawings]

第１図は本考案の第１の実施例を示す回路図、
第２図は第１図に示された実施例をシフトレジス
タに適用したときの回路図、第３図は本考案の第
２の実施例を示す回路図、第４図は従来のシフト
レジスタ用フリツプフロツプの一例を示す回路図
、第５図は第４図に示されたシフトレジスタ用フ
リツプフロツプをシフトレジスタに適用したとき
の回路図である。１Ａ，１Ｂ…インバータ、２，２Ａ…フリツプ
フロツプ部、１０，１０Ａ…シフトレジスタ用フ
リツプフロツプ、２１Ａ〜２１Ｄ…トランスフア
ゲート、２２Ａ，２２Ｂ…増幅器、２３Ａ〜２３
Ｄ…インバータ、ＣＩ…クロツク入力端子、ＣＯ
…クロツク出力端子。 FIG. 1 is a circuit diagram showing a first embodiment of the present invention;
Fig. 2 is a circuit diagram when the embodiment shown in Fig. 1 is applied to a shift register, Fig. 3 is a circuit diagram showing a second embodiment of the present invention, and Fig. 4 is a circuit diagram for a conventional shift register. FIG. 5 is a circuit diagram showing an example of a flip-flop, and is a circuit diagram when the shift register flip-flop shown in FIG. 4 is applied to a shift register. 1A, 1B... Inverter, 2, 2A... Flip-flop unit, 10, 10A... Flip-flop for shift register, 21A-21D... Transfer gate, 22A, 22B... Amplifier, 23A-23
D...Inverter, CI...Clock input terminal, CO
...Clock output terminal.

Claims

[Scope of utility model registration request]

A clock input terminal for inputting a clock signal,
a first inverter that inverts the clock signal from the clock input terminal; a second inverter that inverts the output signal of the first inverter; and a clock output terminal connected to the output terminal of the second inverter. It has a data input terminal and a data output terminal, and is connected to at least two input terminals of the first and second inverters, and receives a clock signal input from the clock input terminal and data input from the data input terminal. A flip-flop for a shift register, comprising a flip-flop section that outputs data at a predetermined level determined from the data output terminal.