JPS59103279U - voltage level detection circuit - Google Patents

voltage level detection circuit

Info

Publication number
JPS59103279U
JPS59103279U JP20149582U JP20149582U JPS59103279U JP S59103279 U JPS59103279 U JP S59103279U JP 20149582 U JP20149582 U JP 20149582U JP 20149582 U JP20149582 U JP 20149582U JP S59103279 U JPS59103279 U JP S59103279U
Authority
JP
Japan
Prior art keywords
voltage level
detection circuit
level detection
voltage
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20149582U
Other languages
Japanese (ja)
Inventor
吉弘 松本
温 大久保
Original Assignee
富士電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士電機株式会社 filed Critical 富士電機株式会社
Priority to JP20149582U priority Critical patent/JPS59103279U/en
Publication of JPS59103279U publication Critical patent/JPS59103279U/en
Pending legal-status Critical Current

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  • Measurement Of Current Or Voltage (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はインバータ装置の一例を示す回路図、第2図は
従来の電圧レベル検出回路の一例を示す回路図、第3図
はこの考案の一実施例を示す回路図である。 TI、T2・・・・・・端子、12・・・・・・分圧回
路、17・・・・・・トランジスタ、R2,R3・・・
・・・抵抗、18−1.18−2・・・・・・フォトカ
プラ。
FIG. 1 is a circuit diagram showing an example of an inverter device, FIG. 2 is a circuit diagram showing an example of a conventional voltage level detection circuit, and FIG. 3 is a circuit diagram showing an embodiment of this invention. TI, T2... terminal, 12... voltage divider circuit, 17... transistor, R2, R3...
...Resistor, 18-1.18-2...Photocoupler.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 電圧を検出すべき2つの端子間に分圧回路を介してトラ
ンジスタを接続し、該トランジスタの出力側に接続され
た抵抗にフォトカプラを接続して、該トランジスタの入
力側に印加される電圧レベルに応じて上記フォトカプラ
を動作させることにより上記端子間の電圧を検出するこ
とを特徴とする電圧レベル検出回路。
A transistor is connected between the two terminals where the voltage is to be detected via a voltage divider circuit, and a photocoupler is connected to the resistor connected to the output side of the transistor to determine the voltage level applied to the input side of the transistor. A voltage level detection circuit characterized in that the voltage between the terminals is detected by operating the photocoupler in accordance with the above.
JP20149582U 1982-12-27 1982-12-27 voltage level detection circuit Pending JPS59103279U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20149582U JPS59103279U (en) 1982-12-27 1982-12-27 voltage level detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20149582U JPS59103279U (en) 1982-12-27 1982-12-27 voltage level detection circuit

Publications (1)

Publication Number Publication Date
JPS59103279U true JPS59103279U (en) 1984-07-11

Family

ID=30426989

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20149582U Pending JPS59103279U (en) 1982-12-27 1982-12-27 voltage level detection circuit

Country Status (1)

Country Link
JP (1) JPS59103279U (en)

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