JPS60116526U - Digital device reset circuit - Google Patents

Digital device reset circuit

Info

Publication number
JPS60116526U
JPS60116526U JP291484U JP291484U JPS60116526U JP S60116526 U JPS60116526 U JP S60116526U JP 291484 U JP291484 U JP 291484U JP 291484 U JP291484 U JP 291484U JP S60116526 U JPS60116526 U JP S60116526U
Authority
JP
Japan
Prior art keywords
circuit
time constant
reset circuit
digital device
device reset
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP291484U
Other languages
Japanese (ja)
Inventor
豊田 薫
寿和 恩田
Original Assignee
株式会社明電舎
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社明電舎 filed Critical 株式会社明電舎
Priority to JP291484U priority Critical patent/JPS60116526U/en
Publication of JPS60116526U publication Critical patent/JPS60116526U/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示す回路図、第2図は第1
図の回路動作を説明する為のタイムチャートである。 1・・・直流電源、2,6・・・抵抗、3,7・・・コ
ンデンサ、4,5・・・NAND回路、8,9・・・時
定数回路。
Fig. 1 is a circuit diagram showing one embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
3 is a time chart for explaining the operation of the circuit shown in the figure. 1... DC power supply, 2, 6... Resistor, 3, 7... Capacitor, 4, 5... NAND circuit, 8, 9... Time constant circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 第1抵抗および第1コンデンサを直列接続した第1時定
数回路と、第1および第2入力端に前記第1時定数回路
の出力電圧が印加される第1NAND回路と、第2抵抗
および第2フンデンサを直列接続して成り、前記第1N
AND回路の出力電圧が印加される第2時定数回路と、
前記第1時定数回路の出力が所定値以上であり且つ前記
第2時定数回路の出力が所定値以下であるときりセット
信号を出力する第2NAND回路とを備えたことを特徴
とするディジタル装置のリセット回路。
a first time constant circuit in which a first resistor and a first capacitor are connected in series; a first NAND circuit to which the output voltage of the first time constant circuit is applied to first and second input terminals; The first N
a second time constant circuit to which the output voltage of the AND circuit is applied;
and a second NAND circuit that outputs a threshold set signal when the output of the first time constant circuit is above a predetermined value and the output of the second time constant circuit is below a predetermined value. reset circuit.
JP291484U 1984-01-12 1984-01-12 Digital device reset circuit Pending JPS60116526U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP291484U JPS60116526U (en) 1984-01-12 1984-01-12 Digital device reset circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP291484U JPS60116526U (en) 1984-01-12 1984-01-12 Digital device reset circuit

Publications (1)

Publication Number Publication Date
JPS60116526U true JPS60116526U (en) 1985-08-07

Family

ID=30477038

Family Applications (1)

Application Number Title Priority Date Filing Date
JP291484U Pending JPS60116526U (en) 1984-01-12 1984-01-12 Digital device reset circuit

Country Status (1)

Country Link
JP (1) JPS60116526U (en)

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